Lines Matching +full:0 +full:x404
43 #define MGE_RX_DEFAULT_QUEUE 0
48 #define MGE_IC_RX 0
119 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg))
120 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val))
126 } while (0)
134 } while (0)
144 } while (0)
149 } while (0)
154 } while (0)
159 } while (0)
165 #define MGE_REG_PHYDEV 0x000
166 #define MGE_REG_SMI 0x004
168 #define MGE_SMI_WRITE (0 << 26)
172 #define MGE_SMI_MASK 0x1fffffff
173 #define MGE_SMI_DATA_MASK 0xffff
190 #define MGE_INT_CAUSE 0x080
191 #define MGE_INT_MASK 0x084
193 #define MGE_PORT_CONFIG 0x400
194 #define PORT_CONFIG_UPM (1 << 0) /* promiscuous */
208 #define MGE_PORT_EXT_CONFIG 0x404
209 #define MGE_MAC_ADDR_L 0x414
210 #define MGE_MAC_ADDR_H 0x418
212 #define MGE_SDMA_CONFIG 0x41c
213 #define MGE_SDMA_INT_ON_FRAME_BOUND (1 << 0)
216 #define MGE_SDMA_BURST_1_WORD 0x0
217 #define MGE_SDMA_BURST_2_WORD 0x1
218 #define MGE_SDMA_BURST_4_WORD 0x2
219 #define MGE_SDMA_BURST_8_WORD 0x3
220 #define MGE_SDMA_BURST_16_WORD 0x4
225 #define MGE_PORT_SERIAL_CTRL 0x43c
226 #define PORT_SERIAL_ENABLE (1 << 0) /* serial port enable */
232 #define PORT_SERIAL_NO_PAUSE_DIS 0x00
233 #define PORT_SERIAL_PAUSE_DIS 0x01
235 #define PORT_SERIAL_NO_JAM 0x00
236 #define PORT_SERIAL_JAM 0x01
242 #define PORT_SERIAL_MRU_1518 0x0
243 #define PORT_SERIAL_MRU_1522 0x1
244 #define PORT_SERIAL_MRU_1552 0x2
245 #define PORT_SERIAL_MRU_9022 0x3
246 #define PORT_SERIAL_MRU_9192 0x4
247 #define PORT_SERIAL_MRU_9700 0x5
253 #define MGE_PORT_STATUS 0x444
262 #define MGE_TX_QUEUE_CMD 0x448
263 #define MGE_ENABLE_TXQ (1 << 0)
267 #define MGE_PORT_SERIAL_CTRL1 0x44c
277 #define MGE_COLLISION_LIMIT(val) (((val) & 0x3f) << 16)
280 #define MGE_PORT_INT_CAUSE 0x460
281 #define MGE_PORT_INT_MASK 0x468
282 #define MGE_PORT_INT_RX (1 << 0)
289 #define MGE_PORT_INT_CAUSE_EXT 0x464
290 #define MGE_PORT_INT_MASK_EXT 0x46C
291 #define MGE_PORT_INT_EXT_TXBUF0 (1 << 0)
300 #define MGE_RX_FIFO_URGENT_TRSH 0x470
301 #define MGE_TX_FIFO_URGENT_TRSH 0x474
303 #define MGE_FIXED_PRIO_CONF 0x4dc
306 #define MGE_RX_CUR_DESC_PTR(q) (0x60c + ((q)<<4))
308 #define MGE_RX_QUEUE_CMD 0x680
309 #define MGE_ENABLE_RXQ(q) (1 << ((q) & 0x7))
310 #define MGE_ENABLE_RXQ_ALL (0xff)
311 #define MGE_DISABLE_RXQ(q) (1 << (((q) & 0x7) + 8))
312 #define MGE_DISABLE_RXQ_ALL (0xff00)
314 #define MGE_TX_CUR_DESC_PTR 0x6c0
316 #define MGE_TX_TOKEN_COUNT(q) (0x700 + ((q)<<4))
317 #define MGE_TX_TOKEN_CONF(q) (0x704 + ((q)<<4))
318 #define MGE_TX_ARBITER_CONF(q) (0x704 + ((q)<<4))
321 #define MGE_DA_FILTER_SPEC_MCAST(i) (0x1400 + ((i) << 2))
322 #define MGE_DA_FILTER_OTH_MCAST(i) (0x1500 + ((i) << 2))
325 #define MGE_DA_FILTER_UCAST(i) (0x1600 + ((i) << 2))
341 #define MGE_TX_IP_HDR_SIZE(size) ((size << 11) & 0xFFFF)
344 #define MGE_ERR_SUMMARY (1 << 0)
347 #define MGE_RX_L4_PROTO_TCP (0 << 21)
366 #define MGE_TX_ERROR_LC (0 << 1) /* Late collision */
371 #define MGE_RX_ERROR_CE (0 << 1) /* CRC error */