Lines Matching +full:0 +full:xfc0000ff
169 { 0, 0 }
174 static int switch_attached = 0;
176 DRIVER_MODULE(mge, simplebus, mge_driver, 0, 0);
177 DRIVER_MODULE(miibus, mge, miibus_driver, 0, 0);
178 DRIVER_MODULE(mdio, mge, mdio_driver, 0, 0);
184 { SYS_RES_MEMORY, 0, RF_ACTIVE },
185 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
188 { -1, 0 }
222 if (timeout == 0) {
224 ret = ~0U;
237 if (timeout == 0) {
239 ret = ~0U;
268 if (timeout == 0) {
299 if (retries == 0)
325 if (retries == 0)
342 valid = 0;
343 for (i = 0; i < 6; i++)
344 if (lmac[i] != 0) {
361 addr[0] = (mac_h & 0xff000000) >> 24;
362 addr[1] = (mac_h & 0x00ff0000) >> 16;
363 addr[2] = (mac_h & 0x0000ff00) >> 8;
364 addr[3] = (mac_h & 0x000000ff);
365 addr[4] = (mac_l & 0x0000ff00) >> 8;
366 addr[5] = (mac_l & 0x000000ff);
375 return ((val & 0x3fff) << 4);
378 return ((val & 0xffff) << 4);
388 return ((val & 0x3fff) << 8);
391 return (((val & 0x8000) << 10) | ((val & 0x7fff) << 7));
402 sc->mge_mtu = 0x458;
403 sc->mge_tfut_ipg_max = 0x3FFF;
404 sc->mge_rx_ipg_max = 0x3FFF;
405 sc->mge_tx_arb_cfg = 0x000000FF;
406 sc->mge_tx_tok_cfg = 0x3FFFFFFF;
407 sc->mge_tx_tok_cnt = 0x3FFFFFFF;
411 sc->mge_hw_csum = 0;
427 mac_h = (if_mac[0] << 24)| (if_mac[1] << 16) |
428 (if_mac[2] << 8) | (if_mac[3] << 0);
441 last_byte &= 0xf;
446 for (i = 0; i < MGE_UCAST_REG_NUMBER; i++) {
450 MGE_WRITE(sc, MGE_DA_FILTER_UCAST(i), 0);
469 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
474 for (i = 0; i < MGE_UCAST_REG_NUMBER; i++)
482 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
483 MGE_WRITE(sc, MGE_DA_FILTER_SPEC_MCAST(i), 0);
484 MGE_WRITE(sc, MGE_DA_FILTER_OTH_MCAST(i), 0);
533 return (0);
544 desc_paddr = 0;
545 for (i = size - 1; i >= 0; i--) {
578 1, 0, /* alignment, boundary */
583 MCLBYTES, 0, /* maxsegsz, flags */
592 for (i = 0; i < size; i++) {
594 error = bus_dmamap_create(*buffer_tag, 0, &dw->buffer_dmap);
604 return (0);
615 16, 0, /* alignment, boundary */
620 sizeof(struct mge_desc), 0, /* maxsegsz, flags */
630 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
636 sc->tx_desc_start = sc->mge_tx_desc[0].mge_desc_paddr;
637 sc->rx_desc_start = sc->mge_rx_desc[0].mge_desc_paddr;
639 return (0);
649 for (i = 0; i < size; i++) {
680 mge_free_desc(sc, sc->mge_tx_desc, MGE_TX_DESC_NUM, sc->mge_tx_dtag, 0);
702 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
708 sc->rx_desc_start = sc->mge_rx_desc[0].mge_desc_paddr;
709 sc->rx_desc_curr = 0;
726 int rx_npkts = 0;
772 phy = 0;
774 if (fdt_get_phyaddr(sc->node, sc->dev, &phy, (void **)&sc->phy_sc) == 0) {
780 sc->phy_attached = 0;
784 if (fdt_find_compatible(sc->node, "mrvl,sw", 1) != 0) {
790 sc->switch_attached = 0;
793 if (device_get_unit(dev) == 0) {
821 sc->tx_desc_curr = 0;
822 sc->rx_desc_curr = 0;
823 sc->tx_desc_used_idx = 0;
824 sc->tx_desc_used_count = 0;
838 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0);
845 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
862 mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
877 ifmedia_init(&sc->mge_ifmedia, 0,
882 0, NULL);
892 NULL, *mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i)].handler,
896 mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i)].description);
908 return (0);
927 for (i = 0; i < sc->mge_intr_cnt; ++i) {
935 mge_intrs[(sc->mge_intr_cnt == 1 ? 0 : i + 1)].description);
954 if (device_get_unit(dev) == 0)
957 return (0);
1042 return (0);
1074 mge_intrs_ctrl(sc, 0);
1084 MGE_WRITE(sc, MGE_FIXED_PRIO_CONF, MGE_FIXED_PRIO_EN(0));
1088 MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(0), sc->mge_tx_tok_cnt);
1089 MGE_WRITE(sc, MGE_TX_TOKEN_CONF(0), sc->mge_tx_tok_cfg);
1090 MGE_WRITE(sc, MGE_TX_ARBITER_CONF(0), sc->mge_tx_arb_cfg);
1094 MGE_WRITE(sc, MGE_TX_TOKEN_COUNT(i), 0);
1095 MGE_WRITE(sc, MGE_TX_TOKEN_CONF(i), 0);
1096 MGE_WRITE(sc, MGE_TX_ARBITER_CONF(i), 0);
1100 MGE_WRITE(sc, sc->mge_mtu, 0);
1104 PORT_CONFIG_RXCS | PORT_CONFIG_DFLT_RXQ(0) |
1105 PORT_CONFIG_ARO_RXQ(0));
1106 MGE_WRITE(sc, MGE_PORT_EXT_CONFIG , 0x0);
1127 MGE_WRITE(sc, MGE_TX_FIFO_URGENT_TRSH, 0x0);
1134 sc->tx_desc_curr = 0;
1135 sc->rx_desc_curr = 0;
1136 sc->tx_desc_used_idx = 0;
1137 sc->tx_desc_used_count = 0;
1140 for (i = 0; i < MGE_RX_DESC_NUM; i++) {
1155 count = 0x100000;
1161 if (--count == 0) {
1178 mge_intrs_ctrl(sc, 0);
1184 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, 0);
1185 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
1186 sc->wd_timer = 0;
1304 int rx_npkts = 0;
1308 while (count != 0) {
1316 if ((status & MGE_DMA_OWNED) != 0)
1327 0, ifp, NULL);
1348 dw->mge_desc->byte_count = 0;
1354 if (count > 0)
1405 int send = 0;
1410 sc->wd_timer = 0;
1449 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
1461 error = 0;
1496 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
1497 if_setcapenablebit(ifp, IFCAP_HWCSUM & ifr->ifr_reqcap, 0);
1501 if_sethwassist(ifp, 0);
1511 mge_intrs_ctrl(sc, 0);
1512 if_setcapenablebit(ifp, IFCAP_POLLING, 0);
1518 if_setcapenablebit(ifp, 0, IFCAP_POLLING);
1531 return (0);
1542 return 0;
1569 return (0);
1591 return (0);
1610 return (0);
1631 if (error != 0) {
1646 for (seg = 0; seg < nsegs; seg++) {
1650 dw->mge_desc->cmd_status = 0;
1651 if (seg == 0)
1663 return (0);
1699 if (sc->wd_timer == 0 || --sc->wd_timer) {
1727 uint32_t reg_val, queued = 0;
1745 if (M_WRITABLE(m0) == 0) {
1763 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
1767 if (mge_encap(sc, m0) != 0)
1793 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0)
1800 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
1801 sc->wd_timer = 0;
1804 mge_intrs_ctrl(sc, 0);
1839 count = 0x100000;
1848 if (count == 0)
1863 return (0);
1870 int csum_flags = 0;
1876 if ((bufsize & MGE_RX_IP_FRAGMENT) == 0 &&
1880 frame->m_pkthdr.csum_data = 0xFFFF;
1893 int cmd_status = 0;
1897 if (csum_flags != 0) {
1942 MGE_WRITE(sc, MGE_INT_CAUSE, 0x0);
1943 MGE_WRITE(sc, MGE_INT_MASK, 0x0);
1945 MGE_WRITE(sc, MGE_PORT_INT_CAUSE, 0x0);
1946 MGE_WRITE(sc, MGE_PORT_INT_CAUSE_EXT, 0x0);
1948 MGE_WRITE(sc, MGE_PORT_INT_MASK, 0x0);
1949 MGE_WRITE(sc, MGE_PORT_INT_MASK_EXT, 0x0);
1956 uint8_t crc = 0;
1958 0x00, 0x07, 0x0E, 0x09, 0x1C, 0x1B, 0x12, 0x15,
1959 0x38, 0x3F, 0x36, 0x31, 0x24, 0x23, 0x2A, 0x2D,
1960 0x70, 0x77, 0x7E, 0x79, 0x6C, 0x6B, 0x62, 0x65,
1961 0x48, 0x4F, 0x46, 0x41, 0x54, 0x53, 0x5A, 0x5D,
1962 0xE0, 0xE7, 0xEE, 0xE9, 0xFC, 0xFB, 0xF2, 0xF5,
1963 0xD8, 0xDF, 0xD6, 0xD1, 0xC4, 0xC3, 0xCA, 0xCD,
1964 0x90, 0x97, 0x9E, 0x99, 0x8C, 0x8B, 0x82, 0x85,
1965 0xA8, 0xAF, 0xA6, 0xA1, 0xB4, 0xB3, 0xBA, 0xBD,
1966 0xC7, 0xC0, 0xC9, 0xCE, 0xDB, 0xDC, 0xD5, 0xD2,
1967 0xFF, 0xF8, 0xF1, 0xF6, 0xE3, 0xE4, 0xED, 0xEA,
1968 0xB7, 0xB0, 0xB9, 0xBE, 0xAB, 0xAC, 0xA5, 0xA2,
1969 0x8F, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9D, 0x9A,
1970 0x27, 0x20, 0x29, 0x2E, 0x3B, 0x3C, 0x35, 0x32,
1971 0x1F, 0x18, 0x11, 0x16, 0x03, 0x04, 0x0D, 0x0A,
1972 0x57, 0x50, 0x59, 0x5E, 0x4B, 0x4C, 0x45, 0x42,
1973 0x6F, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7D, 0x7A,
1974 0x89, 0x8E, 0x87, 0x80, 0x95, 0x92, 0x9B, 0x9C,
1975 0xB1, 0xB6, 0xBF, 0xB8, 0xAD, 0xAA, 0xA3, 0xA4,
1976 0xF9, 0xFE, 0xF7, 0xF0, 0xE5, 0xE2, 0xEB, 0xEC,
1977 0xC1, 0xC6, 0xCF, 0xC8, 0xDD, 0xDA, 0xD3, 0xD4,
1978 0x69, 0x6E, 0x67, 0x60, 0x75, 0x72, 0x7B, 0x7C,
1979 0x51, 0x56, 0x5F, 0x58, 0x4D, 0x4A, 0x43, 0x44,
1980 0x19, 0x1E, 0x17, 0x10, 0x05, 0x02, 0x0B, 0x0C,
1981 0x21, 0x26, 0x2F, 0x28, 0x3D, 0x3A, 0x33, 0x34,
1982 0x4E, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5C, 0x5B,
1983 0x76, 0x71, 0x78, 0x7F, 0x6A, 0x6D, 0x64, 0x63,
1984 0x3E, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2C, 0x2B,
1985 0x06, 0x01, 0x08, 0x0F, 0x1A, 0x1D, 0x14, 0x13,
1986 0xAE, 0xA9, 0xA0, 0xA7, 0xB2, 0xB5, 0xBC, 0xBB,
1987 0x96, 0x91, 0x98, 0x9F, 0x8A, 0x8D, 0x84, 0x83,
1988 0xDE, 0xD9, 0xD0, 0xD7, 0xC2, 0xC5, 0xCC, 0xCB,
1989 0xE6, 0xE1, 0xE8, 0xEF, 0xFA, 0xFD, 0xF4, 0xF3
2006 static const uint8_t special[5] = { 0x01, 0x00, 0x5E, 0x00, 0x00 };
2013 if (memcmp(mac, special, sizeof(special)) == 0) {
2015 ctx->smt[i >> 2] |= v << ((i & 0x03) << 3);
2018 ctx->omt[i >> 2] |= v << ((i & 0x03) << 3);
2032 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++)
2036 memset(&ctx, 0, sizeof(ctx));
2040 for (i = 0; i < MGE_MCAST_REG_NUMBER; i++) {
2082 error = sysctl_handle_int(oidp, &time, 0, req);
2083 if (error != 0)
2096 return(0);
2109 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "MGE Interrupts coalescing");
2126 return (0);