Lines Matching +full:0 +full:x01010000
72 #define MFI_IMSG0 0x10 /* Inbound message 0 */
73 #define MFI_IMSG1 0x14 /* Inbound message 1 */
74 #define MFI_OMSG0 0x18 /* Outbound message 0 */
75 #define MFI_OMSG1 0x1c /* Outbound message 1 */
76 #define MFI_IDB 0x20 /* Inbound doorbell */
77 #define MFI_ISTS 0x24 /* Inbound interrupt status */
78 #define MFI_IMSK 0x28 /* Inbound interrupt mask */
79 #define MFI_ODB 0x2c /* Outbound doorbell */
80 #define MFI_OSTS 0x30 /* Outbound interrupt status */
81 #define MFI_OMSK 0x34 /* Outbound interrupt mask */
82 #define MFI_IQP 0x40 /* Inbound queue port */
83 #define MFI_OQP 0x44 /* Outbound queue port */
89 #define MFI_RFPI 0x48 /* reply_free_post_host_index */
90 #define MFI_RPI 0x6c /* reply_post_host_index */
91 #define MFI_ILQP 0xc0 /* inbound_low_queue_port */
92 #define MFI_IHQP 0xc4 /* inbound_high_queue_port */
97 #define MFI_ODR0 0x9c /* outbound doorbell register0 */
98 #define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */
99 #define MFI_OSP0 0xb0 /* outbound scratch pad0 */
100 #define MFI_1078_EIM 0x80000004 /* 1078 enable interrupt mask */
101 #define MFI_RMI 0x2 /* reply message interrupt */
102 #define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */
103 #define MFI_ODC 0x4 /* outbound doorbell change interrupt */
106 #define MFI_WSR 0x004 /* write sequence register */
107 #define MFI_HDR 0x008 /* host diagnostic register */
108 #define MFI_RSR 0x3c3 /* Reset Status Register */
113 #define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */
114 #define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */
119 #define MFI_SKINNY_IDB 0x00 /* Inbound doorbell is at 0x00 for skinny */
120 #define MFI_IQPL 0x000000c0
121 #define MFI_IQPH 0x000000c4
122 #define MFI_SKINNY_RM 0x00000001 /* reply skinny message interrupt */
125 #define MFI_OSTS_INTR_VALID 0x00000002
128 #define MFI_FIRMWARE_STATE_CHANGE 0x00000002
129 #define MFI_STATE_CHANGE_INTERRUPT 0x00000004 /* MFI state change interrrupt */
134 #define MFI_FWSTATE_MASK 0xf0000000
135 #define MFI_FWSTATE_UNDEFINED 0x00000000
136 #define MFI_FWSTATE_BB_INIT 0x10000000
137 #define MFI_FWSTATE_FW_INIT 0x40000000
138 #define MFI_FWSTATE_WAIT_HANDSHAKE 0x60000000
139 #define MFI_FWSTATE_FW_INIT_2 0x70000000
140 #define MFI_FWSTATE_DEVICE_SCAN 0x80000000
141 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000
142 #define MFI_FWSTATE_FLUSH_CACHE 0xa0000000
143 #define MFI_FWSTATE_READY 0xb0000000
144 #define MFI_FWSTATE_OPERATIONAL 0xc0000000
145 #define MFI_FWSTATE_FAULT 0xf0000000
146 #define MFI_FWSTATE_MAXSGL_MASK 0x00ff0000
147 #define MFI_FWSTATE_MAXCMD_MASK 0x0000ffff
148 #define MFI_FWSTATE_HOSTMEMREQD_MASK 0x08000000
149 #define MFI_FWSTATE_BOOT_MESSAGE_PENDING 0x90000000
150 #define MFI_RESET_REQUIRED 0x00000001
153 #define MFI_FWSTATE_TB_MASK 0xf0000000
154 #define MFI_FWSTATE_TB_RESET 0x00000000
155 #define MFI_FWSTATE_TB_READY 0x10000000
156 #define MFI_FWSTATE_TB_OPERATIONAL 0x20000000
157 #define MFI_FWSTATE_TB_FAULT 0x40000000
163 #define MFI_FWINIT_ABORT 0x00000000 /* Abort all pending commands */
164 #define MFI_FWINIT_READY 0x00000002 /* Move from operational to ready */
165 #define MFI_FWINIT_MFIMODE 0x00000004 /* unknown */
166 #define MFI_FWINIT_CLEAR_HANDSHAKE 0x00000008 /* Respond to WAIT_HANDSHAKE */
167 #define MFI_FWINIT_HOTPLUG 0x00000010
170 #define MFI_STOP_ADP 0x00000020
171 #define MFI_ADP_RESET 0x00000040
172 #define DIAG_WRITE_ENABLE 0x00000080
173 #define DIAG_RESET_ADAPTER 0x00000004
177 MFI_CMD_INIT = 0x00,
190 MFI_DCMD_CTRL_GETINFO = 0x01010000,
191 MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC =0x0100e100,
192 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201,
193 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202,
194 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000,
195 MFI_DCMD_CTRL_GET_PROPS = 0x01020100,
196 MFI_DCMD_CTRL_SET_PROPS = 0x01020200,
197 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000,
198 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100,
199 MFI_DCMD_CTRL_EVENT_GET = 0x01040300,
200 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500,
201 MFI_DCMD_PR_GET_STATUS = 0x01070100,
202 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200,
203 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300,
204 MFI_DCMD_PR_START = 0x01070400,
205 MFI_DCMD_PR_STOP = 0x01070500,
206 MFI_DCMD_TIME_SECS_GET = 0x01080201,
207 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100,
208 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200,
209 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300,
210 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400,
211 MFI_DCMD_PD_GET_LIST = 0x02010000,
212 MFI_DCMD_PD_LIST_QUERY = 0x02010100,
213 MFI_DCMD_PD_GET_INFO = 0x02020000,
214 MFI_DCMD_PD_STATE_SET = 0x02030100,
215 MFI_DCMD_PD_REBUILD_START = 0x02040100,
216 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200,
217 MFI_DCMD_PD_CLEAR_START = 0x02050100,
218 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200,
219 MFI_DCMD_PD_GET_PROGRESS = 0x02060000,
220 MFI_DCMD_PD_LOCATE_START = 0x02070100,
221 MFI_DCMD_PD_LOCATE_STOP = 0x02070200,
222 MFI_DCMD_LD_MAP_GET_INFO = 0x0300e101,
223 MFI_DCMD_LD_SYNC = 0x0300e102,
224 MFI_DCMD_LD_GET_LIST = 0x03010000,
225 MFI_DCMD_LD_GET_INFO = 0x03020000,
226 MFI_DCMD_LD_GET_PROP = 0x03030000,
227 MFI_DCMD_LD_SET_PROP = 0x03040000,
228 MFI_DCMD_LD_INIT_START = 0x03060100,
229 MFI_DCMD_LD_DELETE = 0x03090000,
230 MFI_DCMD_CFG_READ = 0x04010000,
231 MFI_DCMD_CFG_ADD = 0x04020000,
232 MFI_DCMD_CFG_CLEAR = 0x04030000,
233 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000,
234 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000,
235 MFI_DCMD_CFG_FOREIGN_SCAN = 0x04060100,
236 MFI_DCMD_CFG_FOREIGN_DISPLAY = 0x04060200,
237 MFI_DCMD_CFG_FOREIGN_PREVIEW = 0x04060300,
238 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400,
239 MFI_DCMD_CFG_FOREIGN_CLEAR = 0x04060500,
240 MFI_DCMD_BBU_GET_STATUS = 0x05010000,
241 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000,
242 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000,
243 MFI_DCMD_BBU_START_LEARN = 0x05040000,
244 MFI_DCMD_BBU_GET_PROP = 0x05050100,
245 MFI_DCMD_BBU_SET_PROP = 0x05050200,
246 MFI_DCMD_CLUSTER = 0x08000000,
247 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100,
248 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200
252 #define MFI_FLUSHCACHE_CTRL 0x01
253 #define MFI_FLUSHCACHE_DISK 0x02
256 #define MFI_SHUTDOWN_SPINDOWN 0x01
261 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
262 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
263 #define MFI_FRAME_SGL32 0x0000
264 #define MFI_FRAME_SGL64 0x0002
265 #define MFI_FRAME_SENSE32 0x0000
266 #define MFI_FRAME_SENSE64 0x0004
267 #define MFI_FRAME_DIR_NONE 0x0000
268 #define MFI_FRAME_DIR_WRITE 0x0008
269 #define MFI_FRAME_DIR_READ 0x0010
270 #define MFI_FRAME_DIR_BOTH 0x0018
271 #define MFI_FRAME_IEEE_SGL 0x0020
301 #define MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
302 #define MPI2_FUNCTION_LD_IO_REQUEST 0xF1
310 MFI_STAT_OK = 0x00,
326 MFI_STAT_FLASH_ERROR = 0x10,
342 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
358 MFI_STAT_SHUTDOWN_FAILED = 0x30,
370 MFI_STAT_INVALID_STATUS = 0xFF
376 MFI_EVT_CLASS_INFO = 0,
384 MFI_EVT_LOCALE_LD = 0x0001,
385 MFI_EVT_LOCALE_PD = 0x0002,
386 MFI_EVT_LOCALE_ENCL = 0x0004,
387 MFI_EVT_LOCALE_BBU = 0x0008,
388 MFI_EVT_LOCALE_SAS = 0x0010,
389 MFI_EVT_LOCALE_CTRL = 0x0020,
390 MFI_EVT_LOCALE_CONFIG = 0x0040,
391 MFI_EVT_LOCALE_CLUSTER = 0x0080,
392 MFI_EVT_LOCALE_ALL = 0xffff
396 MR_EVT_ARGS_NONE = 0x00,
419 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
420 #define MR_EVT_PD_REMOVED 0x0070
421 #define MR_EVT_PD_INSERTED 0x005b
422 #define MR_EVT_LD_CHANGE 0x0051
425 MR_LD_CACHE_WRITE_BACK = 0x01,
426 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02,
427 MR_LD_CACHE_READ_AHEAD = 0x04,
428 MR_LD_CACHE_READ_ADAPTIVE = 0x08,
429 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10,
430 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20,
431 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40
433 #define MR_LD_CACHE_MASK 0x7f
435 #define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0
439 #define MR_LD_CACHE_POLICY_WRITE_THROUGH 0
443 #define MR_LD_CACHE_POLICY_IO_DIRECT 0
446 MR_PD_CACHE_UNCHANGED = 0,
452 MR_PD_QUERY_TYPE_ALL = 0,
521 #define MFI_FRAME_DATAOUT 0x08
522 #define MFI_FRAME_DATAIN 0x10
672 * 0 - use auto detect logic of backplanes like SGPIO, i2c SEP using
690 /* set TRUE to disable copyBack (0=copback enabled) */
714 * 0=READ only, 1=5%, 2=10%, 3=15% and so on.
717 /* # of idle minutes before device is spun down (0=use FW defaults) */
734 #define MFI_INFO_HOST_PCIX 0x01
735 #define MFI_INFO_HOST_PCIE 0x02
736 #define MFI_INFO_HOST_ISCSI 0x04
737 #define MFI_INFO_HOST_SAS3G 0x08
746 #define MFI_INFO_DEV_SPI 0x01
747 #define MFI_INFO_DEV_SAS3G 0x02
748 #define MFI_INFO_DEV_SATA1 0x04
749 #define MFI_INFO_DEV_SATA3G 0x08
831 #define MFI_INFO_HW_BBU 0x01
832 #define MFI_INFO_HW_ALARM 0x02
833 #define MFI_INFO_HW_NVRAM 0x04
834 #define MFI_INFO_HW_UART 0x08
856 #define MFI_INFO_RAID_0 0x01
857 #define MFI_INFO_RAID_1 0x02
858 #define MFI_INFO_RAID_5 0x04
859 #define MFI_INFO_RAID_1E 0x08
860 #define MFI_INFO_RAID_6 0x10
863 #define MFI_INFO_AOPS_RBLD_RATE 0x0001
864 #define MFI_INFO_AOPS_CC_RATE 0x0002
865 #define MFI_INFO_AOPS_BGI_RATE 0x0004
866 #define MFI_INFO_AOPS_RECON_RATE 0x0008
867 #define MFI_INFO_AOPS_PATROL_RATE 0x0010
868 #define MFI_INFO_AOPS_ALARM_CONTROL 0x0020
869 #define MFI_INFO_AOPS_CLUSTER_SUPPORTED 0x0040
870 #define MFI_INFO_AOPS_BBU 0x0080
871 #define MFI_INFO_AOPS_SPANNING_ALLOWED 0x0100
872 #define MFI_INFO_AOPS_DEDICATED_SPARES 0x0200
873 #define MFI_INFO_AOPS_REVERTIBLE_SPARES 0x0400
874 #define MFI_INFO_AOPS_FOREIGN_IMPORT 0x0800
875 #define MFI_INFO_AOPS_SELF_DIAGNOSTIC 0x1000
876 #define MFI_INFO_AOPS_MIXED_ARRAY 0x2000
877 #define MFI_INFO_AOPS_GLOBAL_SPARES 0x4000
880 #define MFI_INFO_LDOPS_READ_POLICY 0x01
881 #define MFI_INFO_LDOPS_WRITE_POLICY 0x02
882 #define MFI_INFO_LDOPS_IO_POLICY 0x04
883 #define MFI_INFO_LDOPS_ACCESS_POLICY 0x08
884 #define MFI_INFO_LDOPS_DISK_CACHE_POLICY 0x10
893 #define MFI_INFO_PDOPS_FORCE_ONLINE 0x01
894 #define MFI_INFO_PDOPS_FORCE_OFFLINE 0x02
895 #define MFI_INFO_PDOPS_FORCE_REBUILD 0x04
898 #define MFI_INFO_PDMIX_SAS 0x01
899 #define MFI_INFO_PDMIX_SATA 0x02
900 #define MFI_INFO_PDMIX_ENCL 0x04
901 #define MFI_INFO_PDMIX_LD 0x08
902 #define MFI_INFO_PDMIX_SATA_CLUSTER 0x10
907 char package_version[0x60];
908 uint8_t pad[0x800 - 0x6a0];
1105 #define MFI_PD_PROGRESS_REBUILD (1<<0)
1154 uint8_t scsi_dev_type; /* 0 = disk */
1167 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00,
1168 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01,
1169 MFI_PD_STATE_HOT_SPARE = 0x02,
1170 MFI_PD_STATE_OFFLINE = 0x10,
1171 MFI_PD_STATE_FAILED = 0x11,
1172 MFI_PD_STATE_REBUILD = 0x14,
1173 MFI_PD_STATE_ONLINE = 0x18,
1174 MFI_PD_STATE_COPYBACK = 0x20,
1175 MFI_PD_STATE_SYSTEM = 0x40
1205 MFI_LD_ACCESS_RW = 0,
1212 MFI_LD_STATE_OFFLINE = 0,
1238 #define MFI_LD_PARAMS_INIT_NO 0
1249 #define MFI_LD_PROGRESS_CC (1<<0)
1289 #define MFI_SPARE_DEDICATED (1 << 0)
1305 union mfi_pd_ref ref; /* 0xffff == missing drive */
1323 struct mfi_array array[0];
1324 struct mfi_ld_config ld[0];
1325 struct mfi_spare spare[0];
1394 #define MFI_BBU_TYPE_NONE 0
1402 #define MFI_BBU_STATE_PACK_MISSING (1 << 0)
1417 MFI_PR_STATE_STOPPED = 0,
1420 MFI_PR_STATE_ABORTED = 0xff
1431 MFI_PR_OPMODE_AUTO = 0,
1453 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
1456 uint16_t resvd0; /* 0x00 - 0x01 */
1457 uint16_t timeoutValue; /* 0x02 - 0x03 */
1460 uint16_t TargetID; /* 0x06 - 0x07 */
1462 uint64_t RegLockLBA; /* 0x08 - 0x0F */
1464 uint32_t RegLockLength; /* 0x10 - 0x13 */
1466 uint16_t SMID; /* 0x14 - 0x15 nextLMId */
1467 uint8_t exStatus; /* 0x16 */
1468 uint8_t Status; /* 0x17 status */
1470 uint8_t RAIDFlags; /* 0x18 */
1471 uint8_t numSGE; /* 0x19 numSge */
1472 uint16_t configSeqNum; /* 0x1A - 0x1B */
1473 uint8_t spanArm; /* 0x1C */
1474 uint8_t resvd2[3]; /* 0x1D - 0x1F */
1483 #define NA_MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
1484 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */
1485 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
1486 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */
1487 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */
1488 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */
1489 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */
1490 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */
1491 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */
1492 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */
1493 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */
1494 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */
1495 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */
1496 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */
1497 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */
1498 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */
1499 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */
1500 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */
1501 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */
1502 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */
1503 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */
1504 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */
1505 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */
1506 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */
1507 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */
1508 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */
1509 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */
1510 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */
1511 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */
1512 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */
1515 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
1516 #define MPI2_FUNCTION_HANDSHAKE (0x42)
1524 #define MPI2_VERSION_MAJOR (0x02)
1525 #define MPI2_VERSION_MINOR (0x00)
1526 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
1528 #define MPI2_VERSION_MINOR_MASK (0x00FF)
1529 #define MPI2_VERSION_MINOR_SHIFT (0)
1533 #define MPI2_VERSION_02_00 (0x0200)
1536 #define MPI2_HEADER_VERSION_UNIT (0x10)
1537 #define MPI2_HEADER_VERSION_DEV (0x00)
1538 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
1540 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
1541 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
1547 uint8_t WhoInit; /* 0x00 */
1548 uint8_t Reserved1; /* 0x01 */
1549 uint8_t ChainOffset; /* 0x02 */
1550 uint8_t Function; /* 0x03 */
1551 uint16_t Reserved2; /* 0x04 */
1552 uint8_t Reserved3; /* 0x06 */
1553 uint8_t MsgFlags; /* 0x07 */
1554 uint8_t VP_ID; /* 0x08 */
1555 uint8_t VF_ID; /* 0x09 */
1556 uint16_t Reserved4; /* 0x0A */
1557 uint16_t MsgVersion; /* 0x0C */
1558 uint16_t HeaderVersion; /* 0x0E */
1559 uint32_t Reserved5; /* 0x10 */
1560 uint16_t Reserved6; /* 0x14 */
1561 uint8_t Reserved7; /* 0x16 */
1562 uint8_t HostMSIxVectors; /* 0x17 */
1563 uint16_t Reserved8; /* 0x18 */
1564 uint16_t SystemRequestFrameSize; /* 0x1A */
1565 uint16_t ReplyDescriptorPostQueueDepth; /* 0x1C */
1566 uint16_t ReplyFreeQueueDepth; /* 0x1E */
1567 uint32_t SenseBufferAddressHigh; /* 0x20 */
1568 uint32_t SystemReplyAddressHigh; /* 0x24 */
1569 uint64_t SystemRequestFrameBaseAddress; /* 0x28 */
1570 uint64_t ReplyDescriptorPostQueueAddress;/* 0x30 */
1571 uint64_t ReplyFreeQueueAddress; /* 0x38 */
1572 uint64_t TimeStamp; /* 0x40 */
1576 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
1577 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
1578 #define MPI2_WHOINIT_ROM_BIOS (0x02)
1579 #define MPI2_WHOINIT_PCI_PEER (0x03)
1580 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
1581 #define MPI2_WHOINIT_MANUFACTURER (0x05)
1625 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1629 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1633 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1634 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1638 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1639 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1640 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1641 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1642 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1646 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1647 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1651 #define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000)
1654 #define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
1655 #define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
1656 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
1657 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
1658 #define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000)
1660 #define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800)
1663 #define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
1664 #define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
1665 #define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100)
1666 #define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
1667 #define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400)
1669 #define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0)
1670 #define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000)
1671 #define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040)
1672 #define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080)
1677 uint8_t CDB[20]; /* 0x00 */
1678 uint32_t PrimaryReferenceTag; /* 0x14 */
1679 uint16_t PrimaryApplicationTag; /* 0x18 */
1680 uint16_t PrimaryApplicationTagMask; /* 0x1A */
1681 uint32_t TransferLength; /* 0x1C */
1709 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1728 uint16_t DevHandle; /* 0x00 */
1729 uint8_t ChainOffset; /* 0x02 */
1730 uint8_t Function; /* 0x03 */
1731 uint16_t Reserved1; /* 0x04 */
1732 uint8_t Reserved2; /* 0x06 */
1733 uint8_t MsgFlags; /* 0x07 */
1734 uint8_t VP_ID; /* 0x08 */
1735 uint8_t VF_ID; /* 0x09 */
1736 uint16_t Reserved3; /* 0x0A */
1737 uint32_t SenseBufferLowAddress; /* 0x0C */
1738 uint16_t SGLFlags; /* 0x10 */
1739 uint8_t SenseBufferLength; /* 0x12 */
1740 uint8_t Reserved4; /* 0x13 */
1741 uint8_t SGLOffset0; /* 0x14 */
1742 uint8_t SGLOffset1; /* 0x15 */
1743 uint8_t SGLOffset2; /* 0x16 */
1744 uint8_t SGLOffset3; /* 0x17 */
1745 uint32_t SkipCount; /* 0x18 */
1746 uint32_t DataLength; /* 0x1C */
1747 uint32_t BidirectionalDataLength; /* 0x20 */
1748 uint16_t IoFlags; /* 0x24 */
1749 uint16_t EEDPFlags; /* 0x26 */
1750 uint32_t EEDPBlockSize; /* 0x28 */
1751 uint32_t SecondaryReferenceTag; /* 0x2C */
1752 uint16_t SecondaryApplicationTag; /* 0x30 */
1753 uint16_t ApplicationTagTranslationMask; /* 0x32 */
1754 uint8_t LUN[8]; /* 0x34 */
1755 uint32_t Control; /* 0x3C */
1756 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
1757 MPI2_SCSI_IO_VENDOR_UNIQUE RaidContext; /* 0x60 */
1758 MPI2_SGE_IO_UNION SGL; /* 0x80 */
1771 uint8_t RequestFlags; /* 0x00 */
1772 uint8_t MSIxIndex; /* 0x01 */
1773 uint16_t SMID; /* 0x02 */
1774 uint16_t LMID; /* 0x04 */
1778 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
1779 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
1780 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
1781 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
1782 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
1783 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
1785 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
1812 uint8_t ReplyFlags; /* 0x00 */
1813 uint8_t MSIxIndex; /* 0x01 */
1814 uint16_t SMID; /* 0x02 */
1818 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
1819 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
1820 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
1821 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
1822 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
1823 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
1824 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
1827 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
1828 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
1842 uint16_t TaskTag; /* 0x04 */
1843 uint16_t Reserved1; /* 0x06 */
1848 uint8_t SequenceNumber; /* 0x04 */
1849 uint8_t Reserved1; /* 0x04 */
1850 uint16_t IoIndex; /* 0x06 */
1855 uint8_t SequenceNumber; /* 0x04 */
1856 uint8_t Flags; /* 0x04 */
1857 uint16_t InitiatorDevHandle; /* 0x06 */
1858 uint16_t IoIndex; /* 0x06 */
1863 uint8_t SequenceNumber; /* 0x04 */
1864 uint32_t Reserved; /* 0x04 */