Lines Matching full:oct
45 lio_cn23xx_pf_soft_reset(struct octeon_device *oct) in lio_cn23xx_pf_soft_reset() argument
48 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); in lio_cn23xx_pf_soft_reset()
50 lio_dev_dbg(oct, "BIST enabled for CN23XX soft reset\n"); in lio_cn23xx_pf_soft_reset()
52 lio_write_csr64(oct, LIO_CN23XX_SLI_SCRATCH1, 0x1234ULL); in lio_cn23xx_pf_soft_reset()
55 lio_pci_readq(oct, LIO_CN23XX_RST_SOFT_RST); in lio_cn23xx_pf_soft_reset()
56 lio_pci_writeq(oct, 1, LIO_CN23XX_RST_SOFT_RST); in lio_cn23xx_pf_soft_reset()
61 if (lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH1)) { in lio_cn23xx_pf_soft_reset()
62 lio_dev_err(oct, "Soft reset failed\n"); in lio_cn23xx_pf_soft_reset()
66 lio_dev_dbg(oct, "Reset completed\n"); in lio_cn23xx_pf_soft_reset()
69 lio_write_csr64(oct, LIO_CN23XX_SLI_WIN_WR_MASK_REG, 0xFF); in lio_cn23xx_pf_soft_reset()
75 lio_cn23xx_pf_enable_error_reporting(struct octeon_device *oct) in lio_cn23xx_pf_enable_error_reporting() argument
79 regval = lio_read_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL); in lio_cn23xx_pf_enable_error_reporting()
84 lio_read_pci_cfg(oct, in lio_cn23xx_pf_enable_error_reporting()
87 lio_read_pci_cfg(oct, in lio_cn23xx_pf_enable_error_reporting()
89 lio_dev_err(oct, "PCI-E Fatal error detected;\n" in lio_cn23xx_pf_enable_error_reporting()
99 lio_dev_dbg(oct, "Enabling PCI-E error reporting..\n"); in lio_cn23xx_pf_enable_error_reporting()
100 lio_write_pci_cfg(oct, LIO_CN23XX_CFG_PCIE_DEVCTL, regval); in lio_cn23xx_pf_enable_error_reporting()
104 lio_cn23xx_pf_coprocessor_clock(struct octeon_device *oct) in lio_cn23xx_pf_coprocessor_clock() argument
112 return (((lio_pci_readq(oct, LIO_CN23XX_RST_BOOT) >> 24) & 0x3f) * 50); in lio_cn23xx_pf_coprocessor_clock()
116 lio_cn23xx_pf_get_oq_ticks(struct octeon_device *oct, uint32_t time_intr_in_us) in lio_cn23xx_pf_get_oq_ticks() argument
119 uint32_t oqticks_per_us = lio_cn23xx_pf_coprocessor_clock(oct); in lio_cn23xx_pf_get_oq_ticks()
121 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us; in lio_cn23xx_pf_get_oq_ticks()
140 lio_cn23xx_pf_setup_global_mac_regs(struct octeon_device *oct) in lio_cn23xx_pf_setup_global_mac_regs() argument
143 uint16_t mac_no = oct->pcie_port; in lio_cn23xx_pf_setup_global_mac_regs()
144 uint16_t pf_num = oct->pf_num; in lio_cn23xx_pf_setup_global_mac_regs()
147 lio_dev_dbg(oct, "%s: Using pcie port %d\n", __func__, mac_no); in lio_cn23xx_pf_setup_global_mac_regs()
151 lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)); in lio_cn23xx_pf_setup_global_mac_regs()
158 (oct->sriov_info.trs << LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS); in lio_cn23xx_pf_setup_global_mac_regs()
161 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num), in lio_cn23xx_pf_setup_global_mac_regs()
164 lio_dev_dbg(oct, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n", mac_no, in lio_cn23xx_pf_setup_global_mac_regs()
166 LIO_CAST64(lio_read_csr64(oct, in lio_cn23xx_pf_setup_global_mac_regs()
172 lio_cn23xx_pf_reset_io_queues(struct octeon_device *oct) in lio_cn23xx_pf_reset_io_queues() argument
179 srn = oct->sriov_info.pf_srn; in lio_cn23xx_pf_reset_io_queues()
180 ern = srn + oct->sriov_info.num_pf_rings; in lio_cn23xx_pf_reset_io_queues()
188 d64 = lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
191 lio_write_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
198 lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
203 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
209 lio_dev_err(oct, in lio_cn23xx_pf_reset_io_queues()
216 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in lio_cn23xx_pf_reset_io_queues()
219 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_reset_io_queues()
222 lio_dev_err(oct, "clearing the reset failed for qno: %u\n", in lio_cn23xx_pf_reset_io_queues()
232 lio_cn23xx_pf_setup_global_input_regs(struct octeon_device *oct) in lio_cn23xx_pf_setup_global_input_regs() argument
234 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_setup_global_input_regs()
240 pf_num = oct->pf_num; in lio_cn23xx_pf_setup_global_input_regs()
242 srn = oct->sriov_info.pf_srn; in lio_cn23xx_pf_setup_global_input_regs()
243 ern = srn + oct->sriov_info.num_pf_rings; in lio_cn23xx_pf_setup_global_input_regs()
245 if (lio_cn23xx_pf_reset_io_queues(oct)) in lio_cn23xx_pf_setup_global_input_regs()
255 reg_val = oct->pcie_port << in lio_cn23xx_pf_setup_global_input_regs()
260 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in lio_cn23xx_pf_setup_global_input_regs()
271 iq = oct->instr_queue[q_no]; in lio_cn23xx_pf_setup_global_input_regs()
278 lio_read_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no)); in lio_cn23xx_pf_setup_global_input_regs()
282 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in lio_cn23xx_pf_setup_global_input_regs()
290 lio_write_csr64(oct, inst_cnt_reg, in lio_cn23xx_pf_setup_global_input_regs()
291 (lio_read_csr64(oct, inst_cnt_reg) & in lio_cn23xx_pf_setup_global_input_regs()
301 lio_cn23xx_pf_setup_global_output_regs(struct octeon_device *oct) in lio_cn23xx_pf_setup_global_output_regs() argument
303 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_setup_global_output_regs()
307 srn = oct->sriov_info.pf_srn; in lio_cn23xx_pf_setup_global_output_regs()
308 ern = srn + oct->sriov_info.num_pf_rings; in lio_cn23xx_pf_setup_global_output_regs()
311 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 32); in lio_cn23xx_pf_setup_global_output_regs()
314 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0); in lio_cn23xx_pf_setup_global_output_regs()
318 reg_val = lio_read_csr32(oct, in lio_cn23xx_pf_setup_global_output_regs()
350 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(q_no), in lio_cn23xx_pf_setup_global_output_regs()
354 * Enabling these interrupt in oct->fn_list.enable_interrupt() in lio_cn23xx_pf_setup_global_output_regs()
360 oct, (uint32_t)LIO_GET_OQ_INTR_TIME_CFG(cn23xx->conf)); in lio_cn23xx_pf_setup_global_output_regs()
362 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), in lio_cn23xx_pf_setup_global_output_regs()
368 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_WMARK, 0x40); in lio_cn23xx_pf_setup_global_output_regs()
371 if (oct->pf_num) in lio_cn23xx_pf_setup_global_output_regs()
372 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN2_W1S, in lio_cn23xx_pf_setup_global_output_regs()
375 lio_write_csr64(oct, LIO_CN23XX_SLI_OUT_BP_EN_W1S, in lio_cn23xx_pf_setup_global_output_regs()
380 lio_cn23xx_pf_setup_device_regs(struct octeon_device *oct) in lio_cn23xx_pf_setup_device_regs() argument
383 lio_cn23xx_pf_enable_error_reporting(oct); in lio_cn23xx_pf_setup_device_regs()
386 lio_cn23xx_pf_setup_global_mac_regs(oct); in lio_cn23xx_pf_setup_device_regs()
388 if (lio_cn23xx_pf_setup_global_input_regs(oct)) in lio_cn23xx_pf_setup_device_regs()
391 lio_cn23xx_pf_setup_global_output_regs(oct); in lio_cn23xx_pf_setup_device_regs()
397 lio_write_csr64(oct, LIO_CN23XX_SLI_WINDOW_CTL, in lio_cn23xx_pf_setup_device_regs()
401 lio_write_csr64(oct, LIO_CN23XX_SLI_PKT_IN_JABBER, in lio_cn23xx_pf_setup_device_regs()
407 lio_cn23xx_pf_setup_iq_regs(struct octeon_device *oct, uint32_t iq_no) in lio_cn23xx_pf_setup_iq_regs() argument
409 struct lio_instr_queue *iq = oct->instr_queue[iq_no]; in lio_cn23xx_pf_setup_iq_regs()
412 iq_no += oct->sriov_info.pf_srn; in lio_cn23xx_pf_setup_iq_regs()
415 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_BASE_ADDR64(iq_no), in lio_cn23xx_pf_setup_iq_regs()
417 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count); in lio_cn23xx_pf_setup_iq_regs()
425 lio_dev_dbg(oct, "InstQ[%d]:dbell reg @ 0x%x instcnt_reg @ 0x%x\n", in lio_cn23xx_pf_setup_iq_regs()
432 pkt_in_done = lio_read_csr64(oct, iq->inst_cnt_reg); in lio_cn23xx_pf_setup_iq_regs()
434 if (oct->msix_on) { in lio_cn23xx_pf_setup_iq_regs()
436 lio_write_csr64(oct, iq->inst_cnt_reg, in lio_cn23xx_pf_setup_iq_regs()
443 lio_write_csr64(oct, iq->inst_cnt_reg, pkt_in_done); in lio_cn23xx_pf_setup_iq_regs()
450 lio_cn23xx_pf_setup_oq_regs(struct octeon_device *oct, uint32_t oq_no) in lio_cn23xx_pf_setup_oq_regs() argument
452 struct lio_droq *droq = oct->droq[oq_no]; in lio_cn23xx_pf_setup_oq_regs()
453 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_setup_oq_regs()
458 oq_no += oct->sriov_info.pf_srn; in lio_cn23xx_pf_setup_oq_regs()
460 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_BASE_ADDR64(oq_no), in lio_cn23xx_pf_setup_oq_regs()
462 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count); in lio_cn23xx_pf_setup_oq_regs()
464 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no), in lio_cn23xx_pf_setup_oq_regs()
471 if (!oct->msix_on) { in lio_cn23xx_pf_setup_oq_regs()
477 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in lio_cn23xx_pf_setup_oq_regs()
479 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in lio_cn23xx_pf_setup_oq_regs()
487 lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no)); in lio_cn23xx_pf_setup_oq_regs()
489 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKT_CONTROL(oq_no), in lio_cn23xx_pf_setup_oq_regs()
492 time_threshold = lio_cn23xx_pf_get_oq_ticks(oct, in lio_cn23xx_pf_setup_oq_regs()
496 lio_write_csr64(oct, LIO_CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no), in lio_cn23xx_pf_setup_oq_regs()
503 lio_cn23xx_pf_enable_io_queues(struct octeon_device *oct) in lio_cn23xx_pf_enable_io_queues() argument
509 srn = oct->sriov_info.pf_srn; in lio_cn23xx_pf_enable_io_queues()
510 ern = srn + oct->num_iqs; in lio_cn23xx_pf_enable_io_queues()
514 if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) { in lio_cn23xx_pf_enable_io_queues()
515 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
518 lio_write_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
523 if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) { in lio_cn23xx_pf_enable_io_queues()
528 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
537 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
542 lio_dev_err(oct, "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n", in lio_cn23xx_pf_enable_io_queues()
548 lio_write_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
552 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
555 lio_dev_err(oct, "clearing the reset failed for qno: %u\n", in lio_cn23xx_pf_enable_io_queues()
560 reg_val = lio_read_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
563 lio_write_csr64(oct, in lio_cn23xx_pf_enable_io_queues()
571 if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) { in lio_cn23xx_pf_enable_io_queues()
572 reg_val = lio_read_csr32(oct, in lio_cn23xx_pf_enable_io_queues()
575 lio_write_csr32(oct, in lio_cn23xx_pf_enable_io_queues()
584 lio_cn23xx_pf_disable_io_queues(struct octeon_device *oct) in lio_cn23xx_pf_disable_io_queues() argument
592 srn = oct->sriov_info.pf_srn; in lio_cn23xx_pf_disable_io_queues()
593 ern = srn + oct->num_iqs; in lio_cn23xx_pf_disable_io_queues()
600 d64 = lio_read_csr64(oct, in lio_cn23xx_pf_disable_io_queues()
604 lio_write_csr64(oct, LIO_CN23XX_SLI_IQ_PKT_CONTROL64(q_no), in lio_cn23xx_pf_disable_io_queues()
611 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST); in lio_cn23xx_pf_disable_io_queues()
613 d64 = lio_read_csr64(oct, in lio_cn23xx_pf_disable_io_queues()
620 lio_write_csr32(oct, LIO_CN23XX_SLI_IQ_DOORBELL(q_no), in lio_cn23xx_pf_disable_io_queues()
622 while (((lio_read_csr64(oct, in lio_cn23xx_pf_disable_io_queues()
638 d64 = lio_read_csr64(oct, LIO_CN23XX_SLI_PKT_IOQ_RING_RST); in lio_cn23xx_pf_disable_io_queues()
640 d64 = lio_read_csr64(oct, in lio_cn23xx_pf_disable_io_queues()
647 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_CREDIT(q_no), in lio_cn23xx_pf_disable_io_queues()
649 while ((lio_read_csr64(oct, in lio_cn23xx_pf_disable_io_queues()
656 d32 = lio_read_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no)); in lio_cn23xx_pf_disable_io_queues()
657 lio_write_csr32(oct, LIO_CN23XX_SLI_OQ_PKTS_SENT(q_no), d32); in lio_cn23xx_pf_disable_io_queues()
665 struct octeon_device *oct = ioq_vector->oct_dev; in lio_cn23xx_pf_msix_interrupt_handler() local
666 struct lio_droq *droq = oct->droq[ioq_vector->droq_index]; in lio_cn23xx_pf_msix_interrupt_handler()
671 lio_dev_err(oct, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n", in lio_cn23xx_pf_msix_interrupt_handler()
672 oct->pf_num, ioq_vector->ioq_num); in lio_cn23xx_pf_msix_interrupt_handler()
675 pkts_sent = lio_read_csr64(oct, droq->pkts_sent_reg); in lio_cn23xx_pf_msix_interrupt_handler()
703 struct octeon_device *oct = (struct octeon_device *)dev; in lio_cn23xx_pf_interrupt_handler() local
704 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_interrupt_handler()
707 lio_dev_dbg(oct, "In %s octeon_dev @ %p\n", __func__, oct); in lio_cn23xx_pf_interrupt_handler()
708 intr64 = lio_read_csr64(oct, cn23xx->intr_sum_reg64); in lio_cn23xx_pf_interrupt_handler()
710 oct->int_status = 0; in lio_cn23xx_pf_interrupt_handler()
713 lio_dev_err(oct, "Error Intr: 0x%016llx\n", in lio_cn23xx_pf_interrupt_handler()
716 if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) { in lio_cn23xx_pf_interrupt_handler()
718 oct->int_status |= LIO_DEV_INTR_PKT_DATA; in lio_cn23xx_pf_interrupt_handler()
722 oct->int_status |= LIO_DEV_INTR_DMA0_FORCE; in lio_cn23xx_pf_interrupt_handler()
725 oct->int_status |= LIO_DEV_INTR_DMA1_FORCE; in lio_cn23xx_pf_interrupt_handler()
728 lio_write_csr64(oct, cn23xx->intr_sum_reg64, intr64); in lio_cn23xx_pf_interrupt_handler()
732 lio_cn23xx_pf_bar1_idx_setup(struct octeon_device *oct, uint64_t core_addr, in lio_cn23xx_pf_bar1_idx_setup() argument
739 reg_adr = lio_pci_readq(oct, in lio_cn23xx_pf_bar1_idx_setup()
740 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, in lio_cn23xx_pf_bar1_idx_setup()
743 lio_pci_writeq(oct, (bar1 & 0xFFFFFFFEULL), in lio_cn23xx_pf_bar1_idx_setup()
744 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, in lio_cn23xx_pf_bar1_idx_setup()
746 reg_adr = lio_pci_readq(oct, in lio_cn23xx_pf_bar1_idx_setup()
747 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, in lio_cn23xx_pf_bar1_idx_setup()
756 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | LIO_PCI_BAR1_MASK), in lio_cn23xx_pf_bar1_idx_setup()
757 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in lio_cn23xx_pf_bar1_idx_setup()
759 bar1 = lio_pci_readq(oct, LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, in lio_cn23xx_pf_bar1_idx_setup()
764 lio_cn23xx_pf_bar1_idx_write(struct octeon_device *oct, uint32_t idx, in lio_cn23xx_pf_bar1_idx_write() argument
768 lio_pci_writeq(oct, mask, in lio_cn23xx_pf_bar1_idx_write()
769 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)); in lio_cn23xx_pf_bar1_idx_write()
773 lio_cn23xx_pf_bar1_idx_read(struct octeon_device *oct, uint32_t idx) in lio_cn23xx_pf_bar1_idx_read() argument
776 return ((uint32_t)lio_pci_readq(oct, in lio_cn23xx_pf_bar1_idx_read()
777 LIO_CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, in lio_cn23xx_pf_bar1_idx_read()
785 struct octeon_device *oct = iq->oct_dev; in lio_cn23xx_pf_update_read_index() local
788 uint32_t pkt_in_done = lio_read_csr32(oct, iq->inst_cnt_reg); in lio_cn23xx_pf_update_read_index()
806 lio_cn23xx_pf_enable_interrupt(struct octeon_device *oct, uint8_t intr_flag) in lio_cn23xx_pf_enable_interrupt() argument
808 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_enable_interrupt()
814 lio_write_csr64(oct, cn23xx->intr_enb_reg64, in lio_cn23xx_pf_enable_interrupt()
817 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64); in lio_cn23xx_pf_enable_interrupt()
819 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val); in lio_cn23xx_pf_enable_interrupt()
824 lio_cn23xx_pf_disable_interrupt(struct octeon_device *oct, uint8_t intr_flag) in lio_cn23xx_pf_disable_interrupt() argument
826 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_disable_interrupt()
831 lio_write_csr64(oct, cn23xx->intr_enb_reg64, 0); in lio_cn23xx_pf_disable_interrupt()
833 intr_val = lio_read_csr64(oct, cn23xx->intr_enb_reg64); in lio_cn23xx_pf_disable_interrupt()
835 lio_write_csr64(oct, cn23xx->intr_enb_reg64, intr_val); in lio_cn23xx_pf_disable_interrupt()
840 lio_cn23xx_pf_get_pcie_qlmport(struct octeon_device *oct) in lio_cn23xx_pf_get_pcie_qlmport() argument
842 oct->pcie_port = (lio_read_csr32(oct, in lio_cn23xx_pf_get_pcie_qlmport()
845 lio_dev_dbg(oct, "CN23xx uses PCIE Port %d\n", in lio_cn23xx_pf_get_pcie_qlmport()
846 oct->pcie_port); in lio_cn23xx_pf_get_pcie_qlmport()
850 lio_cn23xx_pf_get_pf_num(struct octeon_device *oct) in lio_cn23xx_pf_get_pf_num() argument
855 fdl_bit = lio_read_pci_cfg(oct, LIO_CN23XX_PCIE_SRIOV_FDL); in lio_cn23xx_pf_get_pf_num()
856 oct->pf_num = ((fdl_bit >> LIO_CN23XX_PCIE_SRIOV_FDL_BIT_POS) & in lio_cn23xx_pf_get_pf_num()
861 lio_cn23xx_pf_setup_reg_address(struct octeon_device *oct) in lio_cn23xx_pf_setup_reg_address() argument
863 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_setup_reg_address()
865 oct->reg_list.pci_win_wr_addr = LIO_CN23XX_SLI_WIN_WR_ADDR64; in lio_cn23xx_pf_setup_reg_address()
867 oct->reg_list.pci_win_rd_addr_hi = LIO_CN23XX_SLI_WIN_RD_ADDR_HI; in lio_cn23xx_pf_setup_reg_address()
868 oct->reg_list.pci_win_rd_addr_lo = LIO_CN23XX_SLI_WIN_RD_ADDR64; in lio_cn23xx_pf_setup_reg_address()
869 oct->reg_list.pci_win_rd_addr = LIO_CN23XX_SLI_WIN_RD_ADDR64; in lio_cn23xx_pf_setup_reg_address()
871 oct->reg_list.pci_win_wr_data_hi = LIO_CN23XX_SLI_WIN_WR_DATA_HI; in lio_cn23xx_pf_setup_reg_address()
872 oct->reg_list.pci_win_wr_data_lo = LIO_CN23XX_SLI_WIN_WR_DATA_LO; in lio_cn23xx_pf_setup_reg_address()
873 oct->reg_list.pci_win_wr_data = LIO_CN23XX_SLI_WIN_WR_DATA64; in lio_cn23xx_pf_setup_reg_address()
875 oct->reg_list.pci_win_rd_data = LIO_CN23XX_SLI_WIN_RD_DATA64; in lio_cn23xx_pf_setup_reg_address()
877 lio_cn23xx_pf_get_pcie_qlmport(oct); in lio_cn23xx_pf_setup_reg_address()
880 if (!oct->msix_on) in lio_cn23xx_pf_setup_reg_address()
884 LIO_CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); in lio_cn23xx_pf_setup_reg_address()
886 LIO_CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); in lio_cn23xx_pf_setup_reg_address()
890 lio_cn23xx_pf_sriov_config(struct octeon_device *oct) in lio_cn23xx_pf_sriov_config() argument
892 struct lio_cn23xx_pf *cn23xx = (struct lio_cn23xx_pf *)oct->chip; in lio_cn23xx_pf_sriov_config()
894 cn23xx->conf = (struct lio_config *)lio_get_config_info(oct, LIO_23XX); in lio_cn23xx_pf_sriov_config()
898 if (oct->sriov_info.num_pf_rings) { in lio_cn23xx_pf_sriov_config()
899 num_pf_rings = oct->sriov_info.num_pf_rings; in lio_cn23xx_pf_sriov_config()
902 …lio_dev_warn(oct, "num_queues_per_pf requested %u is more than available rings (%u). Reducing to %… in lio_cn23xx_pf_sriov_config()
903 oct->sriov_info.num_pf_rings, in lio_cn23xx_pf_sriov_config()
916 oct->sriov_info.trs = total_rings; in lio_cn23xx_pf_sriov_config()
917 oct->sriov_info.pf_srn = total_rings - num_pf_rings; in lio_cn23xx_pf_sriov_config()
918 oct->sriov_info.num_pf_rings = num_pf_rings; in lio_cn23xx_pf_sriov_config()
920 lio_dev_dbg(oct, "trs:%d pf_srn:%d num_pf_rings:%d\n", in lio_cn23xx_pf_sriov_config()
921 oct->sriov_info.trs, oct->sriov_info.pf_srn, in lio_cn23xx_pf_sriov_config()
922 oct->sriov_info.num_pf_rings); in lio_cn23xx_pf_sriov_config()
928 lio_cn23xx_pf_setup_device(struct octeon_device *oct) in lio_cn23xx_pf_setup_device() argument
933 data32 = lio_read_pci_cfg(oct, 0x10); in lio_cn23xx_pf_setup_device()
935 data32 = lio_read_pci_cfg(oct, 0x14); in lio_cn23xx_pf_setup_device()
937 data32 = lio_read_pci_cfg(oct, 0x18); in lio_cn23xx_pf_setup_device()
939 data32 = lio_read_pci_cfg(oct, 0x1c); in lio_cn23xx_pf_setup_device()
944 lio_dev_err(oct, "Device BAR0 unassigned\n"); in lio_cn23xx_pf_setup_device()
947 lio_dev_err(oct, "Device BAR1 unassigned\n"); in lio_cn23xx_pf_setup_device()
952 if (lio_map_pci_barx(oct, 0)) in lio_cn23xx_pf_setup_device()
955 if (lio_map_pci_barx(oct, 1)) { in lio_cn23xx_pf_setup_device()
956 lio_dev_err(oct, "%s CN23XX BAR1 map failed\n", __func__); in lio_cn23xx_pf_setup_device()
957 lio_unmap_pci_barx(oct, 0); in lio_cn23xx_pf_setup_device()
961 lio_cn23xx_pf_get_pf_num(oct); in lio_cn23xx_pf_setup_device()
963 if (lio_cn23xx_pf_sriov_config(oct)) { in lio_cn23xx_pf_setup_device()
964 lio_unmap_pci_barx(oct, 0); in lio_cn23xx_pf_setup_device()
965 lio_unmap_pci_barx(oct, 1); in lio_cn23xx_pf_setup_device()
968 lio_write_csr64(oct, LIO_CN23XX_SLI_MAC_CREDIT_CNT, in lio_cn23xx_pf_setup_device()
971 oct->fn_list.setup_iq_regs = lio_cn23xx_pf_setup_iq_regs; in lio_cn23xx_pf_setup_device()
972 oct->fn_list.setup_oq_regs = lio_cn23xx_pf_setup_oq_regs; in lio_cn23xx_pf_setup_device()
973 oct->fn_list.process_interrupt_regs = lio_cn23xx_pf_interrupt_handler; in lio_cn23xx_pf_setup_device()
974 oct->fn_list.msix_interrupt_handler = in lio_cn23xx_pf_setup_device()
977 oct->fn_list.soft_reset = lio_cn23xx_pf_soft_reset; in lio_cn23xx_pf_setup_device()
978 oct->fn_list.setup_device_regs = lio_cn23xx_pf_setup_device_regs; in lio_cn23xx_pf_setup_device()
979 oct->fn_list.update_iq_read_idx = lio_cn23xx_pf_update_read_index; in lio_cn23xx_pf_setup_device()
981 oct->fn_list.bar1_idx_setup = lio_cn23xx_pf_bar1_idx_setup; in lio_cn23xx_pf_setup_device()
982 oct->fn_list.bar1_idx_write = lio_cn23xx_pf_bar1_idx_write; in lio_cn23xx_pf_setup_device()
983 oct->fn_list.bar1_idx_read = lio_cn23xx_pf_bar1_idx_read; in lio_cn23xx_pf_setup_device()
985 oct->fn_list.enable_interrupt = lio_cn23xx_pf_enable_interrupt; in lio_cn23xx_pf_setup_device()
986 oct->fn_list.disable_interrupt = lio_cn23xx_pf_disable_interrupt; in lio_cn23xx_pf_setup_device()
988 oct->fn_list.enable_io_queues = lio_cn23xx_pf_enable_io_queues; in lio_cn23xx_pf_setup_device()
989 oct->fn_list.disable_io_queues = lio_cn23xx_pf_disable_io_queues; in lio_cn23xx_pf_setup_device()
991 lio_cn23xx_pf_setup_reg_address(oct); in lio_cn23xx_pf_setup_device()
993 oct->coproc_clock_rate = 1000000ULL * in lio_cn23xx_pf_setup_device()
994 lio_cn23xx_pf_coprocessor_clock(oct); in lio_cn23xx_pf_setup_device()
1000 lio_cn23xx_pf_fw_loaded(struct octeon_device *oct) in lio_cn23xx_pf_fw_loaded() argument
1004 val = lio_read_csr64(oct, LIO_CN23XX_SLI_SCRATCH2); in lio_cn23xx_pf_fw_loaded()