Lines Matching +full:tx +full:- +full:burst +full:- +full:length
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
159 #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
160 #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
169 #define LE_CSR30 0x001e /* Base addr of Tx ring lower */
170 #define LE_CSR31 0x001f /* Base addr of Tx ring upper */
171 #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
172 #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
173 #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
174 #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
177 #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
178 #define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */
181 #define LE_CSR42 0x002a /* Current Tx Byte Count */
182 #define LE_CSR43 0x002b /* Current Tx Status */
185 #define LE_CSR46 0x002e /* Tx Poll Time Counter */
186 #define LE_CSR47 0x002f /* Tx Polling Interval */
190 #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
191 #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
192 #define LE_CSR62 0x003e /* Previous Tx Byte Count */
193 #define LE_CSR63 0x003f /* Previous Tx Status */
194 #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
195 #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
196 #define LE_CSR66 0x0042 /* Next Tx Byte Count */
197 #define LE_CSR67 0x0043 /* Next Tx Status */
200 #define LE_CSR76 0x004c /* Receive Ring Length */
201 #define LE_CSR78 0x004e /* Transmit Ring Length */
204 #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
210 #define LE_CSR92 0x005c /* Ring Length Conversion */
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
232 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */
293 #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
295 #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
375 #define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
466 #define LE_B18_BREADE 0x0040 /* burst read enable */
467 #define LE_B18_BWRITE 0x0020 /* burst write enable */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */