Lines Matching +full:burst +full:- +full:clk +full:- +full:enable
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
232 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */
274 #define LE_C0_INEA 0x0040 /* interrupt enable */
279 #define LE_C0_STRT 0x0002 /* enable external activity */
296 #define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */
302 #define LE_C4_EN124 0x8000 /* enable CSR124 */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
304 #define LE_C4_TIMER 0x2000 /* enable bus activity timer */
320 #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
322 #define LE_C5_SINTE 0x0400 /* system interrupt enable */
328 #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
329 #define LE_C5_MPEN 0x0004 /* magic packet enable */
338 #define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */
342 #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
345 enable */
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
348 enable */
352 interrupt enable */
356 internal interrupt enable */
360 interrupt enable */
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
376 #define LE_C15_LOOP 0x0004 /* loopback enable */
403 #define LE_C116_MPPEN 0x0010 /* magic packet pin enable */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
423 #define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */
424 #define LE_B2_LEDPE 0x1000 /* LED program enable */
425 #define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
442 #define LE_B4_100E 0x1000 /* 100Mb/s enable */
443 #define LE_B4_MPSE 0x0200 /* magic packet status enable */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
445 #define LE_B4_PSE 0x0080 /* pulse stretcher enable */
446 #define LE_B4_LNKSE 0x0040 /* link status enable */
447 #define LE_B4_RCVME 0x0020 /* receive match status enable */
448 #define LE_B4_XMTE 0x0010 /* transmit status enable */
449 #define LE_B4_POWER 0x0008 /* power enable */
450 #define LE_B4_RCVE 0x0004 /* receive status enable */
451 #define LE_B4_SPEED 0x0002 /* high speed enable */
452 #define LE_B4_COLE 0x0001 /* collision status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
463 #define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
466 #define LE_B18_BREADE 0x0040 /* burst read enable */
467 #define LE_B18_BWRITE 0x0020 /* burst write enable */
480 #define LE_B19_EEN 0x0010 /* EEPROM port enable */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
506 /* 000 CLK pin */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
540 #define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
546 #define LE_B33_SHADOW 0x8000 /* shadow enable */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */