Lines Matching +full:addr +full:- +full:mode

3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
154 #define LE_CSR15 0x000f /* Mode */
155 #define LE_CSR16 0x0010 /* Initialization Block addr lower */
156 #define LE_CSR17 0x0011 /* Initialization Block addr upper */
157 #define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */
158 #define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */
159 #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
160 #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
161 #define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */
162 #define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */
163 #define LE_CSR24 0x0018 /* Base addr of Rx ring lower */
164 #define LE_CSR25 0x0019 /* Base addr of Rx ring upper */
165 #define LE_CSR26 0x001a /* Next Rx Desc addr lower */
166 #define LE_CSR27 0x001b /* Next Rx Desc addr upper */
167 #define LE_CSR28 0x001c /* Current Rx Desc addr lower */
168 #define LE_CSR29 0x001d /* Current Rx Desc addr upper */
169 #define LE_CSR30 0x001e /* Base addr of Tx ring lower */
170 #define LE_CSR31 0x001f /* Base addr of Tx ring upper */
171 #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
172 #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
173 #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
174 #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
175 #define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */
176 #define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */
177 #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
190 #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
191 #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
194 #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
195 #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
204 #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
205 #define LE_CSR84 0x0054 /* DMA addr register lower */
206 #define LE_CSR85 0x0055 /* DMA addr register upper */
214 #define LE_CSR116 0x0074 /* OnNow Power Mode Register */
222 #define LE_BCR0 0x0000 /* Master Mode Read Active */
223 #define LE_BCR1 0x0001 /* Master Mode Write Active */
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
241 #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
242 #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
330 #define LE_C5_MPMODE 0x0002 /* magic packet mode */
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
363 #define LE_C15_PROM 0x8000 /* promiscuous mode */
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
368 #define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */
370 #define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */
398 #define LE_C116_LCMODE 0x0100 /* link change wakeup mode */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
430 #define LE_B2_AWAKE 0x0004 /* power saving mode select */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
569 /* Initialization block (mode) */
570 #define LE_MODE_PROM 0x8000 /* promiscuous mode */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */
577 #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */
579 transmit mode selection */
586 #define LE_MODE_LOOP 0x0004 /* loopback mode */