Lines Matching +full:0 +full:x0040
139 #define LE_CSR0 0x0000 /* Control and status register */
140 #define LE_CSR1 0x0001 /* low address of init block */
141 #define LE_CSR2 0x0002 /* high address of init block */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
145 #define LE_CSR6 0x0006 /* Rx/Tx Descriptor table length */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
147 #define LE_CSR8 0x0008 /* Logical Address Filter 0 */
148 #define LE_CSR9 0x0009 /* Logical Address Filter 1 */
149 #define LE_CSR10 0x000a /* Logical Address Filter 2 */
150 #define LE_CSR11 0x000b /* Logical Address Filter 3 */
151 #define LE_CSR12 0x000c /* Physical Address 0 */
152 #define LE_CSR13 0x000d /* Physical Address 1 */
153 #define LE_CSR14 0x000e /* Physical Address 2 */
154 #define LE_CSR15 0x000f /* Mode */
155 #define LE_CSR16 0x0010 /* Initialization Block addr lower */
156 #define LE_CSR17 0x0011 /* Initialization Block addr upper */
157 #define LE_CSR18 0x0012 /* Current Rx Buffer addr lower */
158 #define LE_CSR19 0x0013 /* Current Rx Buffer addr upper */
159 #define LE_CSR20 0x0014 /* Current Tx Buffer addr lower */
160 #define LE_CSR21 0x0015 /* Current Tx Buffer addr upper */
161 #define LE_CSR22 0x0016 /* Next Rx Buffer addr lower */
162 #define LE_CSR23 0x0017 /* Next Rx Buffer addr upper */
163 #define LE_CSR24 0x0018 /* Base addr of Rx ring lower */
164 #define LE_CSR25 0x0019 /* Base addr of Rx ring upper */
165 #define LE_CSR26 0x001a /* Next Rx Desc addr lower */
166 #define LE_CSR27 0x001b /* Next Rx Desc addr upper */
167 #define LE_CSR28 0x001c /* Current Rx Desc addr lower */
168 #define LE_CSR29 0x001d /* Current Rx Desc addr upper */
169 #define LE_CSR30 0x001e /* Base addr of Tx ring lower */
170 #define LE_CSR31 0x001f /* Base addr of Tx ring upper */
171 #define LE_CSR32 0x0020 /* Next Tx Desc addr lower */
172 #define LE_CSR33 0x0021 /* Next Tx Desc addr upper */
173 #define LE_CSR34 0x0022 /* Current Tx Desc addr lower */
174 #define LE_CSR35 0x0023 /* Current Tx Desc addr upper */
175 #define LE_CSR36 0x0024 /* Next Next Rx Desc addr lower */
176 #define LE_CSR37 0x0025 /* Next Next Rx Desc addr upper */
177 #define LE_CSR38 0x0026 /* Next Next Tx Desc addr lower */
178 #define LE_CSR39 0x0027 /* Next Next Tx Desc adddr upper */
179 #define LE_CSR40 0x0028 /* Current Rx Byte Count */
180 #define LE_CSR41 0x0029 /* Current Rx Status */
181 #define LE_CSR42 0x002a /* Current Tx Byte Count */
182 #define LE_CSR43 0x002b /* Current Tx Status */
183 #define LE_CSR44 0x002c /* Next Rx Byte Count */
184 #define LE_CSR45 0x002d /* Next Rx Status */
185 #define LE_CSR46 0x002e /* Tx Poll Time Counter */
186 #define LE_CSR47 0x002f /* Tx Polling Interval */
187 #define LE_CSR48 0x0030 /* Rx Poll Time Counter */
188 #define LE_CSR49 0x0031 /* Rx Polling Interval */
189 #define LE_CSR58 0x003a /* Software Style */
190 #define LE_CSR60 0x003c /* Previous Tx Desc addr lower */
191 #define LE_CSR61 0x003d /* Previous Tx Desc addr upper */
192 #define LE_CSR62 0x003e /* Previous Tx Byte Count */
193 #define LE_CSR63 0x003f /* Previous Tx Status */
194 #define LE_CSR64 0x0040 /* Next Tx Buffer addr lower */
195 #define LE_CSR65 0x0041 /* Next Tx Buffer addr upper */
196 #define LE_CSR66 0x0042 /* Next Tx Byte Count */
197 #define LE_CSR67 0x0043 /* Next Tx Status */
198 #define LE_CSR72 0x0048 /* Receive Ring Counter */
199 #define LE_CSR74 0x004a /* Transmit Ring Counter */
200 #define LE_CSR76 0x004c /* Receive Ring Length */
201 #define LE_CSR78 0x004e /* Transmit Ring Length */
202 #define LE_CSR80 0x0050 /* DMA Transfer Counter and FIFO
204 #define LE_CSR82 0x0052 /* Tx Desc addr Pointer lower */
205 #define LE_CSR84 0x0054 /* DMA addr register lower */
206 #define LE_CSR85 0x0055 /* DMA addr register upper */
207 #define LE_CSR86 0x0056 /* Buffer Byte Counter */
208 #define LE_CSR88 0x0058 /* Chip ID Register lower */
209 #define LE_CSR89 0x0059 /* Chip ID Register upper */
210 #define LE_CSR92 0x005c /* Ring Length Conversion */
211 #define LE_CSR100 0x0064 /* Bus Timeout */
212 #define LE_CSR112 0x0070 /* Missed Frame Count */
213 #define LE_CSR114 0x0072 /* Receive Collision Count */
214 #define LE_CSR116 0x0074 /* OnNow Power Mode Register */
215 #define LE_CSR122 0x007a /* Advanced Feature Control */
216 #define LE_CSR124 0x007c /* Test Register 1 */
217 #define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */
222 #define LE_BCR0 0x0000 /* Master Mode Read Active */
223 #define LE_BCR1 0x0001 /* Master Mode Write Active */
224 #define LE_BCR2 0x0002 /* Misc. Configuration */
225 #define LE_BCR4 0x0004 /* LED0 Status */
226 #define LE_BCR5 0x0005 /* LED1 Status */
227 #define LE_BCR6 0x0006 /* LED2 Status */
228 #define LE_BCR7 0x0007 /* LED3 Status */
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
230 #define LE_BCR16 0x0010 /* I/O Base Address lower */
231 #define LE_BCR17 0x0011 /* I/O Base Address upper */
232 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */
233 #define LE_BCR19 0x0013 /* EEPROM Control and Status */
234 #define LE_BCR20 0x0014 /* Software Style */
235 #define LE_BCR22 0x0016 /* PCI Latency Register */
236 #define LE_BCR23 0x0017 /* PCI Subsystem Vendor ID */
237 #define LE_BCR24 0x0018 /* PCI Subsystem ID */
238 #define LE_BCR25 0x0019 /* SRAM Size Register */
239 #define LE_BCR26 0x001a /* SRAM Boundary Register */
240 #define LE_BCR27 0x001b /* SRAM Interface Control Register */
241 #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
242 #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
243 #define LE_BCR30 0x001e /* Exp. Bus Data Port */
244 #define LE_BCR31 0x001f /* Software Timer Register */
245 #define LE_BCR32 0x0020 /* PHY Control and Status Register */
246 #define LE_BCR33 0x0021 /* PHY Address Register */
247 #define LE_BCR34 0x0022 /* PHY Management Data Register */
248 #define LE_BCR35 0x0023 /* PCI Vendor ID Register */
249 #define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */
250 #define LE_BCR37 0x0025 /* PCI DATA0 Alias */
251 #define LE_BCR38 0x0026 /* PCI DATA1 Alias */
252 #define LE_BCR39 0x0027 /* PCI DATA2 Alias */
253 #define LE_BCR40 0x0028 /* PCI DATA3 Alias */
254 #define LE_BCR41 0x0029 /* PCI DATA4 Alias */
255 #define LE_BCR42 0x002a /* PCI DATA5 Alias */
256 #define LE_BCR43 0x002b /* PCI DATA6 Alias */
257 #define LE_BCR44 0x002c /* PCI DATA7 Alias */
258 #define LE_BCR45 0x002d /* OnNow Pattern Matching 1 */
259 #define LE_BCR46 0x002e /* OnNow Pattern Matching 2 */
260 #define LE_BCR47 0x002f /* OnNow Pattern Matching 3 */
261 #define LE_BCR48 0x0030 /* LED4 Status */
262 #define LE_BCR49 0x0031 /* PHY Select */
264 /* Control and status register 0 (csr0) */
265 #define LE_C0_ERR 0x8000 /* error summary */
266 #define LE_C0_BABL 0x4000 /* transmitter timeout error */
267 #define LE_C0_CERR 0x2000 /* collision */
268 #define LE_C0_MISS 0x1000 /* missed a packet */
269 #define LE_C0_MERR 0x0800 /* memory error */
270 #define LE_C0_RINT 0x0400 /* receiver interrupt */
271 #define LE_C0_TINT 0x0200 /* transmitter interrupt */
272 #define LE_C0_IDON 0x0100 /* initialization done */
273 #define LE_C0_INTR 0x0080 /* interrupt condition */
274 #define LE_C0_INEA 0x0040 /* interrupt enable */
275 #define LE_C0_RXON 0x0020 /* receiver on */
276 #define LE_C0_TXON 0x0010 /* transmitter on */
277 #define LE_C0_TDMD 0x0008 /* transmit demand */
278 #define LE_C0_STOP 0x0004 /* disable all external activity */
279 #define LE_C0_STRT 0x0002 /* enable external activity */
280 #define LE_C0_INIT 0x0001 /* begin initialization */
287 #define LE_C3_BABLM 0x4000 /* babble mask */
288 #define LE_C3_MISSM 0x1000 /* missed frame mask */
289 #define LE_C3_MERRM 0x0800 /* memory error mask */
290 #define LE_C3_RINTM 0x0400 /* receive interrupt mask */
291 #define LE_C3_TINTM 0x0200 /* transmit interrupt mask */
292 #define LE_C3_IDONM 0x0100 /* initialization done mask */
293 #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
294 #define LE_C3_LAPPEN 0x0020 /* look ahead packet processing enbl */
295 #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
296 #define LE_C3_EMBA 0x0008 /* enable modified backoff algorithm */
297 #define LE_C3_BSWP 0x0004 /* byte swap */
298 #define LE_C3_ACON 0x0002 /* ALE control, eh? */
299 #define LE_C3_BCON 0x0001 /* byte control */
302 #define LE_C4_EN124 0x8000 /* enable CSR124 */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
304 #define LE_C4_TIMER 0x2000 /* enable bus activity timer */
305 #define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */
306 #define LE_C4_APAD_XMT 0x0800 /* auto pad transmit */
307 #define LE_C4_ASTRP_RCV 0x0400 /* auto strip receive */
308 #define LE_C4_MFCO 0x0200 /* missed frame counter overflow */
309 #define LE_C4_MFCOM 0x0100 /* missed frame coutner overflow mask */
310 #define LE_C4_UINTCMD 0x0080 /* user interrupt command */
311 #define LE_C4_UINT 0x0040 /* user interrupt */
312 #define LE_C4_RCVCCO 0x0020 /* receive collision counter overflow */
313 #define LE_C4_RCVCCOM 0x0010 /* receive collision counter overflow
315 #define LE_C4_TXSTRT 0x0008 /* transmit start status */
316 #define LE_C4_TXSTRTM 0x0004 /* transmit start mask */
319 #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
320 #define LE_C5_LTINTEN 0x4000 /* last transmit interrupt enable */
321 #define LE_C5_SINT 0x0800 /* system interrupt */
322 #define LE_C5_SINTE 0x0400 /* system interrupt enable */
323 #define LE_C5_EXDINT 0x0080 /* excessive deferral interrupt */
324 #define LE_C5_EXDINTE 0x0040 /* excessive deferral interrupt enbl */
325 #define LE_C5_MPPLBA 0x0020 /* magic packet physical logical
327 #define LE_C5_MPINT 0x0010 /* magic packet interrupt */
328 #define LE_C5_MPINTE 0x0008 /* magic packet interrupt enable */
329 #define LE_C5_MPEN 0x0004 /* magic packet enable */
330 #define LE_C5_MPMODE 0x0002 /* magic packet mode */
331 #define LE_C5_SPND 0x0001 /* suspend */
334 #define LE_C6_TLEN 0xf000 /* TLEN from init block */
335 #define LE_C6_RLEN 0x0f00 /* RLEN from init block */
338 #define LE_C7_FASTSPNDE 0x8000 /* fast suspend enable */
339 #define LE_C7_RDMD 0x2000 /* receive demand */
340 #define LE_C7_RDXPOLL 0x1000 /* receive disable polling */
341 #define LE_C7_STINT 0x0800 /* software timer interrupt */
342 #define LE_C7_STINTE 0x0400 /* software timer interrupt enable */
343 #define LE_C7_MREINT 0x0200 /* PHY management read error intr */
344 #define LE_C7_MREINTE 0x0100 /* PHY management read error intr
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
349 #define LE_C7_MCCINT 0x0020 /* PHY management command complete
351 #define LE_C7_MCCINTE 0x0010 /* PHY management command complete
353 #define LE_C7_MCCIINT 0x0008 /* PHY management command complete
355 #define LE_C7_MCCIINTE 0x0004 /* PHY management command complete
357 #define LE_C7_MIIPDTINT 0x0002 /* PHY management detect transition
359 #define LE_C7_MIIPDTINTE 0x0001 /* PHY management detect transition
363 #define LE_C15_PROM 0x8000 /* promiscuous mode */
364 #define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */
365 #define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */
366 #define LE_C15_DLNKTST 0x1000 /* disable link status */
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
368 #define LE_C15_MENDECL 0x0400 /* MENDEC Loopback mode */
369 #define LE_C15_LRT 0x0200 /* low receive threshold (TMAU) */
370 #define LE_C15_TSEL 0x0200 /* transmit mode select (AUI) */
372 #define LE_C15_INTL 0x0040 /* internal loopback */
373 #define LE_C15_DRTY 0x0020 /* disable retry */
374 #define LE_C15_FCOLL 0x0010 /* force collision */
375 #define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */
376 #define LE_C15_LOOP 0x0004 /* loopback enable */
377 #define LE_C15_DTX 0x0002 /* disable transmit */
378 #define LE_C15_DRX 0x0001 /* disable receiver */
380 #define LE_PORTSEL_AUI 0
393 #define LE_C80_DMATC 0x00ff /* DMA transfer counter */
396 #define LE_C116_PME_EN_OVR 0x0400 /* PME_EN overwrite */
397 #define LE_C116_LCDET 0x0200 /* link change detected */
398 #define LE_C116_LCMODE 0x0100 /* link change wakeup mode */
399 #define LE_C116_PMAT 0x0080 /* pattern matched */
400 #define LE_C116_EMPPLBA 0x0040 /* magic packet physical logical
402 #define LE_C116_MPMAT 0x0020 /* magic packet match */
403 #define LE_C116_MPPEN 0x0010 /* magic packet pin enable */
404 #define LE_C116_RST_POL 0x0001 /* PHY_RST pin polarity */
407 #define LE_C122_RCVALGN 0x0001 /* receive packet align */
410 #define LE_C124_RPA 0x0008 /* runt packet accept */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
416 /* bus configuration register 0 (bcr0) */
417 #define LE_B0_MSRDA 0xffff /* reserved locations */
420 #define LE_B1_MSWRA 0xffff /* reserved locations */
423 #define LE_B2_PHYSSELEN 0x2000 /* enable writes to BCR18[4:3] */
424 #define LE_B2_LEDPE 0x1000 /* LED program enable */
425 #define LE_B2_APROMWE 0x0100 /* Address PROM Write Enable */
426 #define LE_B2_INTLEVEL 0x0080 /* 1 == edge triggered */
427 #define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */
428 #define LE_B2_DXCVRPOL 0x0010 /* DXCVR polarity */
429 #define LE_B2_EADISEL 0x0008 /* EADI select */
430 #define LE_B2_AWAKE 0x0004 /* power saving mode select */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
432 #define LE_B2_XMAUSEL 0x0001 /* reserved location */
439 #define LE_B4_LEDOUT 0x8000 /* LED output active */
440 #define LE_B4_LEDPOL 0x4000 /* LED polarity */
441 #define LE_B4_LEDDIS 0x2000 /* LED disable */
442 #define LE_B4_100E 0x1000 /* 100Mb/s enable */
443 #define LE_B4_MPSE 0x0200 /* magic packet status enable */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
445 #define LE_B4_PSE 0x0080 /* pulse stretcher enable */
446 #define LE_B4_LNKSE 0x0040 /* link status enable */
447 #define LE_B4_RCVME 0x0020 /* receive match status enable */
448 #define LE_B4_XMTE 0x0010 /* transmit status enable */
449 #define LE_B4_POWER 0x0008 /* power enable */
450 #define LE_B4_RCVE 0x0004 /* receive status enable */
451 #define LE_B4_SPEED 0x0002 /* high speed enable */
452 #define LE_B4_COLE 0x0001 /* collision status enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
461 #define LE_B18_ROMTMG 0xf000 /* expansion rom timing */
462 #define LE_B18_NOUFLO 0x0800 /* no underflow on transmit */
463 #define LE_B18_MEMCMD 0x0200 /* memory read multiple enable */
464 #define LE_B18_EXTREQ 0x0100 /* extended request */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
466 #define LE_B18_BREADE 0x0040 /* burst read enable */
467 #define LE_B18_BWRITE 0x0020 /* burst write enable */
468 #define LE_B18_PHYSEL1 0x0010 /* PHYSEL 1 */
469 #define LE_B18_PHYSEL0 0x0008 /* PHYSEL 0 */
474 #define LE_B18_LINBC 0x0007 /* reserved locations */
477 #define LE_B19_PVALID 0x8000 /* EEPROM status valid */
478 #define LE_B19_PREAD 0x4000 /* EEPROM read command */
479 #define LE_B19_EEDET 0x2000 /* EEPROM detect */
480 #define LE_B19_EEN 0x0010 /* EEPROM port enable */
481 #define LE_B19_ECS 0x0004 /* EEPROM chip select */
482 #define LE_B19_ESK 0x0002 /* EEPROM serial clock */
483 #define LE_B19_EDI 0x0001 /* EEPROM data in */
484 #define LE_B19_EDO 0x0001 /* EEPROM data out */
487 #define LE_B20_APERREN 0x0400 /* Advanced parity error handling */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
490 #define LE_B20_SSTYLE 0x0007 /* Software Style */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
497 #define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */
500 #define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */
503 #define LE_B27_PTRTST 0x8000 /* reserved for manuf. tests */
504 #define LE_B27_LOLATRX 0x4000 /* low latency receive */
505 #define LE_B27_EBCS 0x0038 /* expansion bus clock source */
511 #define LE_B27_CLK_FAC 0x0007 /* clock factor */
519 #define LE_B28_EADDRL 0xffff /* expansion port address lower */
522 #define LE_B29_FLASH 0x8000 /* flash access */
523 #define LE_B29_LAAINC 0x4000 /* lower address auto increment */
524 #define LE_B29_EPADDRU 0x0007 /* expansion port address upper */
527 #define LE_B30_EBDATA 0xffff /* expansion bus data port */
530 #define LE_B31_STVAL 0xffff /* software timer value */
533 #define LE_B32_ANTST 0x8000 /* reserved for manuf. tests */
534 #define LE_B32_MIIPD 0x4000 /* MII PHY Detect (manuf. tests) */
535 #define LE_B32_FMDC 0x3000 /* fast management data clock */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
538 #define LE_B32_DANAS 0x0080 /* disable autonegotiation */
539 #define LE_B32_XPHYRST 0x0040 /* PHY reset */
540 #define LE_B32_XPHYANE 0x0020 /* PHY autonegotiation enable */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
542 #define LE_B32_XPHYSP 0x0008 /* PHY speed */
543 #define LE_B32_MIIILP 0x0002 /* MII internal loopback */
546 #define LE_B33_SHADOW 0x8000 /* shadow enable */
547 #define LE_B33_MII_SEL 0x4000 /* MII selected */
548 #define LE_B33_ACOMP 0x2000 /* internal PHY autonegotiation comp */
549 #define LE_B33_LINK 0x1000 /* link status */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
551 #define LE_B33_SPEED 0x0400 /* 1 == high speed */
552 #define LE_B33_PHYAD 0x03e0 /* PHY address */
554 #define LE_B33_REGAD 0x001f /* register address */
557 #define LE_B34_MIIMD 0xffff /* MII data */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
561 #define LE_B49_PHYSEL_D 0x0300 /* PHY_SEL_Default */
562 #define LE_B49_PHYSEL_L 0x0010 /* PHY_SEL_Lock */
563 #define LE_B49_PHYSEL 0x0003 /* PHYSEL */
570 #define LE_MODE_PROM 0x8000 /* promiscuous mode */
571 /* 0x7f80 reserved, must be zero */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */
573 #define LE_MODE_DRCVBC 0x4000 /* disable receive broadcast */
574 #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */
575 #define LE_MODE_DLNKTST 0x1000 /* disable link status */
576 #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */
577 #define LE_MODE_MENDECL 0x0400 /* MENDEC loopback mode */
578 #define LE_MODE_LRTTSEL 0x0200 /* lower receive threshold /
580 #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */
581 #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */
582 #define LE_MODE_INTL 0x0040 /* internal loopback */
583 #define LE_MODE_DRTY 0x0020 /* disable retry */
584 #define LE_MODE_COLL 0x0010 /* force a collision */
585 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
586 #define LE_MODE_LOOP 0x0004 /* loopback mode */
587 #define LE_MODE_DTX 0x0002 /* disable transmitter */
588 #define LE_MODE_DRX 0x0001 /* disable receiver */
589 #define LE_MODE_NORMAL 0 /* none of the above */
594 #define CHIPID_MANFID(x) (((x) >> 1) & 0x3ff)
595 #define CHIPID_PARTID(x) (((x) >> 12) & 0xffff)
596 #define CHIPID_VER(x) (((x) >> 28) & 0x7)
598 #define PARTID_Am79c960 0x0003
599 #define PARTID_Am79c961 0x2260
600 #define PARTID_Am79c961A 0x2261
601 #define PARTID_Am79c965 0x2430 /* yes, these... */
602 #define PARTID_Am79c970 0x2430 /* ...are the same */
603 #define PARTID_Am79c970A 0x2621
604 #define PARTID_Am79c971 0x2623
605 #define PARTID_Am79c972 0x2624
606 #define PARTID_Am79c973 0x2625
607 #define PARTID_Am79c978 0x2626
608 #define PARTID_Am79c975 0x2627
609 #define PARTID_Am79c976 0x2628