Lines Matching refs:jme_phyaddr
767 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & in jme_attach()
771 sc->jme_phyaddr); in jme_attach()
773 sc->jme_phyaddr = 0; in jme_attach()
832 sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, in jme_attach()
847 sc->jme_phyaddr = miisc->mii_phy; in jme_attach()
851 if (sc->jme_phyaddr != 0) { in jme_attach()
853 "FPGA PHY is at %d\n", sc->jme_phyaddr); in jme_attach()
855 jme_miibus_writereg(dev, sc->jme_phyaddr, 27, in jme_attach()
1522 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); in jme_setlinkspeed()
1523 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, in jme_setlinkspeed()
1525 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, in jme_setlinkspeed()
2144 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, in jme_mac_config()
2148 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, in jme_mac_config()
2885 reg |= sc->jme_phyaddr; in jme_init_locked()
3337 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); in jme_phy_down()
3355 bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); in jme_phy_up()
3357 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); in jme_phy_up()