65 		struct rx_ring 	*rxr = &que->rxr;  in ixl_configure_rx_itr()  local
69 		rxr->itr = vsi->rx_itr_setting;  in ixl_configure_rx_itr()
70 		rxr->latency = IXL_AVE_LATENCY;  in ixl_configure_rx_itr()
286 	vsi->rx_queues[0].rxr.itr = vsi->rx_itr_setting;  in ixl_configure_legacy()
567 		struct rx_ring 		*rxr = &rx_que->rxr;  in ixl_initialize_vsi()  local
571 		rxr->mbuf_sz = iflib_get_rx_mbuf_sz(vsi->ctx);  in ixl_initialize_vsi()
573 		u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len;  in ixl_initialize_vsi()
577 		rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT;  in ixl_initialize_vsi()
585 		rctx.base = (rxr->rx_paddr/IXL_RX_CTX_BASE_UNITS);  in ixl_initialize_vsi()
625 	struct rx_ring	*rxr = &que->rxr;  in ixl_set_queue_rx_itr()  local
631 	if (rxr->bytes == 0)  in ixl_set_queue_rx_itr()
635 		rx_bytes = rxr->bytes/rxr->itr;  in ixl_set_queue_rx_itr()
636 		rx_itr = rxr->itr;  in ixl_set_queue_rx_itr()
639 		switch (rxr->latency) {  in ixl_set_queue_rx_itr()
663 		rxr->latency = rx_latency;  in ixl_set_queue_rx_itr()
665 		if (rx_itr != rxr->itr) {  in ixl_set_queue_rx_itr()
667 			rx_itr = (10 * rx_itr * rxr->itr) /  in ixl_set_queue_rx_itr()
668 			    ((9 * rx_itr) + rxr->itr);  in ixl_set_queue_rx_itr()
669 			rxr->itr = min(rx_itr, IXL_MAX_ITR);  in ixl_set_queue_rx_itr()
671 			    rxr->me), rxr->itr);  in ixl_set_queue_rx_itr()
677 		if (rxr->itr != vsi->rx_itr_setting) {  in ixl_set_queue_rx_itr()
678 			rxr->itr = vsi->rx_itr_setting;  in ixl_set_queue_rx_itr()
680 			    rxr->me), rxr->itr);  in ixl_set_queue_rx_itr()
683 	rxr->bytes = 0;  in ixl_set_queue_rx_itr()
684 	rxr->packets = 0;  in ixl_set_queue_rx_itr()
800 	val = rd32(rx_que->vsi->hw, rx_que->rxr.tail);  in ixl_sysctl_qrx_tail_handler()
911 			ixl_enable_queue(hw, que->rxr.me);  in ixl_enable_intr()
923 		ixl_disable_queue(hw, que->rxr.me);  in ixl_disable_rings_intr()