Lines Matching +full:long +full:- +full:ram +full:- +full:code
3 Copyright (c) 2013-2018, Intel Corporation
9 1. Redistributions of source code must retain the above copyright notice,
37 * i40e_init_nvm - Initialize NVM function pointers
44 * We are accessing FLASH always through the Shadow RAM.
48 struct i40e_nvm_info *nvm = &hw->nvm; in i40e_init_nvm()
62 nvm->sr_size = BIT(sr_size) * I40E_SR_WORDS_IN_1KB; in i40e_init_nvm()
68 nvm->timeout = I40E_MAX_NVM_TIMEOUT; in i40e_init_nvm()
69 nvm->blank_nvm_mode = FALSE; in i40e_init_nvm()
71 nvm->blank_nvm_mode = TRUE; in i40e_init_nvm()
80 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership
96 if (hw->nvm.blank_nvm_mode) in i40e_acquire_nvm()
105 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time_left) + gtime; in i40e_acquire_nvm()
110 access, (unsigned long long)time_left, ret_code, in i40e_acquire_nvm()
111 hw->aq.asq_last_status); in i40e_acquire_nvm()
124 hw->nvm.hw_semaphore_timeout = in i40e_acquire_nvm()
130 hw->nvm.hw_semaphore_timeout = 0; in i40e_acquire_nvm()
133 (unsigned long long)time_left, ret_code, in i40e_acquire_nvm()
134 hw->aq.asq_last_status); in i40e_acquire_nvm()
143 * i40e_release_nvm - Generic request for releasing the NVM ownership
155 if (hw->nvm.blank_nvm_mode) in i40e_release_nvm()
164 (total_delay < hw->aq.asq_cmd_timeout)) { in i40e_release_nvm()
173 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
176 * Polls the SRCTL Shadow RAM register done bit.
200 * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register
202 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
203 * @data: word read from the Shadow RAM
205 * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
215 if (offset >= hw->nvm.sr_size) { in i40e_read_nvm_word_srctl()
217 "NVM read error: Offset %d beyond Shadow RAM limit %d\n", in i40e_read_nvm_word_srctl()
218 offset, hw->nvm.sr_size); in i40e_read_nvm_word_srctl()
242 "NVM read error: Couldn't access Shadow RAM address: 0x%x\n", in i40e_read_nvm_word_srctl()
250 * i40e_read_nvm_aq - Read Shadow RAM.
255 * @data: buffer with words to write to the Shadow RAM
258 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
271 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_read_nvm_aq()
274 * We cannot do it for the module-based model, as we did not acquire in i40e_read_nvm_aq()
276 * Firmware will check the module-based model. in i40e_read_nvm_aq()
278 if ((offset + words) > hw->nvm.sr_size) in i40e_read_nvm_aq()
280 "NVM write error: offset %d beyond Shadow RAM limit %d\n", in i40e_read_nvm_aq()
281 (offset + words), hw->nvm.sr_size); in i40e_read_nvm_aq()
287 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) in i40e_read_nvm_aq()
303 * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ
305 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
306 * @data: word read from the Shadow RAM
308 * Reads one 16 bit word from the Shadow RAM using the AdminQ
324 * __i40e_read_nvm_word - Reads NVM word, assumes caller does the locking
326 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
327 * @data: word read from the Shadow RAM
329 * Reads one 16 bit word from the Shadow RAM.
339 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) in __i40e_read_nvm_word()
346 * i40e_read_nvm_word - Reads NVM word, acquires lock if necessary
348 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
349 * @data: word read from the Shadow RAM
351 * Reads one 16 bit word from the Shadow RAM.
358 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) in i40e_read_nvm_word()
365 if (hw->flags & I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK) in i40e_read_nvm_word()
371 * i40e_read_nvm_module_data - Reads NVM Buffer to specified memory location
392 "Reading nvm word failed.Error code: %d.\n", in i40e_read_nvm_module_data()
409 /* Pointer points outside of the Shared RAM mapped area */ in i40e_read_nvm_module_data()
411 "Reading nvm data failed. Pointer points outside of the Shared RAM mapped area.\n"); in i40e_read_nvm_module_data()
415 /* Read from the Shadow RAM */ in i40e_read_nvm_module_data()
421 "Reading nvm word failed.Error code: %d.\n", in i40e_read_nvm_module_data()
433 "Reading nvm buffer failed.Error code: %d.\n", in i40e_read_nvm_module_data()
442 * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register
444 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
446 * @data: words read from the Shadow RAM
468 /* Update the number of words read from the Shadow RAM */ in i40e_read_nvm_buffer_srctl()
475 * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ
477 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
479 * @data: words read from the Shadow RAM
503 (u16)(I40E_SR_SECTOR_SIZE_IN_WORDS - in i40e_read_nvm_buffer_aq()
506 read_size = min((*words - words_read), in i40e_read_nvm_buffer_aq()
534 * __i40e_read_nvm_buffer - Reads NVM buffer, caller must acquire lock
536 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
538 * @data: words read from the Shadow RAM
547 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) in __i40e_read_nvm_buffer()
554 * i40e_read_nvm_buffer - Reads Shadow RAM buffer and acquire lock if necessary
556 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
558 * @data: words read from the Shadow RAM
569 if (hw->flags & I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE) { in i40e_read_nvm_buffer()
584 * i40e_write_nvm_aq - Writes Shadow RAM.
589 * @data: buffer with words to write to the Shadow RAM
592 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
604 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_write_nvm_aq()
607 * We cannot do it for the module-based model, as we did not acquire in i40e_write_nvm_aq()
609 * Firmware will check the module-based model. in i40e_write_nvm_aq()
611 if ((offset + words) > hw->nvm.sr_size) in i40e_write_nvm_aq()
612 DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n"); in i40e_write_nvm_aq()
616 else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) in i40e_write_nvm_aq()
631 * __i40e_write_nvm_word - Writes Shadow RAM word
633 * @offset: offset of the Shadow RAM word to write
634 * @data: word to write to the Shadow RAM
653 * __i40e_write_nvm_buffer - Writes Shadow RAM buffer
656 * @offset: offset of the Shadow RAM buffer to write
658 * @data: words to write to the Shadow RAM
660 * Writes a 16 bit words buffer to the Shadow RAM using the admin command.
679 * mirrored in the Shadow RAM is always less than 4K. in __i40e_write_nvm_buffer()
686 * i40e_calc_nvm_checksum - Calculates and returns the checksum
690 * This function calculates SW Checksum that covers the whole 64kB shadow RAM
691 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
720 /* read pointer to PCIe Alt Auto-load module */ in i40e_calc_nvm_checksum()
728 /* Calculate SW checksum that covers the whole 64kB shadow RAM in i40e_calc_nvm_checksum()
729 * except the VPD and PCIe ALT Auto-load modules in i40e_calc_nvm_checksum()
731 for (i = 0; i < hw->nvm.sr_size; i++) { in i40e_calc_nvm_checksum()
762 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local; in i40e_calc_nvm_checksum()
770 * i40e_update_nvm_checksum - Updates the NVM checksum
796 * i40e_validate_nvm_checksum - Validate EEPROM checksum
906 * i40e_nvmupd_command - Process an NVM update command
910 * @perrno: pointer to return error code
931 hw->nvmupd_state, in i40e_nvmupd_command()
932 hw->nvm_release_on_done, hw->nvm_wait_opcode, in i40e_nvmupd_command()
933 cmd->command, cmd->config, cmd->offset, cmd->data_size); in i40e_nvmupd_command()
936 *perrno = -EFAULT; in i40e_nvmupd_command()
946 if (!cmd->data_size) { in i40e_nvmupd_command()
947 *perrno = -EFAULT; in i40e_nvmupd_command()
951 bytes[0] = hw->nvmupd_state; in i40e_nvmupd_command()
953 if (cmd->data_size >= 4) { in i40e_nvmupd_command()
955 *((u16 *)&bytes[2]) = hw->nvm_wait_opcode; in i40e_nvmupd_command()
959 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) in i40e_nvmupd_command()
960 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_command()
970 if (cmd->data_size < hw->nvmupd_features.size) { in i40e_nvmupd_command()
971 *perrno = -EFAULT; in i40e_nvmupd_command()
979 if (cmd->data_size > hw->nvmupd_features.size) in i40e_nvmupd_command()
980 i40e_memset(bytes + hw->nvmupd_features.size, 0x0, in i40e_nvmupd_command()
981 cmd->data_size - hw->nvmupd_features.size, in i40e_nvmupd_command()
984 i40e_memcpy(bytes, &hw->nvmupd_features, in i40e_nvmupd_command()
985 hw->nvmupd_features.size, I40E_NONDMA_MEM); in i40e_nvmupd_command()
991 if (hw->nvmupd_state == I40E_NVMUPD_STATE_ERROR) { in i40e_nvmupd_command()
994 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_command()
1005 i40e_acquire_spinlock(&hw->aq.arq_spinlock); in i40e_nvmupd_command()
1006 switch (hw->nvmupd_state) { in i40e_nvmupd_command()
1024 if (cmd->offset == 0xffff) { in i40e_nvmupd_command()
1031 *perrno = -EBUSY; in i40e_nvmupd_command()
1037 "NVMUPD: no such state %d\n", hw->nvmupd_state); in i40e_nvmupd_command()
1039 *perrno = -ESRCH; in i40e_nvmupd_command()
1043 i40e_release_spinlock(&hw->aq.arq_spinlock); in i40e_nvmupd_command()
1048 * i40e_nvmupd_state_init - Handle NVM update state Init
1052 * @perrno: pointer to return error code
1073 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1084 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1090 hw->nvmupd_state = I40E_NVMUPD_STATE_READING; in i40e_nvmupd_state_init()
1098 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1104 hw->nvm_release_on_done = TRUE; in i40e_nvmupd_state_init()
1105 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_erase; in i40e_nvmupd_state_init()
1106 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_state_init()
1115 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1121 hw->nvm_release_on_done = TRUE; in i40e_nvmupd_state_init()
1122 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_init()
1123 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_state_init()
1132 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1138 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_init()
1139 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; in i40e_nvmupd_state_init()
1148 hw->aq.asq_last_status); in i40e_nvmupd_state_init()
1152 *perrno = hw->aq.asq_last_status ? in i40e_nvmupd_state_init()
1154 hw->aq.asq_last_status) : in i40e_nvmupd_state_init()
1155 -EIO; in i40e_nvmupd_state_init()
1158 hw->nvm_release_on_done = TRUE; in i40e_nvmupd_state_init()
1159 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_init()
1160 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_state_init()
1182 *perrno = -ESRCH; in i40e_nvmupd_state_init()
1189 * i40e_nvmupd_state_reading - Handle NVM update state Reading
1193 * @perrno: pointer to return error code
1218 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_state_reading()
1226 *perrno = -ESRCH; in i40e_nvmupd_state_reading()
1233 * i40e_nvmupd_state_writing - Handle NVM update state Writing
1237 * @perrno: pointer to return error code
1259 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_writing()
1260 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; in i40e_nvmupd_state_writing()
1267 *perrno = hw->aq.asq_last_status ? in i40e_nvmupd_state_writing()
1269 hw->aq.asq_last_status) : in i40e_nvmupd_state_writing()
1270 -EIO; in i40e_nvmupd_state_writing()
1271 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_state_writing()
1273 hw->nvm_release_on_done = TRUE; in i40e_nvmupd_state_writing()
1274 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_writing()
1275 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_state_writing()
1283 *perrno = hw->aq.asq_last_status ? in i40e_nvmupd_state_writing()
1285 hw->aq.asq_last_status) : in i40e_nvmupd_state_writing()
1286 -EIO; in i40e_nvmupd_state_writing()
1287 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_state_writing()
1289 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_writing()
1290 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITE_WAIT; in i40e_nvmupd_state_writing()
1298 *perrno = hw->aq.asq_last_status ? in i40e_nvmupd_state_writing()
1300 hw->aq.asq_last_status) : in i40e_nvmupd_state_writing()
1301 -EIO; in i40e_nvmupd_state_writing()
1302 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_state_writing()
1304 hw->nvm_release_on_done = TRUE; in i40e_nvmupd_state_writing()
1305 hw->nvm_wait_opcode = i40e_aqc_opc_nvm_update; in i40e_nvmupd_state_writing()
1306 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_state_writing()
1315 *perrno = -ESRCH; in i40e_nvmupd_state_writing()
1319 /* In some circumstances, a multi-write transaction takes longer in i40e_nvmupd_state_writing()
1325 if (status && (hw->aq.asq_last_status == I40E_AQ_RC_EBUSY) && in i40e_nvmupd_state_writing()
1328 u32 old_asq_status = hw->aq.asq_last_status; in i40e_nvmupd_state_writing()
1332 if (gtime >= hw->nvm.hw_semaphore_timeout) { in i40e_nvmupd_state_writing()
1335 gtime, hw->nvm.hw_semaphore_timeout); in i40e_nvmupd_state_writing()
1341 hw->aq.asq_last_status); in i40e_nvmupd_state_writing()
1343 hw->aq.asq_last_status = old_asq_status; in i40e_nvmupd_state_writing()
1355 * i40e_nvmupd_clear_wait_state - clear wait state on hw
1362 hw->nvm_wait_opcode); in i40e_nvmupd_clear_wait_state()
1364 if (hw->nvm_release_on_done) { in i40e_nvmupd_clear_wait_state()
1366 hw->nvm_release_on_done = FALSE; in i40e_nvmupd_clear_wait_state()
1368 hw->nvm_wait_opcode = 0; in i40e_nvmupd_clear_wait_state()
1370 if (hw->aq.arq_last_status) { in i40e_nvmupd_clear_wait_state()
1371 hw->nvmupd_state = I40E_NVMUPD_STATE_ERROR; in i40e_nvmupd_clear_wait_state()
1375 switch (hw->nvmupd_state) { in i40e_nvmupd_clear_wait_state()
1377 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_nvmupd_clear_wait_state()
1381 hw->nvmupd_state = I40E_NVMUPD_STATE_WRITING; in i40e_nvmupd_clear_wait_state()
1390 * i40e_nvmupd_check_wait_event - handle NVM update operation events
1400 if (opcode == hw->nvm_wait_opcode) { in i40e_nvmupd_check_wait_event()
1401 i40e_memcpy(&hw->nvm_aq_event_desc, desc, in i40e_nvmupd_check_wait_event()
1408 * i40e_nvmupd_validate_command - Validate given command
1411 * @perrno: pointer to return error code
1427 transaction = i40e_nvmupd_get_transaction(cmd->config); in i40e_nvmupd_validate_command()
1428 module = i40e_nvmupd_get_module(cmd->config); in i40e_nvmupd_validate_command()
1431 if ((cmd->data_size < 1) || in i40e_nvmupd_validate_command()
1432 (cmd->data_size > I40E_NVMUPD_MAX_DATA)) { in i40e_nvmupd_validate_command()
1435 cmd->data_size); in i40e_nvmupd_validate_command()
1436 *perrno = -EFAULT; in i40e_nvmupd_validate_command()
1440 switch (cmd->command) { in i40e_nvmupd_validate_command()
1467 *perrno = -EFAULT; in i40e_nvmupd_validate_command()
1515 * i40e_nvmupd_exec_aq - Run an AQ command
1519 * @perrno: pointer to return error code
1536 if (cmd->offset == 0xffff) in i40e_nvmupd_exec_aq()
1540 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_nvmupd_exec_aq()
1543 memset(&hw->nvm_wb_desc, 0, aq_desc_len); in i40e_nvmupd_exec_aq()
1546 if (cmd->data_size < aq_desc_len) { in i40e_nvmupd_exec_aq()
1549 cmd->data_size, aq_desc_len); in i40e_nvmupd_exec_aq()
1550 *perrno = -EINVAL; in i40e_nvmupd_exec_aq()
1556 aq_data_len = cmd->data_size - aq_desc_len; in i40e_nvmupd_exec_aq()
1557 buff_size = max(aq_data_len, (u32)LE16_TO_CPU(aq_desc->datalen)); in i40e_nvmupd_exec_aq()
1559 if (!hw->nvm_buff.va) { in i40e_nvmupd_exec_aq()
1560 status = i40e_allocate_virt_mem(hw, &hw->nvm_buff, in i40e_nvmupd_exec_aq()
1561 hw->aq.asq_buf_size); in i40e_nvmupd_exec_aq()
1568 if (hw->nvm_buff.va) { in i40e_nvmupd_exec_aq()
1569 buff = hw->nvm_buff.va; in i40e_nvmupd_exec_aq()
1575 if (cmd->offset) in i40e_nvmupd_exec_aq()
1576 memset(&hw->nvm_aq_event_desc, 0, aq_desc_len); in i40e_nvmupd_exec_aq()
1585 i40e_aq_str(hw, hw->aq.asq_last_status)); in i40e_nvmupd_exec_aq()
1586 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); in i40e_nvmupd_exec_aq()
1591 if (cmd->offset) { in i40e_nvmupd_exec_aq()
1592 hw->nvm_wait_opcode = cmd->offset; in i40e_nvmupd_exec_aq()
1593 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT_WAIT; in i40e_nvmupd_exec_aq()
1600 * i40e_nvmupd_get_aq_result - Get the results from the previous exec_aq
1604 * @perrno: pointer to return error code
1620 aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_wb_desc.datalen); in i40e_nvmupd_get_aq_result()
1623 if (cmd->offset > aq_total_len) { in i40e_nvmupd_get_aq_result()
1625 __func__, cmd->offset, aq_total_len); in i40e_nvmupd_get_aq_result()
1626 *perrno = -EINVAL; in i40e_nvmupd_get_aq_result()
1631 if (cmd->data_size > (aq_total_len - cmd->offset)) { in i40e_nvmupd_get_aq_result()
1632 int new_len = aq_total_len - cmd->offset; in i40e_nvmupd_get_aq_result()
1635 __func__, cmd->data_size, new_len); in i40e_nvmupd_get_aq_result()
1636 cmd->data_size = new_len; in i40e_nvmupd_get_aq_result()
1639 remainder = cmd->data_size; in i40e_nvmupd_get_aq_result()
1640 if (cmd->offset < aq_desc_len) { in i40e_nvmupd_get_aq_result()
1641 u32 len = aq_desc_len - cmd->offset; in i40e_nvmupd_get_aq_result()
1643 len = min(len, cmd->data_size); in i40e_nvmupd_get_aq_result()
1645 __func__, cmd->offset, cmd->offset + len); in i40e_nvmupd_get_aq_result()
1647 buff = ((u8 *)&hw->nvm_wb_desc) + cmd->offset; in i40e_nvmupd_get_aq_result()
1651 remainder -= len; in i40e_nvmupd_get_aq_result()
1652 buff = hw->nvm_buff.va; in i40e_nvmupd_get_aq_result()
1654 buff = (u8 *)hw->nvm_buff.va + (cmd->offset - aq_desc_len); in i40e_nvmupd_get_aq_result()
1658 int start_byte = buff - (u8 *)hw->nvm_buff.va; in i40e_nvmupd_get_aq_result()
1669 * i40e_nvmupd_get_aq_event - Get the Admin Queue event from previous exec_aq
1673 * @perrno: pointer to return error code
1687 aq_total_len = aq_desc_len + LE16_TO_CPU(hw->nvm_aq_event_desc.datalen); in i40e_nvmupd_get_aq_event()
1690 if (cmd->data_size > aq_total_len) { in i40e_nvmupd_get_aq_event()
1693 __func__, cmd->data_size, aq_total_len); in i40e_nvmupd_get_aq_event()
1694 cmd->data_size = aq_total_len; in i40e_nvmupd_get_aq_event()
1697 i40e_memcpy(bytes, &hw->nvm_aq_event_desc, cmd->data_size, in i40e_nvmupd_get_aq_event()
1704 * i40e_nvmupd_nvm_read - Read NVM
1708 * @perrno: pointer to return error code
1721 transaction = i40e_nvmupd_get_transaction(cmd->config); in i40e_nvmupd_nvm_read()
1722 module = i40e_nvmupd_get_module(cmd->config); in i40e_nvmupd_nvm_read()
1726 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_nvmupd_nvm_read()
1728 status = i40e_aq_read_nvm(hw, module, cmd->offset, (u16)cmd->data_size, in i40e_nvmupd_nvm_read()
1733 module, cmd->offset, cmd->data_size); in i40e_nvmupd_nvm_read()
1736 status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_read()
1737 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_read()
1744 * i40e_nvmupd_nvm_erase - Erase an NVM module
1747 * @perrno: pointer to return error code
1760 transaction = i40e_nvmupd_get_transaction(cmd->config); in i40e_nvmupd_nvm_erase()
1761 module = i40e_nvmupd_get_module(cmd->config); in i40e_nvmupd_nvm_erase()
1765 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_nvmupd_nvm_erase()
1767 status = i40e_aq_erase_nvm(hw, module, cmd->offset, (u16)cmd->data_size, in i40e_nvmupd_nvm_erase()
1772 module, cmd->offset, cmd->data_size); in i40e_nvmupd_nvm_erase()
1775 status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_erase()
1776 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_erase()
1783 * i40e_nvmupd_nvm_write - Write NVM
1787 * @perrno: pointer to return error code
1801 transaction = i40e_nvmupd_get_transaction(cmd->config); in i40e_nvmupd_nvm_write()
1802 module = i40e_nvmupd_get_module(cmd->config); in i40e_nvmupd_nvm_write()
1804 preservation_flags = i40e_nvmupd_get_preservation_flags(cmd->config); in i40e_nvmupd_nvm_write()
1807 cmd_details.wb_desc = &hw->nvm_wb_desc; in i40e_nvmupd_nvm_write()
1809 status = i40e_aq_update_nvm(hw, module, cmd->offset, in i40e_nvmupd_nvm_write()
1810 (u16)cmd->data_size, bytes, last, in i40e_nvmupd_nvm_write()
1815 module, cmd->offset, cmd->data_size); in i40e_nvmupd_nvm_write()
1818 status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_write()
1819 *perrno = i40e_aq_rc_to_posix(status, hw->aq.asq_last_status); in i40e_nvmupd_nvm_write()