Lines Matching +full:0 +full:x0802
44 #define I40E_FW_API_VERSION_MAJOR 0x0001
45 #define I40E_FW_API_VERSION_MINOR_X722 0x000C
46 #define I40E_FW_API_VERSION_MINOR_X710 0x000F
53 #define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
55 #define I40E_MINOR_VER_GET_LINK_INFO_X722 0x0009
57 #define I40E_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
59 #define I40E_MINOR_VER_FW_REQUEST_FEC_X722 0x000A
86 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
91 #define I40E_AQ_FLAG_DD_SHIFT 0
103 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
104 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
105 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
106 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
107 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
108 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
109 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
110 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
111 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
112 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
113 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
117 I40E_AQ_RC_OK = 0, /* success */
145 i40e_aqc_opc_get_version = 0x0001,
146 i40e_aqc_opc_driver_version = 0x0002,
147 i40e_aqc_opc_queue_shutdown = 0x0003,
148 i40e_aqc_opc_set_pf_context = 0x0004,
151 i40e_aqc_opc_request_resource = 0x0008,
152 i40e_aqc_opc_release_resource = 0x0009,
154 i40e_aqc_opc_list_func_capabilities = 0x000A,
155 i40e_aqc_opc_list_dev_capabilities = 0x000B,
158 i40e_aqc_opc_set_proxy_config = 0x0104,
159 i40e_aqc_opc_set_ns_proxy_table_entry = 0x0105,
162 i40e_aqc_opc_mac_address_read = 0x0107,
163 i40e_aqc_opc_mac_address_write = 0x0108,
166 i40e_aqc_opc_clear_pxe_mode = 0x0110,
169 i40e_aqc_opc_set_wol_filter = 0x0120,
170 i40e_aqc_opc_get_wake_reason = 0x0121,
171 i40e_aqc_opc_clear_all_wol_filters = 0x025E,
174 i40e_aqc_opc_get_switch_config = 0x0200,
175 i40e_aqc_opc_add_statistics = 0x0201,
176 i40e_aqc_opc_remove_statistics = 0x0202,
177 i40e_aqc_opc_set_port_parameters = 0x0203,
178 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
179 i40e_aqc_opc_set_switch_config = 0x0205,
180 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
181 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
183 i40e_aqc_opc_add_vsi = 0x0210,
184 i40e_aqc_opc_update_vsi_parameters = 0x0211,
185 i40e_aqc_opc_get_vsi_parameters = 0x0212,
187 i40e_aqc_opc_add_pv = 0x0220,
188 i40e_aqc_opc_update_pv_parameters = 0x0221,
189 i40e_aqc_opc_get_pv_parameters = 0x0222,
191 i40e_aqc_opc_add_veb = 0x0230,
192 i40e_aqc_opc_update_veb_parameters = 0x0231,
193 i40e_aqc_opc_get_veb_parameters = 0x0232,
195 i40e_aqc_opc_delete_element = 0x0243,
197 i40e_aqc_opc_add_macvlan = 0x0250,
198 i40e_aqc_opc_remove_macvlan = 0x0251,
199 i40e_aqc_opc_add_vlan = 0x0252,
200 i40e_aqc_opc_remove_vlan = 0x0253,
201 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
202 i40e_aqc_opc_add_tag = 0x0255,
203 i40e_aqc_opc_remove_tag = 0x0256,
204 i40e_aqc_opc_add_multicast_etag = 0x0257,
205 i40e_aqc_opc_remove_multicast_etag = 0x0258,
206 i40e_aqc_opc_update_tag = 0x0259,
207 i40e_aqc_opc_add_control_packet_filter = 0x025A,
208 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
209 i40e_aqc_opc_add_cloud_filters = 0x025C,
210 i40e_aqc_opc_remove_cloud_filters = 0x025D,
211 i40e_aqc_opc_clear_wol_switch_filters = 0x025E,
212 i40e_aqc_opc_replace_cloud_filters = 0x025F,
214 i40e_aqc_opc_add_mirror_rule = 0x0260,
215 i40e_aqc_opc_delete_mirror_rule = 0x0261,
218 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
219 i40e_aqc_opc_dcb_updated = 0x0302,
220 i40e_aqc_opc_set_dcb_parameters = 0x0303,
223 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
224 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
225 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
226 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
227 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
228 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
230 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
231 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
232 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
233 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
234 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
235 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
236 i40e_aqc_opc_query_port_ets_config = 0x0419,
237 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
238 i40e_aqc_opc_suspend_port_tx = 0x041B,
239 i40e_aqc_opc_resume_port_tx = 0x041C,
240 i40e_aqc_opc_configure_partition_bw = 0x041D,
242 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
243 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
246 i40e_aqc_opc_get_phy_abilities = 0x0600,
247 i40e_aqc_opc_set_phy_config = 0x0601,
248 i40e_aqc_opc_set_mac_config = 0x0603,
249 i40e_aqc_opc_set_link_restart_an = 0x0605,
250 i40e_aqc_opc_get_link_status = 0x0607,
251 i40e_aqc_opc_set_phy_int_mask = 0x0613,
252 i40e_aqc_opc_get_local_advt_reg = 0x0614,
253 i40e_aqc_opc_set_local_advt_reg = 0x0615,
254 i40e_aqc_opc_get_partner_advt = 0x0616,
255 i40e_aqc_opc_set_lb_modes = 0x0618,
256 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
257 i40e_aqc_opc_set_phy_debug = 0x0622,
258 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
259 i40e_aqc_opc_run_phy_activity = 0x0626,
260 i40e_aqc_opc_set_phy_register = 0x0628,
261 i40e_aqc_opc_get_phy_register = 0x0629,
264 i40e_aqc_opc_nvm_read = 0x0701,
265 i40e_aqc_opc_nvm_erase = 0x0702,
266 i40e_aqc_opc_nvm_update = 0x0703,
267 i40e_aqc_opc_nvm_config_read = 0x0704,
268 i40e_aqc_opc_nvm_config_write = 0x0705,
269 i40e_aqc_opc_nvm_update_in_process = 0x0706,
270 i40e_aqc_opc_rollback_revision_update = 0x0707,
271 i40e_aqc_opc_oem_post_update = 0x0720,
272 i40e_aqc_opc_thermal_sensor = 0x0721,
275 i40e_aqc_opc_send_msg_to_pf = 0x0801,
276 i40e_aqc_opc_send_msg_to_vf = 0x0802,
277 i40e_aqc_opc_send_msg_to_peer = 0x0803,
280 i40e_aqc_opc_alternate_write = 0x0900,
281 i40e_aqc_opc_alternate_write_indirect = 0x0901,
282 i40e_aqc_opc_alternate_read = 0x0902,
283 i40e_aqc_opc_alternate_read_indirect = 0x0903,
284 i40e_aqc_opc_alternate_write_done = 0x0904,
285 i40e_aqc_opc_alternate_set_mode = 0x0905,
286 i40e_aqc_opc_alternate_clear_port = 0x0906,
289 i40e_aqc_opc_lldp_get_mib = 0x0A00,
290 i40e_aqc_opc_lldp_update_mib = 0x0A01,
291 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
292 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
293 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
294 i40e_aqc_opc_lldp_stop = 0x0A05,
295 i40e_aqc_opc_lldp_start = 0x0A06,
296 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
297 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
298 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
299 i40e_aqc_opc_lldp_restore = 0x0A0A,
302 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
303 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
304 i40e_aqc_opc_set_rss_key = 0x0B02,
305 i40e_aqc_opc_set_rss_lut = 0x0B03,
306 i40e_aqc_opc_get_rss_key = 0x0B04,
307 i40e_aqc_opc_get_rss_lut = 0x0B05,
310 i40e_aqc_opc_event_lan_overflow = 0x1001,
313 i40e_aqc_opc_oem_parameter_change = 0xFE00,
314 i40e_aqc_opc_oem_device_status_change = 0xFE01,
315 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
316 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
319 i40e_aqc_opc_debug_read_reg = 0xFF03,
320 i40e_aqc_opc_debug_write_reg = 0xFF04,
321 i40e_aqc_opc_debug_modify_reg = 0xFF07,
322 i40e_aqc_opc_debug_dump_internals = 0xFF08,
344 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
351 /* internal (0x00XX) commands */
353 /* Get version (direct 0x0001) */
365 /* Send driver version (indirect 0x0002) */
378 /* Queue Shutdown (direct 0x0003) */
381 #define I40E_AQ_DRIVER_UNLOADING 0x1
387 /* Set PF context (0x0004, direct) */
395 /* Request resource ownership (direct 0x0008)
396 * Release resource ownership (direct 0x0009)
415 /* Get function capabilities (indirect 0x000A)
416 * Get device capabilities (indirect 0x000B)
442 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
443 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
444 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
445 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
446 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
447 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
448 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
449 #define I40E_AQ_CAP_ID_SRIOV 0x0012
450 #define I40E_AQ_CAP_ID_VF 0x0013
451 #define I40E_AQ_CAP_ID_VMDQ 0x0014
452 #define I40E_AQ_CAP_ID_8021QBG 0x0015
453 #define I40E_AQ_CAP_ID_8021QBR 0x0016
454 #define I40E_AQ_CAP_ID_VSI 0x0017
455 #define I40E_AQ_CAP_ID_DCB 0x0018
456 #define I40E_AQ_CAP_ID_FCOE 0x0021
457 #define I40E_AQ_CAP_ID_ISCSI 0x0022
458 #define I40E_AQ_CAP_ID_RSS 0x0040
459 #define I40E_AQ_CAP_ID_RXQ 0x0041
460 #define I40E_AQ_CAP_ID_TXQ 0x0042
461 #define I40E_AQ_CAP_ID_MSIX 0x0043
462 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
463 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
464 #define I40E_AQ_CAP_ID_1588 0x0046
465 #define I40E_AQ_CAP_ID_IWARP 0x0051
466 #define I40E_AQ_CAP_ID_LED 0x0061
467 #define I40E_AQ_CAP_ID_SDP 0x0062
468 #define I40E_AQ_CAP_ID_MDIO 0x0063
469 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
470 #define I40E_AQ_CAP_ID_DIS_UNUSED_PORTS 0x0067
471 #define I40E_AQ_CAP_ID_NVM_MGMT 0x0080
472 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
473 #define I40E_AQ_CAP_ID_CEM 0x00F2
475 /* Set CPPM Configuration (direct 0x0103) */
478 #define I40E_AQ_CPPM_EN_LTRC 0x0800
479 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
480 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
481 #define I40E_AQ_CPPM_EN_HPTC 0x4000
482 #define I40E_AQ_CPPM_EN_DMARC 0x8000
493 /* Set ARP Proxy command / response (indirect 0x0104) */
496 #define I40E_AQ_ARP_INIT_IPV4 0x0800
497 #define I40E_AQ_ARP_UNSUP_CTL 0x1000
498 #define I40E_AQ_ARP_ENA 0x2000
499 #define I40E_AQ_ARP_ADD_IPV4 0x4000
500 #define I40E_AQ_ARP_DEL_IPV4 0x8000
503 #define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
504 #define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800
510 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
512 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
519 #define I40E_AQ_NS_PROXY_ADD_0 0x0001
520 #define I40E_AQ_NS_PROXY_DEL_0 0x0002
521 #define I40E_AQ_NS_PROXY_ADD_1 0x0004
522 #define I40E_AQ_NS_PROXY_DEL_1 0x0008
523 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010
524 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020
525 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040
526 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080
527 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100
528 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
529 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
530 #define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
531 #define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
539 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
541 /* Manage LAA Command (0x0106) - obsolete */
544 #define I40E_AQ_LAA_FLAG_WR 0x8000
553 /* Manage MAC Address Read Command (indirect 0x0107) */
556 #define I40E_AQC_LAN_ADDR_VALID 0x10
557 #define I40E_AQC_SAN_ADDR_VALID 0x20
558 #define I40E_AQC_PORT_ADDR_VALID 0x40
559 #define I40E_AQC_WOL_ADDR_VALID 0x80
560 #define I40E_AQC_MC_MAG_EN_VALID 0x100
561 #define I40E_AQC_WOL_PRESERVE_STATUS 0x200
562 #define I40E_AQC_ADDR_VALID_MASK 0x3F0
579 /* Manage MAC Address Write Command (0x0108) */
582 #define I40E_AQC_MC_MAG_EN 0x0100
583 #define I40E_AQC_WOL_PRESERVE_ON_PFR 0x0200
584 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
585 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
586 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
587 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
588 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
597 /* PXE commands (0x011x) */
599 /* Clear PXE Command and response (direct 0x0110) */
607 /* Set WoL Filter (0x0120) */
613 #define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
616 #define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
617 #define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
620 #define I40E_AQC_SET_WOL_FILTER 0x8000
621 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
622 #define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
623 #define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
626 #define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
627 #define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
640 I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data);
642 /* Get Wake Reason (0x0121) */
647 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
648 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
651 #define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
658 /* Switch configuration commands (0x02xx) */
672 /* Get Switch Configuration command (indirect 0x0200)
701 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
702 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
703 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
708 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
710 /* Get Switch Configuration (indirect 0x0200)
719 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
721 /* Add Statistics (direct 0x0201)
722 * Remove Statistics (direct 0x0202)
733 /* Set Port Parameters command (direct 0x0203) */
740 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
741 #define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
748 /* Get Switch Resource Allocation (indirect 0x0204) */
761 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
762 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
763 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
764 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
765 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
766 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
767 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
768 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
769 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
770 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
771 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
772 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
773 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
774 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
775 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
776 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
777 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
778 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
779 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
788 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
790 /* Set Switch Configuration (direct 0x0205) */
794 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
795 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
796 #define I40E_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
797 #define I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN 0x0008
801 * of 0x88a8 (802.1ad). Should be zero for firmware API
809 * zero for their defaults of 0x8100 (802.1Q). Should be zero
815 * Bit 7 : 0 : No action, 1: Switch to mode defined by bits 6:0
816 * Bit 6 : 0 : Destination Port, 1: source port
818 * 0: rsvd
822 * Bits 3:0 Mode
823 * 0: default mode
828 #define I40E_AQ_SET_SWITCH_BIT7_VALID 0x80
830 #define I40E_AQ_SET_SWITCH_L4_SRC_PORT 0x40
832 #define I40E_AQ_SET_SWITCH_L4_TYPE_RSVD 0x00
833 #define I40E_AQ_SET_SWITCH_L4_TYPE_TCP 0x10
834 #define I40E_AQ_SET_SWITCH_L4_TYPE_UDP 0x20
835 #define I40E_AQ_SET_SWITCH_L4_TYPE_BOTH 0x30
837 #define I40E_AQ_SET_SWITCH_MODE_DEFAULT 0x00
838 #define I40E_AQ_SET_SWITCH_MODE_L4_PORT 0x01
839 #define I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL 0x02
840 #define I40E_AQ_SET_SWITCH_MODE_TUNNEL 0x03
847 /* Read Receive control registers (direct 0x0206)
848 * Write Receive control registers (direct 0x0207)
861 /* Add VSI (indirect 0x0210)
865 * Update VSI (indirect 0x211)
868 * Get VSI (indirect 0x0212)
874 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
875 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
876 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
881 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
882 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
883 #define I40E_AQ_VSI_TYPE_VF 0x0
884 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
885 #define I40E_AQ_VSI_TYPE_PF 0x2
886 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
887 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
908 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
909 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
910 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
911 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
912 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
913 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
914 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
915 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
916 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
917 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
920 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
921 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
922 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
923 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
924 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
928 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
929 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
930 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
936 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
937 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
939 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
940 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
941 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
942 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
943 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
944 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
946 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
947 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
948 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
949 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
951 #define I40E_AQ_VSI_OVLAN_MODE_SHIFT 0x00
952 #define I40E_AQ_VSI_OVLAN_MODE_MASK (0x03 << \
954 #define I40E_AQ_VSI_OVLAN_MODE_UNTAGGED 0x01
955 #define I40E_AQ_VSI_OVLAN_MODE_TAGGED 0x02
956 #define I40E_AQ_VSI_OVLAN_MODE_ALL 0x03
957 #define I40E_AQ_VSI_OVLAN_INSERT_PVID 0x04
958 #define I40E_AQ_VSI_OVLAN_EMOD_SHIFT 0x03
959 #define I40E_AQ_VSI_OVLAN_EMOD_MASK (0x03 <<\
961 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_ALL 0x00
962 #define I40E_AQ_VSI_OVLAN_EMOD_SHOW_UP 0x01
963 #define I40E_AQ_VSI_OVLAN_EMOD_HIDE_ALL 0x02
964 #define I40E_AQ_VSI_OVLAN_EMOD_NOTHING 0x03
965 #define I40E_AQ_VSI_OVLAN_CTRL_ENA 0x04
970 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
971 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
974 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
977 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
980 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
983 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
986 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
989 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
992 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
998 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
999 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
1001 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
1002 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
1003 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
1004 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
1005 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
1006 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
1010 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
1011 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
1013 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
1014 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
1016 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
1017 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
1020 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
1024 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
1025 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
1026 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
1027 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
1028 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
1029 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
1039 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
1047 /* Add Port Virtualizer (direct 0x0220)
1048 * also used for update PV (direct 0x0221) but only flags are used
1053 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
1054 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
1055 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
1056 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
1067 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
1068 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
1069 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1070 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
1076 /* Get PV Params (direct 0x0222)
1084 #define I40E_AQC_GET_PV_PV_TYPE 0x1
1085 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
1086 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
1093 /* Add VEB (direct 0x0230) */
1098 #define I40E_AQC_ADD_VEB_FLOATING 0x1
1100 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
1102 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
1103 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
1104 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
1105 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
1117 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
1118 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
1119 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
1120 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
1128 /* Get VEB Parameters (direct 0x0232)
1134 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
1143 /* Delete Element (direct 0x0243)
1147 /* Add MAC-VLAN (indirect 0x0250) */
1153 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
1154 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
1156 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
1168 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1169 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1170 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1171 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1172 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1174 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1175 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1179 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1180 #define I40E_AQC_MM_HASH_MATCH 0x02
1181 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1196 /* Remove MAC-VLAN (indirect 0x0251)
1205 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1206 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1207 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1208 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1212 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1213 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1217 /* Add VLAN (indirect 0x0252)
1218 * Remove VLAN (indirect 0x0253)
1225 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1227 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1228 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1229 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1230 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1232 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1233 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1234 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1235 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1236 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1238 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1242 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1243 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1244 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1246 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1247 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1259 /* Set VSI Promiscuous Modes (direct 0x0254) */
1264 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1265 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1266 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1267 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1268 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1269 #define I40E_AQC_SET_VSI_PROMISC_RX_ONLY 0x8000
1271 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1273 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1274 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1280 /* Add S/E-tag command (direct 0x0255)
1285 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1287 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1288 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1305 /* Remove S/E-tag command (direct 0x0256)
1310 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1311 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1319 /* Add multicast E-Tag (direct 0x0257)
1320 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1345 /* Update S/E-Tag (direct 0x0259) */
1348 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1349 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1366 /* Add Control Packet filter (direct 0x025A)
1367 * Remove Control Packet filter (direct 0x025B)
1375 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1376 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1377 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1378 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1379 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1381 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1382 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1400 /* Add Cloud filters (indirect 0x025C)
1401 * Remove Cloud filters (indirect 0x025D)
1409 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1410 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1439 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1440 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1442 /* 0x0000 reserved */
1443 /* 0x0001 reserved */
1444 /* 0x0002 reserved */
1445 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1446 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1447 /* 0x0005 reserved */
1448 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1449 /* 0x0007 reserved */
1450 /* 0x0008 reserved */
1451 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1452 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1453 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1454 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1455 #define I40E_AQC_ADD_CLOUD_FILTER_OIP1 0x0010
1456 #define I40E_AQC_ADD_CLOUD_FILTER_OIP2 0x0012
1457 /* 0x000D reserved */
1458 /* 0x000E reserved */
1459 /* 0x000F reserved */
1460 /* 0x0010 to 0x0017 is for custom filters */
1461 #define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */
1462 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */
1463 #define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */
1465 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1467 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1468 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1469 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1472 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1473 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1480 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1481 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1482 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1487 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1488 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1493 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1494 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1504 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1537 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data);
1545 #define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
1578 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb);
1591 /* Replace filter Command 0x025F
1604 #define I40E_AQC_REPLACE_L1_FILTER 0x0
1605 #define I40E_AQC_REPLACE_CLOUD_FILTER 0x1
1606 #define I40E_AQC_GET_CLOUD_FILTERS 0x2
1607 #define I40E_AQC_MIRROR_CLOUD_FILTER 0x4
1608 #define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
1627 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
1644 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf);
1646 /* Add Mirror Rule (indirect or direct 0x0260)
1647 * Delete Mirror Rule (indirect or direct 0x0261)
1654 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1655 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1681 /* DCB 0x03xx*/
1683 /* PFC Ignore (direct 0x0301)
1689 #define I40E_AQC_PFC_IGNORE_SET 0x80
1690 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1696 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1700 /* TX scheduler 0x04xx */
1719 /* Configure VSI BW limits (direct 0x0400) */
1725 u8 max_credit; /* 0-3, limit = 2^max */
1731 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1739 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1744 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1746 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1757 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1759 /* Query vsi bw configuration (indirect 0x0408) */
1768 u8 max_bw; /* 0-3, limit = 2^max */
1772 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1774 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1781 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1785 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1787 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1793 u8 max_bw; /* 0-3, limit = 2^max */
1799 /* Enable Physical Port ETS (indirect 0x0413)
1800 * Modify Physical Port ETS (indirect 0x0414)
1801 * Disable Physical Port ETS (indirect 0x0415)
1807 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1814 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1816 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1822 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1827 I40E_CHECK_STRUCT_LEN(0x40,
1831 * (indirect 0x0417)
1841 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1843 /* Query Switching Component Configuration (indirect 0x0418) */
1849 u8 tc_bw_max; /* 0-3, limit = 2^max */
1853 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1855 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1865 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1870 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1873 * (indirect 0x041A)
1882 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1886 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1889 * (direct 0x041B and 0x041C) uses the generic SEID struct
1893 * (indirect 0x041D)
1901 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1904 * (direct 0x0500) and (direct 0x0501)
1915 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1921 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1924 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1925 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1928 I40E_PHY_TYPE_SGMII = 0x0,
1929 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1930 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1931 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1932 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1933 I40E_PHY_TYPE_XAUI = 0x5,
1934 I40E_PHY_TYPE_XFI = 0x6,
1935 I40E_PHY_TYPE_SFI = 0x7,
1936 I40E_PHY_TYPE_XLAUI = 0x8,
1937 I40E_PHY_TYPE_XLPPI = 0x9,
1938 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1939 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1940 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1941 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1942 I40E_PHY_TYPE_UNRECOGNIZED = 0xE,
1943 I40E_PHY_TYPE_UNSUPPORTED = 0xF,
1944 I40E_PHY_TYPE_100BASE_TX = 0x11,
1945 I40E_PHY_TYPE_1000BASE_T = 0x12,
1946 I40E_PHY_TYPE_10GBASE_T = 0x13,
1947 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1948 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1949 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1950 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1951 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1952 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1953 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1954 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1955 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1956 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1957 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1958 I40E_PHY_TYPE_25GBASE_KR = 0x1F,
1959 I40E_PHY_TYPE_25GBASE_CR = 0x20,
1960 I40E_PHY_TYPE_25GBASE_SR = 0x21,
1961 I40E_PHY_TYPE_25GBASE_LR = 0x22,
1962 I40E_PHY_TYPE_25GBASE_AOC = 0x23,
1963 I40E_PHY_TYPE_25GBASE_ACC = 0x24,
1964 I40E_PHY_TYPE_2_5GBASE_T = 0x26,
1965 I40E_PHY_TYPE_5GBASE_T = 0x27,
1966 I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS = 0x30,
1967 I40E_PHY_TYPE_5GBASE_T_LINK_STATUS = 0x31,
1969 I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
1970 I40E_PHY_TYPE_EMPTY = 0xFE,
1971 I40E_PHY_TYPE_DEFAULT = 0xFF,
2013 #define I40E_LINK_SPEED_2_5GB_SHIFT 0x0
2014 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
2015 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
2016 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
2017 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
2018 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
2019 #define I40E_LINK_SPEED_25GB_SHIFT 0x6
2020 #define I40E_LINK_SPEED_5GB_SHIFT 0x7
2023 I40E_LINK_SPEED_UNKNOWN = 0,
2042 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
2048 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
2049 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
2050 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
2051 #define I40E_AQ_PHY_LINK_ENABLED 0x08
2052 #define I40E_AQ_PHY_AN_ENABLED 0x10
2053 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
2054 #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40
2055 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80
2057 #define I40E_AQ_EEE_AUTO 0x0001
2058 #define I40E_AQ_EEE_100BASE_TX 0x0002
2059 #define I40E_AQ_EEE_1000BASE_T 0x0004
2060 #define I40E_AQ_EEE_10GBASE_T 0x0008
2061 #define I40E_AQ_EEE_1000BASE_KX 0x0010
2062 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
2063 #define I40E_AQ_EEE_10GBASE_KR 0x0040
2064 #define I40E_AQ_EEE_2_5GBASE_T 0x0100
2065 #define I40E_AQ_EEE_5GBASE_T 0x0200
2068 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
2070 #define I40E_AQ_PHY_TYPE_EXT_25G_KR 0x01
2071 #define I40E_AQ_PHY_TYPE_EXT_25G_CR 0x02
2072 #define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04
2073 #define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08
2074 #define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10
2075 #define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20
2076 #define I40E_AQ_PHY_TYPE_EXT_2_5GBASE_T 0x40
2077 #define I40E_AQ_PHY_TYPE_EXT_5GBASE_T 0x80
2079 #define I40E_AQ_ENABLE_FEC_KR 0x01
2080 #define I40E_AQ_ENABLE_FEC_RS 0x02
2081 #define I40E_AQ_REQUEST_FEC_KR 0x04
2082 #define I40E_AQ_REQUEST_FEC_RS 0x08
2083 #define I40E_AQ_ENABLE_FEC_AUTO 0x10
2085 #define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0
2096 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
2098 /* Set PHY Config (direct 0x0601) */
2103 /* bits 0-2 use the values from get_phy_abilities_resp */
2104 #define I40E_AQ_PHY_ENABLE_LINK 0x08
2105 #define I40E_AQ_PHY_ENABLE_AN 0x10
2106 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
2112 #define I40E_AQ_SET_FEC_ABILITY_KR BIT(0)
2117 #define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0
2118 #define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT)
2124 /* Set MAC Config command data structure (direct 0x0603) */
2128 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
2129 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
2131 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
2132 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
2133 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
2134 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
2135 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
2136 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
2137 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
2138 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
2139 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
2140 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
2141 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
2142 #define I40E_AQ_SET_MAC_CONFIG_DROP_BLOCKING_PACKET_EN 0x80
2151 /* Restart Auto-Negotiation (direct 0x605) */
2154 #define I40E_AQ_PHY_RESTART_AN 0x02
2155 #define I40E_AQ_PHY_LINK_ENABLE 0x04
2161 /* Get Link Status cmd & response data structure (direct 0x0607) */
2164 #define I40E_AQ_LSE_MASK 0x3
2165 #define I40E_AQ_LSE_NOP 0x0
2166 #define I40E_AQ_LSE_DISABLE 0x2
2167 #define I40E_AQ_LSE_ENABLE 0x3
2169 #define I40E_AQ_LSE_IS_ENABLED 0x1
2173 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
2174 #define I40E_AQ_LINK_UP_FUNCTION 0x01
2175 #define I40E_AQ_LINK_FAULT 0x02
2176 #define I40E_AQ_LINK_FAULT_TX 0x04
2177 #define I40E_AQ_LINK_FAULT_RX 0x08
2178 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
2179 #define I40E_AQ_LINK_UP_PORT 0x20
2180 #define I40E_AQ_MEDIA_AVAILABLE 0x40
2181 #define I40E_AQ_SIGNAL_DETECT 0x80
2183 #define I40E_AQ_AN_COMPLETED 0x01
2184 #define I40E_AQ_LP_AN_ABILITY 0x02
2185 #define I40E_AQ_PD_FAULT 0x04
2186 #define I40E_AQ_FEC_EN 0x08
2187 #define I40E_AQ_PHY_LOW_POWER 0x10
2188 #define I40E_AQ_LINK_PAUSE_TX 0x20
2189 #define I40E_AQ_LINK_PAUSE_RX 0x40
2190 #define I40E_AQ_QUALIFIED_MODULE 0x80
2192 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
2193 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
2194 #define I40E_AQ_LINK_TX_SHIFT 0x02
2195 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
2196 #define I40E_AQ_LINK_TX_ACTIVE 0x00
2197 #define I40E_AQ_LINK_TX_DRAINED 0x01
2198 #define I40E_AQ_LINK_TX_FLUSHED 0x03
2199 #define I40E_AQ_LINK_FORCED_40G 0x10
2201 #define I40E_AQ_25G_NO_ERR 0X00
2202 #define I40E_AQ_25G_NOT_PRESENT 0X01
2203 #define I40E_AQ_25G_NVM_CRC_ERR 0X02
2204 #define I40E_AQ_25G_SBUS_UCODE_ERR 0X03
2205 #define I40E_AQ_25G_SERDES_UCODE_ERR 0X04
2206 #define I40E_AQ_25G_NIMB_UCODE_ERR 0X05
2209 #define I40E_AQ_LOOPBACK_MASK 0x07
2211 #define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB)
2214 #define I40E_AQ_CONFIG_FEC_KR_ENA 0x01
2215 #define I40E_AQ_CONFIG_FEC_RS_ENA 0x02
2216 #define I40E_AQ_CONFIG_CRC_ENA 0x04
2217 #define I40E_AQ_CONFIG_PACING_MASK 0x78
2221 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
2222 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
2223 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
2224 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
2225 #define I40E_AQ_PWR_CLASS_MASK 0x03
2237 /* Set event mask command (direct 0x613) */
2241 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
2242 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
2243 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
2244 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
2245 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
2246 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
2247 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
2248 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
2249 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2255 /* Get Local AN advt register (direct 0x0614)
2256 * Set Local AN advt register (direct 0x0615)
2257 * Get Link Partner AN advt register (direct 0x0616)
2267 /* Set Loopback mode (0x0618) */
2270 #define I40E_AQ_LB_NONE 0
2277 #define I40E_AQ_LB_PHY_LOCAL 0x01
2278 #define I40E_AQ_LB_PHY_REMOTE 0x02
2279 #define I40E_AQ_LB_MAC_LOCAL 0x04
2281 #define I40E_AQ_LB_LOCAL 0
2282 #define I40E_AQ_LB_FAR 0x01
2284 #define I40E_AQ_LB_SPEED_NONE 0
2295 /* Set PHY Debug command (0x0622) */
2298 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
2300 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
2302 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
2303 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
2304 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
2306 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
2308 #define I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
2315 I40E_AQC_PHY_REG_INTERNAL = 0x1,
2316 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
2317 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2321 /* Run PHY Activity (0x0626) */
2325 #define I40E_AQ_RUN_PHY_ACT_ID_USR_DFND 0x10
2330 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT_DUR 0x801a
2331 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_STAT 0x801b
2332 #define I40E_AQ_RUN_PHY_ACT_DNL_OPCODE_GET_EEE_DUR 0x1801b
2338 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_SUCC 0x4
2339 #define I40E_AQ_RUN_PHY_ACT_CMD_STAT_MASK 0xFFFF
2349 /* Set PHY Register command (0x0628) */
2350 /* Get PHY Register command (0x0629) */
2353 #define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0
2358 #define I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE 0x01
2359 #define I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER 0x02
2361 #define I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK (0x3 << \
2371 /* NVM Read command (indirect 0x0701)
2372 * NVM Erase commands (direct 0x0702)
2373 * NVM Update commands (indirect 0x0703)
2377 #define I40E_AQ_NVM_LAST_CMD 0x01
2378 #define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20
2379 #define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40
2380 #define I40E_AQ_NVM_FLASH_ONLY 0x80
2382 #define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
2383 #define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2384 #define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
2394 /* NVM Config Read (indirect 0x0704) */
2398 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
2409 /* NVM Config Write (indirect 0x0705) */
2420 /* Used for 0x0704 as well as for 0x0705 commands */
2424 #define I40E_AQ_ANVM_FEATURE 0
2428 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
2429 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
2430 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
2435 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
2437 /* NVM Update in Process (direct 0x0706) */
2440 #define I40E_AQ_UPDATE_FLOW_END 0x0
2441 #define I40E_AQ_UPDATE_FLOW_START 0x1
2454 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
2456 /* Minimal Rollback Revision Update (direct 0x0707) */
2459 #define I40E_AQ_RREV_OPTIN_MODE 0x01
2461 #define I40E_AQ_RREV_MODULE_PCIE_ANALOG 0
2477 /* OEM Post Update (indirect 0x0720)
2481 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
2486 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
2495 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
2497 /* Thermal Sensor (indirect 0x0721)
2503 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
2513 /* Send to PF command (indirect 0x0801) id is only used by PF
2514 * Send to VF command (indirect 0x0802) id is only used by PF
2515 * Send to Peer PF command (indirect 0x0803)
2528 /* Direct write (direct 0x0900)
2529 * Direct read (direct 0x0902)
2540 /* Indirect write (indirect 0x0901)
2541 * Indirect read (indirect 0x0903)
2553 /* Done alternate write (direct 0x0904)
2559 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2567 /* Set OEM mode (direct 0x0905) */
2570 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2577 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2579 /* async events 0x10xx */
2581 /* Lan Queue Overflow Event (direct, 0x1001) */
2590 /* Get LLDP MIB (indirect 0x0A00) */
2594 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2595 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2596 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2597 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2598 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2599 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2600 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2601 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2602 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2603 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2614 /* Configure LLDP MIB Change Event (direct 0x0A01)
2619 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2620 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2628 /* Add LLDP TLV (indirect 0x0A02)
2629 * Delete LLDP TLV (indirect 0x0A04)
2632 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2642 /* Update LLDP TLV (indirect 0x0A03) */
2644 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2655 /* Stop LLDP (direct 0x0A05) */
2658 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2659 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2660 #define I40E_AQ_LLDP_AGENT_STOP_PERSIST 0x2
2666 /* Start LLDP (direct 0x0A06) */
2669 #define I40E_AQ_LLDP_AGENT_START 0x1
2670 #define I40E_AQ_LLDP_AGENT_START_PERSIST 0x2
2676 /* Set DCB (direct 0x0303) */
2679 #define I40E_AQ_DCB_SET_AGENT 0x1
2680 #define I40E_DCB_VALID 0x1
2687 /* Get CEE DCBX Oper Config (0x0A07)
2692 #define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0
2693 #define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT)
2694 #define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3
2695 #define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT)
2696 #define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2697 #define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2699 #define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2700 #define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2701 #define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2702 #define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2703 #define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2704 #define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2705 #define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2706 #define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2707 #define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2708 #define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2709 #define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2710 #define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2733 I40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp);
2745 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp);
2747 /* Set Local LLDP MIB (indirect 0x0A08)
2751 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
2754 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2758 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
2770 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK 0x01
2775 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_lldp_set_local_mib_resp);
2777 /* Stop/Start LLDP Agent (direct 0x0A09)
2781 #define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0
2790 /* Restore LLDP Agent factory settings (direct 0x0A0A) */
2793 #define I40E_AQ_LLDP_AGENT_RESTORE_NOT 0x0
2794 #define I40E_AQ_LLDP_AGENT_RESTORE 0x1
2800 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2805 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2806 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2807 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2808 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2818 #define I40E_AQC_SINGLE_PF 0x0
2819 #define I40E_AQC_MULTIPLE_PFS 0x1
2826 /* remove UDP Tunnel command (0x0B01) */
2829 u8 index; /* 0 to 15 */
2837 u8 index; /* 0 to 15 */
2846 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2847 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2848 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2859 u8 standard_rss_key[0x28];
2860 u8 extended_hash_key[0xc];
2863 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2866 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2867 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2868 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2871 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2872 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2875 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2885 /* tunnel key structure 0x0B10 */
2890 u8 key1_len; /* 0 to 15 */
2891 u8 key2_len; /* 0 to 15 */
2893 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2895 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2896 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2897 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2899 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2900 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2901 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2902 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2908 /* OEM mode commands (direct 0xFE0x) */
2911 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2923 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2924 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2930 /* Initialize OCSD (0xFE02, direct) */
2941 /* Initialize OCBB (0xFE03, direct) */
2954 /* get device id (0xFF00) uses the generic structure */
2956 /* set test more (0xFF01, internal) */
2960 #define I40E_AQ_TEST_PARTIAL 0
2965 #define I40E_AQ_TEST_OPEN 0
2975 /* Debug Read Register command (0xFF03)
2976 * Debug Write Register command (0xFF04)
2987 /* Scatter/gather Reg Read (indirect 0xFF05)
2988 * Scatter/gather Reg Write (indirect 0xFF06)
2997 /* Debug Modify register (direct 0xFF07) */
3007 /* dump internal data (0xFF08, indirect) */
3009 #define I40E_AQ_CLUSTER_ID_AUX 0