Lines Matching full:hw
42 * @hw: pointer to the hardware structure
46 static void i40e_adminq_init_regs(struct i40e_hw *hw) in i40e_adminq_init_regs() argument
49 if (i40e_is_vf(hw)) { in i40e_adminq_init_regs()
50 hw->aq.asq.tail = I40E_VF_ATQT1; in i40e_adminq_init_regs()
51 hw->aq.asq.head = I40E_VF_ATQH1; in i40e_adminq_init_regs()
52 hw->aq.asq.len = I40E_VF_ATQLEN1; in i40e_adminq_init_regs()
53 hw->aq.asq.bal = I40E_VF_ATQBAL1; in i40e_adminq_init_regs()
54 hw->aq.asq.bah = I40E_VF_ATQBAH1; in i40e_adminq_init_regs()
55 hw->aq.arq.tail = I40E_VF_ARQT1; in i40e_adminq_init_regs()
56 hw->aq.arq.head = I40E_VF_ARQH1; in i40e_adminq_init_regs()
57 hw->aq.arq.len = I40E_VF_ARQLEN1; in i40e_adminq_init_regs()
58 hw->aq.arq.bal = I40E_VF_ARQBAL1; in i40e_adminq_init_regs()
59 hw->aq.arq.bah = I40E_VF_ARQBAH1; in i40e_adminq_init_regs()
61 hw->aq.asq.tail = I40E_PF_ATQT; in i40e_adminq_init_regs()
62 hw->aq.asq.head = I40E_PF_ATQH; in i40e_adminq_init_regs()
63 hw->aq.asq.len = I40E_PF_ATQLEN; in i40e_adminq_init_regs()
64 hw->aq.asq.bal = I40E_PF_ATQBAL; in i40e_adminq_init_regs()
65 hw->aq.asq.bah = I40E_PF_ATQBAH; in i40e_adminq_init_regs()
66 hw->aq.arq.tail = I40E_PF_ARQT; in i40e_adminq_init_regs()
67 hw->aq.arq.head = I40E_PF_ARQH; in i40e_adminq_init_regs()
68 hw->aq.arq.len = I40E_PF_ARQLEN; in i40e_adminq_init_regs()
69 hw->aq.arq.bal = I40E_PF_ARQBAL; in i40e_adminq_init_regs()
70 hw->aq.arq.bah = I40E_PF_ARQBAH; in i40e_adminq_init_regs()
76 * @hw: pointer to the hardware structure
78 enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_asq_ring() argument
82 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq.desc_buf, in i40e_alloc_adminq_asq_ring()
84 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
90 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.cmd_buf, in i40e_alloc_adminq_asq_ring()
91 (hw->aq.num_asq_entries * in i40e_alloc_adminq_asq_ring()
94 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_alloc_adminq_asq_ring()
103 * @hw: pointer to the hardware structure
105 enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw) in i40e_alloc_adminq_arq_ring() argument
109 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq.desc_buf, in i40e_alloc_adminq_arq_ring()
111 (hw->aq.num_arq_entries * in i40e_alloc_adminq_arq_ring()
120 * @hw: pointer to the hardware structure
125 void i40e_free_adminq_asq(struct i40e_hw *hw) in i40e_free_adminq_asq() argument
127 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); in i40e_free_adminq_asq()
128 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_adminq_asq()
133 * @hw: pointer to the hardware structure
138 void i40e_free_adminq_arq(struct i40e_hw *hw) in i40e_free_adminq_arq() argument
140 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_adminq_arq()
145 * @hw: pointer to the hardware structure
147 static enum i40e_status_code i40e_alloc_arq_bufs(struct i40e_hw *hw) in i40e_alloc_arq_bufs() argument
159 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.arq.dma_head, in i40e_alloc_arq_bufs()
160 (hw->aq.num_arq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_arq_bufs()
163 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)hw->aq.arq.dma_head.va; in i40e_alloc_arq_bufs()
166 for (i = 0; i < hw->aq.num_arq_entries; i++) { in i40e_alloc_arq_bufs()
167 bi = &hw->aq.arq.r.arq_bi[i]; in i40e_alloc_arq_bufs()
168 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_arq_bufs()
170 hw->aq.arq_buf_size, in i40e_alloc_arq_bufs()
176 desc = I40E_ADMINQ_DESC(hw->aq.arq, i); in i40e_alloc_arq_bufs()
179 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_alloc_arq_bufs()
204 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_alloc_arq_bufs()
205 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_alloc_arq_bufs()
212 * @hw: pointer to the hardware structure
214 static enum i40e_status_code i40e_alloc_asq_bufs(struct i40e_hw *hw) in i40e_alloc_asq_bufs() argument
221 ret_code = i40e_allocate_virt_mem(hw, &hw->aq.asq.dma_head, in i40e_alloc_asq_bufs()
222 (hw->aq.num_asq_entries * sizeof(struct i40e_dma_mem))); in i40e_alloc_asq_bufs()
225 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)hw->aq.asq.dma_head.va; in i40e_alloc_asq_bufs()
228 for (i = 0; i < hw->aq.num_asq_entries; i++) { in i40e_alloc_asq_bufs()
229 bi = &hw->aq.asq.r.asq_bi[i]; in i40e_alloc_asq_bufs()
230 ret_code = i40e_allocate_dma_mem(hw, bi, in i40e_alloc_asq_bufs()
232 hw->aq.asq_buf_size, in i40e_alloc_asq_bufs()
244 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_alloc_asq_bufs()
245 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_alloc_asq_bufs()
252 * @hw: pointer to the hardware structure
254 static void i40e_free_arq_bufs(struct i40e_hw *hw) in i40e_free_arq_bufs() argument
259 for (i = 0; i < hw->aq.num_arq_entries; i++) in i40e_free_arq_bufs()
260 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]); in i40e_free_arq_bufs()
263 i40e_free_dma_mem(hw, &hw->aq.arq.desc_buf); in i40e_free_arq_bufs()
266 i40e_free_virt_mem(hw, &hw->aq.arq.dma_head); in i40e_free_arq_bufs()
271 * @hw: pointer to the hardware structure
273 static void i40e_free_asq_bufs(struct i40e_hw *hw) in i40e_free_asq_bufs() argument
278 for (i = 0; i < hw->aq.num_asq_entries; i++) in i40e_free_asq_bufs()
279 if (hw->aq.asq.r.asq_bi[i].pa) in i40e_free_asq_bufs()
280 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]); in i40e_free_asq_bufs()
283 i40e_free_virt_mem(hw, &hw->aq.asq.cmd_buf); in i40e_free_asq_bufs()
286 i40e_free_dma_mem(hw, &hw->aq.asq.desc_buf); in i40e_free_asq_bufs()
289 i40e_free_virt_mem(hw, &hw->aq.asq.dma_head); in i40e_free_asq_bufs()
294 * @hw: pointer to the hardware structure
298 static enum i40e_status_code i40e_config_asq_regs(struct i40e_hw *hw) in i40e_config_asq_regs() argument
304 wr32(hw, hw->aq.asq.head, 0); in i40e_config_asq_regs()
305 wr32(hw, hw->aq.asq.tail, 0); in i40e_config_asq_regs()
308 if (!i40e_is_vf(hw)) in i40e_config_asq_regs()
309 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
311 if (i40e_is_vf(hw)) in i40e_config_asq_regs()
312 wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries | in i40e_config_asq_regs()
314 wr32(hw, hw->aq.asq.bal, I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
315 wr32(hw, hw->aq.asq.bah, I40E_HI_DWORD(hw->aq.asq.desc_buf.pa)); in i40e_config_asq_regs()
318 reg = rd32(hw, hw->aq.asq.bal); in i40e_config_asq_regs()
319 if (reg != I40E_LO_DWORD(hw->aq.asq.desc_buf.pa)) in i40e_config_asq_regs()
327 * @hw: pointer to the hardware structure
331 static enum i40e_status_code i40e_config_arq_regs(struct i40e_hw *hw) in i40e_config_arq_regs() argument
337 wr32(hw, hw->aq.arq.head, 0); in i40e_config_arq_regs()
338 wr32(hw, hw->aq.arq.tail, 0); in i40e_config_arq_regs()
341 if (!i40e_is_vf(hw)) in i40e_config_arq_regs()
342 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
344 if (i40e_is_vf(hw)) in i40e_config_arq_regs()
345 wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries | in i40e_config_arq_regs()
347 wr32(hw, hw->aq.arq.bal, I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
348 wr32(hw, hw->aq.arq.bah, I40E_HI_DWORD(hw->aq.arq.desc_buf.pa)); in i40e_config_arq_regs()
350 /* Update tail in the HW to post pre-allocated buffers */ in i40e_config_arq_regs()
351 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1); in i40e_config_arq_regs()
354 reg = rd32(hw, hw->aq.arq.bal); in i40e_config_arq_regs()
355 if (reg != I40E_LO_DWORD(hw->aq.arq.desc_buf.pa)) in i40e_config_arq_regs()
363 * @hw: pointer to the hardware structure
367 * in the hw->aq structure:
368 * - hw->aq.num_asq_entries
369 * - hw->aq.arq_buf_size
374 enum i40e_status_code i40e_init_asq(struct i40e_hw *hw) in i40e_init_asq() argument
378 if (hw->aq.asq.count > 0) { in i40e_init_asq()
385 if ((hw->aq.num_asq_entries == 0) || in i40e_init_asq()
386 (hw->aq.asq_buf_size == 0)) { in i40e_init_asq()
391 hw->aq.asq.next_to_use = 0; in i40e_init_asq()
392 hw->aq.asq.next_to_clean = 0; in i40e_init_asq()
395 ret_code = i40e_alloc_adminq_asq_ring(hw); in i40e_init_asq()
400 ret_code = i40e_alloc_asq_bufs(hw); in i40e_init_asq()
405 ret_code = i40e_config_asq_regs(hw); in i40e_init_asq()
410 hw->aq.asq.count = hw->aq.num_asq_entries; in i40e_init_asq()
414 i40e_free_adminq_asq(hw); in i40e_init_asq()
418 i40e_free_asq_bufs(hw); in i40e_init_asq()
426 * @hw: pointer to the hardware structure
430 * in the hw->aq structure:
431 * - hw->aq.num_asq_entries
432 * - hw->aq.arq_buf_size
437 enum i40e_status_code i40e_init_arq(struct i40e_hw *hw) in i40e_init_arq() argument
441 if (hw->aq.arq.count > 0) { in i40e_init_arq()
448 if ((hw->aq.num_arq_entries == 0) || in i40e_init_arq()
449 (hw->aq.arq_buf_size == 0)) { in i40e_init_arq()
454 hw->aq.arq.next_to_use = 0; in i40e_init_arq()
455 hw->aq.arq.next_to_clean = 0; in i40e_init_arq()
458 ret_code = i40e_alloc_adminq_arq_ring(hw); in i40e_init_arq()
463 ret_code = i40e_alloc_arq_bufs(hw); in i40e_init_arq()
468 ret_code = i40e_config_arq_regs(hw); in i40e_init_arq()
473 hw->aq.arq.count = hw->aq.num_arq_entries; in i40e_init_arq()
477 i40e_free_adminq_arq(hw); in i40e_init_arq()
485 * @hw: pointer to the hardware structure
489 enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw) in i40e_shutdown_asq() argument
493 i40e_acquire_spinlock(&hw->aq.asq_spinlock); in i40e_shutdown_asq()
495 if (hw->aq.asq.count == 0) { in i40e_shutdown_asq()
501 wr32(hw, hw->aq.asq.head, 0); in i40e_shutdown_asq()
502 wr32(hw, hw->aq.asq.tail, 0); in i40e_shutdown_asq()
503 wr32(hw, hw->aq.asq.len, 0); in i40e_shutdown_asq()
504 wr32(hw, hw->aq.asq.bal, 0); in i40e_shutdown_asq()
505 wr32(hw, hw->aq.asq.bah, 0); in i40e_shutdown_asq()
507 hw->aq.asq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_asq()
510 i40e_free_asq_bufs(hw); in i40e_shutdown_asq()
513 i40e_release_spinlock(&hw->aq.asq_spinlock); in i40e_shutdown_asq()
519 * @hw: pointer to the hardware structure
523 enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw) in i40e_shutdown_arq() argument
527 i40e_acquire_spinlock(&hw->aq.arq_spinlock); in i40e_shutdown_arq()
529 if (hw->aq.arq.count == 0) { in i40e_shutdown_arq()
535 wr32(hw, hw->aq.arq.head, 0); in i40e_shutdown_arq()
536 wr32(hw, hw->aq.arq.tail, 0); in i40e_shutdown_arq()
537 wr32(hw, hw->aq.arq.len, 0); in i40e_shutdown_arq()
538 wr32(hw, hw->aq.arq.bal, 0); in i40e_shutdown_arq()
539 wr32(hw, hw->aq.arq.bah, 0); in i40e_shutdown_arq()
541 hw->aq.arq.count = 0; /* to indicate uninitialized queue */ in i40e_shutdown_arq()
544 i40e_free_arq_bufs(hw); in i40e_shutdown_arq()
547 i40e_release_spinlock(&hw->aq.arq_spinlock); in i40e_shutdown_arq()
553 * @hw: pointer to the hardware structure
555 static void i40e_resume_aq(struct i40e_hw *hw) in i40e_resume_aq() argument
558 hw->aq.asq.next_to_use = 0; in i40e_resume_aq()
559 hw->aq.asq.next_to_clean = 0; in i40e_resume_aq()
561 i40e_config_asq_regs(hw); in i40e_resume_aq()
563 hw->aq.arq.next_to_use = 0; in i40e_resume_aq()
564 hw->aq.arq.next_to_clean = 0; in i40e_resume_aq()
566 i40e_config_arq_regs(hw); in i40e_resume_aq()
570 * i40e_set_hw_flags - set HW flags
571 * @hw: pointer to the hardware structure
573 static void i40e_set_hw_flags(struct i40e_hw *hw) in i40e_set_hw_flags() argument
575 struct i40e_adminq_info *aq = &hw->aq; in i40e_set_hw_flags()
577 hw->flags = 0; in i40e_set_hw_flags()
579 switch (hw->mac.type) { in i40e_set_hw_flags()
584 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; in i40e_set_hw_flags()
585 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_set_hw_flags()
587 hw->flags |= I40E_HW_FLAG_802_1AD_CAPABLE; in i40e_set_hw_flags()
591 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE | in i40e_set_hw_flags()
597 hw->flags |= I40E_HW_FLAG_FW_LLDP_STOPPABLE; in i40e_set_hw_flags()
602 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE; in i40e_set_hw_flags()
607 hw->flags |= I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE; in i40e_set_hw_flags()
618 hw->flags |= I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK; in i40e_set_hw_flags()
623 hw->flags |= I40E_HW_FLAG_FW_LLDP_PERSISTENT; in i40e_set_hw_flags()
624 hw->flags |= I40E_HW_FLAG_DROP_MODE; in i40e_set_hw_flags()
630 hw->flags |= I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED; in i40e_set_hw_flags()
635 * @hw: pointer to the hardware structure
638 * in the hw->aq structure:
639 * - hw->aq.num_asq_entries
640 * - hw->aq.num_arq_entries
641 * - hw->aq.arq_buf_size
642 * - hw->aq.asq_buf_size
644 enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw) in i40e_init_adminq() argument
646 struct i40e_adminq_info *aq = &hw->aq; in i40e_init_adminq()
666 i40e_adminq_init_regs(hw); in i40e_init_adminq()
669 hw->aq.asq_cmd_timeout = I40E_ASQ_CMD_TIMEOUT; in i40e_init_adminq()
672 ret_code = i40e_init_asq(hw); in i40e_init_adminq()
677 ret_code = i40e_init_arq(hw); in i40e_init_adminq()
682 if (i40e_is_vf(hw)) in i40e_init_adminq()
689 ret_code = i40e_aq_get_firmware_version(hw, in i40e_init_adminq()
700 i40e_resume_aq(hw); in i40e_init_adminq()
709 i40e_set_hw_flags(hw); in i40e_init_adminq()
712 i40e_read_nvm_word(hw, I40E_SR_NVM_DEV_STARTER_VERSION, in i40e_init_adminq()
713 &hw->nvm.version); in i40e_init_adminq()
714 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo); in i40e_init_adminq()
715 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi); in i40e_init_adminq()
716 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; in i40e_init_adminq()
717 i40e_read_nvm_word(hw, I40E_SR_BOOT_CONFIG_PTR, &cfg_ptr); in i40e_init_adminq()
718 i40e_read_nvm_word(hw, (cfg_ptr + I40E_NVM_OEM_VER_OFF), in i40e_init_adminq()
720 i40e_read_nvm_word(hw, (cfg_ptr + (I40E_NVM_OEM_VER_OFF + 1)), in i40e_init_adminq()
722 hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo; in i40e_init_adminq()
730 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL); in i40e_init_adminq()
731 hw->nvm_release_on_done = FALSE; in i40e_init_adminq()
732 hw->nvmupd_state = I40E_NVMUPD_STATE_INIT; in i40e_init_adminq()
740 i40e_shutdown_arq(hw); in i40e_init_adminq()
742 i40e_shutdown_asq(hw); in i40e_init_adminq()
753 * @hw: pointer to the hardware structure
755 enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw) in i40e_shutdown_adminq() argument
759 if (i40e_check_asq_alive(hw)) in i40e_shutdown_adminq()
760 i40e_aq_queue_shutdown(hw, TRUE); in i40e_shutdown_adminq()
762 i40e_shutdown_asq(hw); in i40e_shutdown_adminq()
763 i40e_shutdown_arq(hw); in i40e_shutdown_adminq()
764 i40e_destroy_spinlock(&hw->aq.asq_spinlock); in i40e_shutdown_adminq()
765 i40e_destroy_spinlock(&hw->aq.arq_spinlock); in i40e_shutdown_adminq()
767 if (hw->nvm_buff.va) in i40e_shutdown_adminq()
768 i40e_free_virt_mem(hw, &hw->nvm_buff); in i40e_shutdown_adminq()
775 * @hw: pointer to the hardware structure
779 u16 i40e_clean_asq(struct i40e_hw *hw) in i40e_clean_asq() argument
781 struct i40e_adminq_ring *asq = &(hw->aq.asq); in i40e_clean_asq()
789 while (rd32(hw, hw->aq.asq.head) != ntc) { in i40e_clean_asq()
790 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_clean_asq()
791 "ntc %d head %d.\n", ntc, rd32(hw, hw->aq.asq.head)); in i40e_clean_asq()
798 cb_func(hw, &desc_cb); in i40e_clean_asq()
816 * @hw: pointer to the hw struct
821 bool i40e_asq_done(struct i40e_hw *hw) in i40e_asq_done() argument
826 return rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use; in i40e_asq_done()
832 * @hw: pointer to the hw struct
841 enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw, in i40e_asq_send_command() argument
855 i40e_acquire_spinlock(&hw->aq.asq_spinlock); in i40e_asq_send_command()
857 hw->aq.asq_last_status = I40E_AQ_RC_OK; in i40e_asq_send_command()
859 if (hw->aq.asq.count == 0) { in i40e_asq_send_command()
860 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command()
866 val = rd32(hw, hw->aq.asq.head); in i40e_asq_send_command()
867 if (val >= hw->aq.num_asq_entries) { in i40e_asq_send_command()
868 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command()
874 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command()
901 if (buff_size > hw->aq.asq_buf_size) { in i40e_asq_send_command()
902 i40e_debug(hw, in i40e_asq_send_command()
911 i40e_debug(hw, in i40e_asq_send_command()
925 if (i40e_clean_asq(hw) == 0) { in i40e_asq_send_command()
926 i40e_debug(hw, in i40e_asq_send_command()
934 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use); in i40e_asq_send_command()
942 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]); in i40e_asq_send_command()
958 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQTX: desc and buffer:\n"); in i40e_asq_send_command()
959 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, in i40e_asq_send_command()
961 (hw->aq.asq.next_to_use)++; in i40e_asq_send_command()
962 if (hw->aq.asq.next_to_use == hw->aq.asq.count) in i40e_asq_send_command()
963 hw->aq.asq.next_to_use = 0; in i40e_asq_send_command()
965 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use); in i40e_asq_send_command()
977 if (i40e_asq_done(hw)) in i40e_asq_send_command()
981 } while (total_delay < hw->aq.asq_cmd_timeout); in i40e_asq_send_command()
985 if (i40e_asq_done(hw)) { in i40e_asq_send_command()
993 i40e_debug(hw, in i40e_asq_send_command()
1008 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval; in i40e_asq_send_command()
1011 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, in i40e_asq_send_command()
1013 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size); in i40e_asq_send_command()
1023 if (rd32(hw, hw->aq.asq.len) & I40E_GL_ATQLEN_ATQCRIT_MASK) { in i40e_asq_send_command()
1024 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command()
1028 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_asq_send_command()
1035 i40e_release_spinlock(&hw->aq.asq_spinlock); in i40e_asq_send_command()
1058 * @hw: pointer to the hw struct
1066 enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw, in i40e_clean_arq_element() argument
1071 u16 ntc = hw->aq.arq.next_to_clean; in i40e_clean_arq_element()
1083 i40e_acquire_spinlock(&hw->aq.arq_spinlock); in i40e_clean_arq_element()
1085 if (hw->aq.arq.count == 0) { in i40e_clean_arq_element()
1086 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, in i40e_clean_arq_element()
1093 if (!i40e_is_vf(hw)) in i40e_clean_arq_element()
1094 ntu = rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK; in i40e_clean_arq_element()
1096 ntu = rd32(hw, hw->aq.arq.head) & I40E_VF_ARQH1_ARQH_MASK; in i40e_clean_arq_element()
1104 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc); in i40e_clean_arq_element()
1107 hw->aq.arq_last_status = in i40e_clean_arq_element()
1112 i40e_debug(hw, in i40e_clean_arq_element()
1115 hw->aq.arq_last_status); in i40e_clean_arq_element()
1124 hw->aq.arq.r.arq_bi[desc_idx].va, in i40e_clean_arq_element()
1127 i40e_debug(hw, I40E_DEBUG_AQ_COMMAND, "AQRX: desc and buffer:\n"); in i40e_clean_arq_element()
1128 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf, in i40e_clean_arq_element()
1129 hw->aq.arq_buf_size); in i40e_clean_arq_element()
1135 bi = &hw->aq.arq.r.arq_bi[ntc]; in i40e_clean_arq_element()
1139 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF) in i40e_clean_arq_element()
1146 wr32(hw, hw->aq.arq.tail, ntc); in i40e_clean_arq_element()
1149 if (ntc == hw->aq.num_arq_entries) in i40e_clean_arq_element()
1151 hw->aq.arq.next_to_clean = ntc; in i40e_clean_arq_element()
1152 hw->aq.arq.next_to_use = ntu; in i40e_clean_arq_element()
1154 i40e_nvmupd_check_wait_event(hw, LE16_TO_CPU(e->desc.opcode), &e->desc); in i40e_clean_arq_element()
1158 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc); in i40e_clean_arq_element()
1160 i40e_release_spinlock(&hw->aq.arq_spinlock); in i40e_clean_arq_element()