Lines Matching +full:0 +full:- +full:indexed
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
60 for (tc = 0; tc < tc_count; tc++) { in ixgbe_dcb_get_tc_stats_82598()
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc)); in ixgbe_dcb_get_tc_stats_82598()
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc)); in ixgbe_dcb_get_tc_stats_82598()
66 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc)); in ixgbe_dcb_get_tc_stats_82598()
68 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc)); in ixgbe_dcb_get_tc_stats_82598()
75 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
93 for (tc = 0; tc < tc_count; tc++) { in ixgbe_dcb_get_pfc_stats_82598()
95 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc)); in ixgbe_dcb_get_pfc_stats_82598()
97 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc)); in ixgbe_dcb_get_pfc_stats_82598()
104 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
108 * @tsa: transmission selection algorithm indexed by traffic class
115 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598()
116 u32 credit_refill = 0; in ixgbe_dcb_config_rx_arbiter_82598()
117 u32 credit_max = 0; in ixgbe_dcb_config_rx_arbiter_82598()
118 u8 i = 0; in ixgbe_dcb_config_rx_arbiter_82598()
134 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { in ixgbe_dcb_config_rx_arbiter_82598()
161 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
165 * @bwg_id: bandwidth grouping indexed by traffic class
166 * @tsa: transmission selection algorithm indexed by traffic class
184 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); in ixgbe_dcb_config_tx_desc_arbiter_82598()
189 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { in ixgbe_dcb_config_tx_desc_arbiter_82598()
208 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
212 * @bwg_id: bandwidth grouping indexed by traffic class
213 * @tsa: transmission selection algorithm indexed by traffic class
233 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { in ixgbe_dcb_config_tx_data_arbiter_82598()
256 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
283 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { in ixgbe_dcb_config_pfc_82598()
285 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0); in ixgbe_dcb_config_pfc_82598()
286 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0); in ixgbe_dcb_config_pfc_82598()
290 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_dcb_config_pfc_82598()
291 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
297 reg = hw->fc.pause_time | (hw->fc.pause_time << 16); in ixgbe_dcb_config_pfc_82598()
298 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) in ixgbe_dcb_config_pfc_82598()
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_dcb_config_pfc_82598()
308 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
316 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82598()
317 u8 i = 0; in ixgbe_dcb_config_tc_stats_82598()
318 u8 j = 0; in ixgbe_dcb_config_tc_stats_82598()
320 /* Receive Queues stats setting - 8 queues per statistics reg */ in ixgbe_dcb_config_tc_stats_82598()
321 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) { in ixgbe_dcb_config_tc_stats_82598()
323 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
326 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
329 /* Transmit Queues stats setting - 4 queues per statistics reg*/ in ixgbe_dcb_config_tc_stats_82598()
330 for (i = 0; i < 8; i++) { in ixgbe_dcb_config_tc_stats_82598()
332 reg |= ((0x1010101) * i); in ixgbe_dcb_config_tc_stats_82598()
340 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
345 * @bwg_id: bandwidth grouping indexed by traffic class
346 * @tsa: transmission selection algorithm indexed by traffic class