Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
41 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
60 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) in ixgbe_init_ops_generic() argument
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_generic()
72 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_generic()
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_init_ops_generic()
78 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; in ixgbe_init_ops_generic()
81 eeprom->ops.read = ixgbe_read_eerd_generic; in ixgbe_init_ops_generic()
82 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; in ixgbe_init_ops_generic()
84 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; in ixgbe_init_ops_generic()
85 eeprom->ops.read_buffer = in ixgbe_init_ops_generic()
88 eeprom->ops.write = ixgbe_write_eeprom_generic; in ixgbe_init_ops_generic()
89 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic; in ixgbe_init_ops_generic()
90 eeprom->ops.validate_checksum = in ixgbe_init_ops_generic()
92 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic; in ixgbe_init_ops_generic()
93 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic; in ixgbe_init_ops_generic()
96 mac->ops.init_hw = ixgbe_init_hw_generic; in ixgbe_init_ops_generic()
97 mac->ops.reset_hw = NULL; in ixgbe_init_ops_generic()
98 mac->ops.start_hw = ixgbe_start_hw_generic; in ixgbe_init_ops_generic()
99 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic; in ixgbe_init_ops_generic()
100 mac->ops.get_media_type = NULL; in ixgbe_init_ops_generic()
101 mac->ops.get_supported_physical_layer = NULL; in ixgbe_init_ops_generic()
102 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic; in ixgbe_init_ops_generic()
103 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic; in ixgbe_init_ops_generic()
104 mac->ops.stop_adapter = ixgbe_stop_adapter_generic; in ixgbe_init_ops_generic()
105 mac->ops.get_bus_info = ixgbe_get_bus_info_generic; in ixgbe_init_ops_generic()
106 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie; in ixgbe_init_ops_generic()
107 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync; in ixgbe_init_ops_generic()
108 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync; in ixgbe_init_ops_generic()
109 mac->ops.prot_autoc_read = prot_autoc_read_generic; in ixgbe_init_ops_generic()
110 mac->ops.prot_autoc_write = prot_autoc_write_generic; in ixgbe_init_ops_generic()
113 mac->ops.led_on = ixgbe_led_on_generic; in ixgbe_init_ops_generic()
114 mac->ops.led_off = ixgbe_led_off_generic; in ixgbe_init_ops_generic()
115 mac->ops.blink_led_start = ixgbe_blink_led_start_generic; in ixgbe_init_ops_generic()
116 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic; in ixgbe_init_ops_generic()
117 mac->ops.init_led_link_act = ixgbe_init_led_link_act_generic; in ixgbe_init_ops_generic()
120 mac->ops.set_rar = ixgbe_set_rar_generic; in ixgbe_init_ops_generic()
121 mac->ops.clear_rar = ixgbe_clear_rar_generic; in ixgbe_init_ops_generic()
122 mac->ops.insert_mac_addr = NULL; in ixgbe_init_ops_generic()
123 mac->ops.set_vmdq = NULL; in ixgbe_init_ops_generic()
124 mac->ops.clear_vmdq = NULL; in ixgbe_init_ops_generic()
125 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic; in ixgbe_init_ops_generic()
126 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic; in ixgbe_init_ops_generic()
127 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic; in ixgbe_init_ops_generic()
128 mac->ops.enable_mc = ixgbe_enable_mc_generic; in ixgbe_init_ops_generic()
129 mac->ops.disable_mc = ixgbe_disable_mc_generic; in ixgbe_init_ops_generic()
130 mac->ops.clear_vfta = NULL; in ixgbe_init_ops_generic()
131 mac->ops.set_vfta = NULL; in ixgbe_init_ops_generic()
132 mac->ops.set_vlvf = NULL; in ixgbe_init_ops_generic()
133 mac->ops.init_uta_tables = NULL; in ixgbe_init_ops_generic()
134 mac->ops.enable_rx = ixgbe_enable_rx_generic; in ixgbe_init_ops_generic()
135 mac->ops.disable_rx = ixgbe_disable_rx_generic; in ixgbe_init_ops_generic()
136 mac->ops.toggle_txdctl = ixgbe_toggle_txdctl_generic; in ixgbe_init_ops_generic()
138 /* Flow Control */ in ixgbe_init_ops_generic()
139 mac->ops.fc_enable = ixgbe_fc_enable_generic; in ixgbe_init_ops_generic()
140 mac->ops.setup_fc = ixgbe_setup_fc_generic; in ixgbe_init_ops_generic()
141 mac->ops.fc_autoneg = ixgbe_fc_autoneg; in ixgbe_init_ops_generic()
144 mac->ops.get_link_capabilities = NULL; in ixgbe_init_ops_generic()
145 mac->ops.setup_link = NULL; in ixgbe_init_ops_generic()
146 mac->ops.check_link = NULL; in ixgbe_init_ops_generic()
147 mac->ops.dmac_config = NULL; in ixgbe_init_ops_generic()
148 mac->ops.dmac_update_tcs = NULL; in ixgbe_init_ops_generic()
149 mac->ops.dmac_config_tcs = NULL; in ixgbe_init_ops_generic()
155 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
156 * of flow control
157 * @hw: pointer to hardware structure
159 * This function returns true if the device supports flow control
163 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) in ixgbe_device_supports_autoneg_fc() argument
171 switch (hw->phy.media_type) { in ixgbe_device_supports_autoneg_fc()
175 /* flow control autoneg block list */ in ixgbe_device_supports_autoneg_fc()
176 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
184 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_device_supports_autoneg_fc()
195 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_XFI) in ixgbe_device_supports_autoneg_fc()
201 /* only some copper devices support flow control autoneg */ in ixgbe_device_supports_autoneg_fc()
202 switch (hw->device_id) { in ixgbe_device_supports_autoneg_fc()
224 "Device %x does not support flow control autoneg", in ixgbe_device_supports_autoneg_fc()
225 hw->device_id); in ixgbe_device_supports_autoneg_fc()
231 * ixgbe_setup_fc_generic - Set up flow control
232 * @hw: pointer to hardware structure
234 * Called at init time to set up flow control.
236 s32 ixgbe_setup_fc_generic(struct ixgbe_hw *hw) in ixgbe_setup_fc_generic() argument
246 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { in ixgbe_setup_fc_generic()
255 * default flow control setting, so we explicitly set it to full. in ixgbe_setup_fc_generic()
257 if (hw->fc.requested_mode == ixgbe_fc_default) in ixgbe_setup_fc_generic()
258 hw->fc.requested_mode = ixgbe_fc_full; in ixgbe_setup_fc_generic()
261 * Set up the 1G and 10G flow control advertisement registers so the in ixgbe_setup_fc_generic()
262 * HW will be able to do fc autoneg once the cable is plugged in. If in ixgbe_setup_fc_generic()
265 switch (hw->phy.media_type) { in ixgbe_setup_fc_generic()
268 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp); in ixgbe_setup_fc_generic()
272 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
277 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_setup_fc_generic()
281 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, in ixgbe_setup_fc_generic()
290 * 0: Flow control is completely disabled in ixgbe_setup_fc_generic()
291 * 1: Rx flow control is enabled (we can receive pause frames, in ixgbe_setup_fc_generic()
293 * 2: Tx flow control is enabled (we can send pause frames but in ixgbe_setup_fc_generic()
295 * 3: Both Rx and Tx flow control (symmetric) are enabled. in ixgbe_setup_fc_generic()
298 switch (hw->fc.requested_mode) { in ixgbe_setup_fc_generic()
300 /* Flow control completely disabled by software override. */ in ixgbe_setup_fc_generic()
302 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
305 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
310 * Tx Flow control is enabled, and Rx Flow control is in ixgbe_setup_fc_generic()
315 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
318 } else if (hw->phy.media_type == ixgbe_media_type_copper) { in ixgbe_setup_fc_generic()
325 * Rx Flow control is enabled and Tx Flow control is in ixgbe_setup_fc_generic()
334 /* Flow control (both Rx and Tx) is enabled by SW override. */ in ixgbe_setup_fc_generic()
336 if (hw->phy.media_type == ixgbe_media_type_backplane) in ixgbe_setup_fc_generic()
339 else if (hw->phy.media_type == ixgbe_media_type_copper) in ixgbe_setup_fc_generic()
344 "Flow control param set incorrectly\n"); in ixgbe_setup_fc_generic()
350 if (hw->mac.type < ixgbe_mac_X540) { in ixgbe_setup_fc_generic()
352 * Enable auto-negotiation between the MAC & PHY; in ixgbe_setup_fc_generic()
353 * the MAC will advertise clause 37 flow control. in ixgbe_setup_fc_generic()
355 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); in ixgbe_setup_fc_generic()
356 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); in ixgbe_setup_fc_generic()
359 if (hw->fc.strict_ieee) in ixgbe_setup_fc_generic()
362 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); in ixgbe_setup_fc_generic()
371 if (hw->phy.media_type == ixgbe_media_type_backplane) { in ixgbe_setup_fc_generic()
373 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked); in ixgbe_setup_fc_generic()
376 } else if ((hw->phy.media_type == ixgbe_media_type_copper) && in ixgbe_setup_fc_generic()
377 (ixgbe_device_supports_autoneg_fc(hw))) { in ixgbe_setup_fc_generic()
378 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, in ixgbe_setup_fc_generic()
388 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
389 * @hw: pointer to hardware structure
393 * table, VLAN filter table, calls routine to set up link and flow control
396 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) in ixgbe_start_hw_generic() argument
405 hw->phy.media_type = hw->mac.ops.get_media_type(hw); in ixgbe_start_hw_generic()
410 hw->mac.ops.clear_vfta(hw); in ixgbe_start_hw_generic()
413 hw->mac.ops.clear_hw_cntrs(hw); in ixgbe_start_hw_generic()
416 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); in ixgbe_start_hw_generic()
418 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); in ixgbe_start_hw_generic()
419 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_generic()
421 /* Setup flow control */ in ixgbe_start_hw_generic()
422 ret_val = ixgbe_setup_fc(hw); in ixgbe_start_hw_generic()
424 DEBUGOUT1("Flow control setup failed, returning %d\n", ret_val); in ixgbe_start_hw_generic()
429 switch (hw->mac.type) { in ixgbe_start_hw_generic()
433 hw->mac.ops.get_device_caps(hw, &device_caps); in ixgbe_start_hw_generic()
435 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
437 hw->need_crosstalk_fix = true; in ixgbe_start_hw_generic()
440 hw->need_crosstalk_fix = false; in ixgbe_start_hw_generic()
445 hw->adapter_stopped = false; in ixgbe_start_hw_generic()
451 * ixgbe_start_hw_gen2 - Init sequence for common device family
452 * @hw: pointer to hw structure
460 void ixgbe_start_hw_gen2(struct ixgbe_hw *hw) in ixgbe_start_hw_gen2() argument
466 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
467 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); in ixgbe_start_hw_gen2()
468 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); in ixgbe_start_hw_gen2()
470 IXGBE_WRITE_FLUSH(hw); in ixgbe_start_hw_gen2()
473 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_start_hw_gen2()
474 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); in ixgbe_start_hw_gen2()
476 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); in ixgbe_start_hw_gen2()
479 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_start_hw_gen2()
480 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_start_hw_gen2()
483 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_start_hw_gen2()
488 * ixgbe_init_hw_generic - Generic hardware initialization
489 * @hw: pointer to hardware structure
494 * up link and flow control settings, and leaves transmit and receive units
497 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) in ixgbe_init_hw_generic() argument
504 status = hw->mac.ops.reset_hw(hw); in ixgbe_init_hw_generic()
507 /* Start the HW */ in ixgbe_init_hw_generic()
508 status = hw->mac.ops.start_hw(hw); in ixgbe_init_hw_generic()
512 if (hw->mac.ops.init_led_link_act) in ixgbe_init_hw_generic()
513 hw->mac.ops.init_led_link_act(hw); in ixgbe_init_hw_generic()
516 DEBUGOUT1("Failed to initialize HW, STATUS = %d\n", status); in ixgbe_init_hw_generic()
522 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
523 * @hw: pointer to hardware structure
528 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) in ixgbe_clear_hw_cntrs_generic() argument
534 IXGBE_READ_REG(hw, IXGBE_CRCERRS); in ixgbe_clear_hw_cntrs_generic()
535 IXGBE_READ_REG(hw, IXGBE_ILLERRC); in ixgbe_clear_hw_cntrs_generic()
536 IXGBE_READ_REG(hw, IXGBE_ERRBC); in ixgbe_clear_hw_cntrs_generic()
537 IXGBE_READ_REG(hw, IXGBE_MSPDC); in ixgbe_clear_hw_cntrs_generic()
539 IXGBE_READ_REG(hw, IXGBE_MPC(i)); in ixgbe_clear_hw_cntrs_generic()
541 IXGBE_READ_REG(hw, IXGBE_MLFC); in ixgbe_clear_hw_cntrs_generic()
542 IXGBE_READ_REG(hw, IXGBE_MRFC); in ixgbe_clear_hw_cntrs_generic()
543 IXGBE_READ_REG(hw, IXGBE_RLEC); in ixgbe_clear_hw_cntrs_generic()
544 IXGBE_READ_REG(hw, IXGBE_LXONTXC); in ixgbe_clear_hw_cntrs_generic()
545 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); in ixgbe_clear_hw_cntrs_generic()
546 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
547 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); in ixgbe_clear_hw_cntrs_generic()
548 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); in ixgbe_clear_hw_cntrs_generic()
550 IXGBE_READ_REG(hw, IXGBE_LXONRXC); in ixgbe_clear_hw_cntrs_generic()
551 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); in ixgbe_clear_hw_cntrs_generic()
555 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); in ixgbe_clear_hw_cntrs_generic()
556 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); in ixgbe_clear_hw_cntrs_generic()
557 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
558 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
559 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); in ixgbe_clear_hw_cntrs_generic()
561 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); in ixgbe_clear_hw_cntrs_generic()
562 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); in ixgbe_clear_hw_cntrs_generic()
565 if (hw->mac.type >= ixgbe_mac_82599EB) in ixgbe_clear_hw_cntrs_generic()
567 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); in ixgbe_clear_hw_cntrs_generic()
568 IXGBE_READ_REG(hw, IXGBE_PRC64); in ixgbe_clear_hw_cntrs_generic()
569 IXGBE_READ_REG(hw, IXGBE_PRC127); in ixgbe_clear_hw_cntrs_generic()
570 IXGBE_READ_REG(hw, IXGBE_PRC255); in ixgbe_clear_hw_cntrs_generic()
571 IXGBE_READ_REG(hw, IXGBE_PRC511); in ixgbe_clear_hw_cntrs_generic()
572 IXGBE_READ_REG(hw, IXGBE_PRC1023); in ixgbe_clear_hw_cntrs_generic()
573 IXGBE_READ_REG(hw, IXGBE_PRC1522); in ixgbe_clear_hw_cntrs_generic()
574 IXGBE_READ_REG(hw, IXGBE_GPRC); in ixgbe_clear_hw_cntrs_generic()
575 IXGBE_READ_REG(hw, IXGBE_BPRC); in ixgbe_clear_hw_cntrs_generic()
576 IXGBE_READ_REG(hw, IXGBE_MPRC); in ixgbe_clear_hw_cntrs_generic()
577 IXGBE_READ_REG(hw, IXGBE_GPTC); in ixgbe_clear_hw_cntrs_generic()
578 IXGBE_READ_REG(hw, IXGBE_GORCL); in ixgbe_clear_hw_cntrs_generic()
579 IXGBE_READ_REG(hw, IXGBE_GORCH); in ixgbe_clear_hw_cntrs_generic()
580 IXGBE_READ_REG(hw, IXGBE_GOTCL); in ixgbe_clear_hw_cntrs_generic()
581 IXGBE_READ_REG(hw, IXGBE_GOTCH); in ixgbe_clear_hw_cntrs_generic()
582 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_clear_hw_cntrs_generic()
584 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); in ixgbe_clear_hw_cntrs_generic()
585 IXGBE_READ_REG(hw, IXGBE_RUC); in ixgbe_clear_hw_cntrs_generic()
586 IXGBE_READ_REG(hw, IXGBE_RFC); in ixgbe_clear_hw_cntrs_generic()
587 IXGBE_READ_REG(hw, IXGBE_ROC); in ixgbe_clear_hw_cntrs_generic()
588 IXGBE_READ_REG(hw, IXGBE_RJC); in ixgbe_clear_hw_cntrs_generic()
589 IXGBE_READ_REG(hw, IXGBE_MNGPRC); in ixgbe_clear_hw_cntrs_generic()
590 IXGBE_READ_REG(hw, IXGBE_MNGPDC); in ixgbe_clear_hw_cntrs_generic()
591 IXGBE_READ_REG(hw, IXGBE_MNGPTC); in ixgbe_clear_hw_cntrs_generic()
592 IXGBE_READ_REG(hw, IXGBE_TORL); in ixgbe_clear_hw_cntrs_generic()
593 IXGBE_READ_REG(hw, IXGBE_TORH); in ixgbe_clear_hw_cntrs_generic()
594 IXGBE_READ_REG(hw, IXGBE_TPR); in ixgbe_clear_hw_cntrs_generic()
595 IXGBE_READ_REG(hw, IXGBE_TPT); in ixgbe_clear_hw_cntrs_generic()
596 IXGBE_READ_REG(hw, IXGBE_PTC64); in ixgbe_clear_hw_cntrs_generic()
597 IXGBE_READ_REG(hw, IXGBE_PTC127); in ixgbe_clear_hw_cntrs_generic()
598 IXGBE_READ_REG(hw, IXGBE_PTC255); in ixgbe_clear_hw_cntrs_generic()
599 IXGBE_READ_REG(hw, IXGBE_PTC511); in ixgbe_clear_hw_cntrs_generic()
600 IXGBE_READ_REG(hw, IXGBE_PTC1023); in ixgbe_clear_hw_cntrs_generic()
601 IXGBE_READ_REG(hw, IXGBE_PTC1522); in ixgbe_clear_hw_cntrs_generic()
602 IXGBE_READ_REG(hw, IXGBE_MPTC); in ixgbe_clear_hw_cntrs_generic()
603 IXGBE_READ_REG(hw, IXGBE_BPTC); in ixgbe_clear_hw_cntrs_generic()
605 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); in ixgbe_clear_hw_cntrs_generic()
606 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); in ixgbe_clear_hw_cntrs_generic()
607 if (hw->mac.type >= ixgbe_mac_82599EB) { in ixgbe_clear_hw_cntrs_generic()
608 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); in ixgbe_clear_hw_cntrs_generic()
609 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); in ixgbe_clear_hw_cntrs_generic()
610 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); in ixgbe_clear_hw_cntrs_generic()
611 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); in ixgbe_clear_hw_cntrs_generic()
612 IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); in ixgbe_clear_hw_cntrs_generic()
614 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); in ixgbe_clear_hw_cntrs_generic()
615 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); in ixgbe_clear_hw_cntrs_generic()
619 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) { in ixgbe_clear_hw_cntrs_generic()
620 if (hw->phy.id == 0) in ixgbe_clear_hw_cntrs_generic()
621 ixgbe_identify_phy(hw); in ixgbe_clear_hw_cntrs_generic()
622 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, in ixgbe_clear_hw_cntrs_generic()
624 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, in ixgbe_clear_hw_cntrs_generic()
626 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, in ixgbe_clear_hw_cntrs_generic()
628 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, in ixgbe_clear_hw_cntrs_generic()
636 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
637 * @hw: pointer to hardware structure
643 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, in ixgbe_read_pba_string_generic() argument
659 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_string_generic()
665 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); in ixgbe_read_pba_string_generic()
692 pba_num[6] = '-'; in ixgbe_read_pba_string_generic()
700 /* switch all the data but the '-' to hex char */ in ixgbe_read_pba_string_generic()
705 pba_num[offset] += 'A' - 0xA; in ixgbe_read_pba_string_generic()
711 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); in ixgbe_read_pba_string_generic()
717 if (length == 0xFFFF || length == 0 || length > hw->eeprom.word_size) { in ixgbe_read_pba_string_generic()
723 if (pba_num_size < (((u32)length * 2) - 1)) { in ixgbe_read_pba_string_generic()
730 length--; in ixgbe_read_pba_string_generic()
733 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); in ixgbe_read_pba_string_generic()
747 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
748 * @hw: pointer to hardware structure
753 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) in ixgbe_read_pba_num_generic() argument
760 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); in ixgbe_read_pba_num_generic()
770 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); in ixgbe_read_pba_num_generic()
782 * @hw: pointer to the HW structure
792 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, in ixgbe_read_pba_raw() argument
803 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, in ixgbe_read_pba_raw()
804 &pba->word[0]); in ixgbe_read_pba_raw()
809 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; in ixgbe_read_pba_raw()
810 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; in ixgbe_read_pba_raw()
816 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { in ixgbe_read_pba_raw()
817 if (pba->pba_block == NULL) in ixgbe_read_pba_raw()
820 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, in ixgbe_read_pba_raw()
830 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], in ixgbe_read_pba_raw()
832 pba->pba_block); in ixgbe_read_pba_raw()
836 if (eeprom_buf_size > (u32)(pba->word[1] + in ixgbe_read_pba_raw()
838 memcpy(pba->pba_block, in ixgbe_read_pba_raw()
839 &eeprom_buf[pba->word[1]], in ixgbe_read_pba_raw()
852 * @hw: pointer to the HW structure
861 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, in ixgbe_write_pba_raw() argument
870 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, in ixgbe_write_pba_raw()
871 &pba->word[0]); in ixgbe_write_pba_raw()
876 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; in ixgbe_write_pba_raw()
877 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; in ixgbe_write_pba_raw()
883 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { in ixgbe_write_pba_raw()
884 if (pba->pba_block == NULL) in ixgbe_write_pba_raw()
888 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], in ixgbe_write_pba_raw()
889 pba->pba_block[0], in ixgbe_write_pba_raw()
890 pba->pba_block); in ixgbe_write_pba_raw()
894 if (eeprom_buf_size > (u32)(pba->word[1] + in ixgbe_write_pba_raw()
895 pba->pba_block[0])) { in ixgbe_write_pba_raw()
896 memcpy(&eeprom_buf[pba->word[1]], in ixgbe_write_pba_raw()
897 pba->pba_block, in ixgbe_write_pba_raw()
898 pba->pba_block[0] * sizeof(u16)); in ixgbe_write_pba_raw()
910 * @hw: pointer to the HW structure
920 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, in ixgbe_get_pba_block_size() argument
930 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, in ixgbe_get_pba_block_size()
945 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, in ixgbe_get_pba_block_size()
970 * ixgbe_get_mac_addr_generic - Generic get MAC address
971 * @hw: pointer to hardware structure
978 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) in ixgbe_get_mac_addr_generic() argument
986 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); in ixgbe_get_mac_addr_generic()
987 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); in ixgbe_get_mac_addr_generic()
999 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
1000 * @hw: pointer to hardware structure
1005 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) in ixgbe_set_pci_config_data_generic() argument
1007 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_set_pci_config_data_generic()
1009 if (hw->bus.type == ixgbe_bus_type_unknown) in ixgbe_set_pci_config_data_generic()
1010 hw->bus.type = ixgbe_bus_type_pci_express; in ixgbe_set_pci_config_data_generic()
1014 hw->bus.width = ixgbe_bus_width_pcie_x1; in ixgbe_set_pci_config_data_generic()
1017 hw->bus.width = ixgbe_bus_width_pcie_x2; in ixgbe_set_pci_config_data_generic()
1020 hw->bus.width = ixgbe_bus_width_pcie_x4; in ixgbe_set_pci_config_data_generic()
1023 hw->bus.width = ixgbe_bus_width_pcie_x8; in ixgbe_set_pci_config_data_generic()
1026 hw->bus.width = ixgbe_bus_width_unknown; in ixgbe_set_pci_config_data_generic()
1032 hw->bus.speed = ixgbe_bus_speed_2500; in ixgbe_set_pci_config_data_generic()
1035 hw->bus.speed = ixgbe_bus_speed_5000; in ixgbe_set_pci_config_data_generic()
1038 hw->bus.speed = ixgbe_bus_speed_8000; in ixgbe_set_pci_config_data_generic()
1041 hw->bus.speed = ixgbe_bus_speed_unknown; in ixgbe_set_pci_config_data_generic()
1045 mac->ops.set_lan_id(hw); in ixgbe_set_pci_config_data_generic()
1049 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1050 * @hw: pointer to hardware structure
1055 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) in ixgbe_get_bus_info_generic() argument
1062 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); in ixgbe_get_bus_info_generic()
1064 ixgbe_set_pci_config_data_generic(hw, link_status); in ixgbe_get_bus_info_generic()
1070 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1071 * @hw: pointer to the HW structure
1073 * Determines the LAN function id by reading memory-mapped registers and swaps
1077 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) in ixgbe_set_lan_id_multi_port_pcie() argument
1079 struct ixgbe_bus_info *bus = &hw->bus; in ixgbe_set_lan_id_multi_port_pcie()
1085 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); in ixgbe_set_lan_id_multi_port_pcie()
1086 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; in ixgbe_set_lan_id_multi_port_pcie()
1087 bus->lan_id = (u8)bus->func; in ixgbe_set_lan_id_multi_port_pcie()
1090 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); in ixgbe_set_lan_id_multi_port_pcie()
1092 bus->func ^= 0x1; in ixgbe_set_lan_id_multi_port_pcie()
1095 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SFP) { in ixgbe_set_lan_id_multi_port_pcie()
1096 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_4, &ee_ctrl_4); in ixgbe_set_lan_id_multi_port_pcie()
1097 bus->instance_id = (ee_ctrl_4 & IXGBE_EE_CTRL_4_INST_ID) >> in ixgbe_set_lan_id_multi_port_pcie()
1103 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1104 * @hw: pointer to hardware structure
1111 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) in ixgbe_stop_adapter_generic() argument
1122 hw->adapter_stopped = true; in ixgbe_stop_adapter_generic()
1125 ixgbe_disable_rx(hw); in ixgbe_stop_adapter_generic()
1128 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); in ixgbe_stop_adapter_generic()
1131 IXGBE_READ_REG(hw, IXGBE_EICR); in ixgbe_stop_adapter_generic()
1134 for (i = 0; i < hw->mac.max_tx_queues; i++) in ixgbe_stop_adapter_generic()
1135 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); in ixgbe_stop_adapter_generic()
1138 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_stop_adapter_generic()
1139 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); in ixgbe_stop_adapter_generic()
1142 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); in ixgbe_stop_adapter_generic()
1146 IXGBE_WRITE_FLUSH(hw); in ixgbe_stop_adapter_generic()
1150 * Prevent the PCI-E bus from hanging by disabling PCI-E primary in ixgbe_stop_adapter_generic()
1153 return ixgbe_disable_pcie_primary(hw); in ixgbe_stop_adapter_generic()
1157 * ixgbe_init_led_link_act_generic - Store the LED index link/activity.
1158 * @hw: pointer to hardware structure
1163 s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw) in ixgbe_init_led_link_act_generic() argument
1165 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_led_link_act_generic()
1169 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_init_led_link_act_generic()
1177 mac->led_link_act = i; in ixgbe_init_led_link_act_generic()
1186 switch (hw->mac.type) { in ixgbe_init_led_link_act_generic()
1189 mac->led_link_act = 1; in ixgbe_init_led_link_act_generic()
1192 mac->led_link_act = 2; in ixgbe_init_led_link_act_generic()
1198 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1199 * @hw: pointer to hardware structure
1202 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_on_generic() argument
1204 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_on_generic()
1214 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_on_generic()
1215 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_on_generic()
1221 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1222 * @hw: pointer to hardware structure
1225 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_led_off_generic() argument
1227 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_led_off_generic()
1237 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_led_off_generic()
1238 IXGBE_WRITE_FLUSH(hw); in ixgbe_led_off_generic()
1244 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1245 * @hw: pointer to hardware structure
1250 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) in ixgbe_init_eeprom_params_generic() argument
1252 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_eeprom_params_generic()
1258 if (eeprom->type == ixgbe_eeprom_uninitialized) { in ixgbe_init_eeprom_params_generic()
1259 eeprom->type = ixgbe_eeprom_none; in ixgbe_init_eeprom_params_generic()
1262 eeprom->semaphore_delay = 10; in ixgbe_init_eeprom_params_generic()
1264 eeprom->word_page_size = 0; in ixgbe_init_eeprom_params_generic()
1270 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_init_eeprom_params_generic()
1272 eeprom->type = ixgbe_eeprom_spi; in ixgbe_init_eeprom_params_generic()
1280 eeprom->word_size = 1 << (eeprom_size + in ixgbe_init_eeprom_params_generic()
1285 eeprom->address_bits = 16; in ixgbe_init_eeprom_params_generic()
1287 eeprom->address_bits = 8; in ixgbe_init_eeprom_params_generic()
1289 "%d\n", eeprom->type, eeprom->word_size, in ixgbe_init_eeprom_params_generic()
1290 eeprom->address_bits); in ixgbe_init_eeprom_params_generic()
1297 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1298 * @hw: pointer to hardware structure
1303 * Reads 16 bit word(s) from EEPROM through bit-bang method
1305 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang_generic() argument
1313 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_buffer_bit_bang_generic()
1320 if (offset + words > hw->eeprom.word_size) { in ixgbe_write_eeprom_buffer_bit_bang_generic()
1329 if ((hw->eeprom.word_page_size == 0) && in ixgbe_write_eeprom_buffer_bit_bang_generic()
1331 ixgbe_detect_eeprom_page_size_generic(hw, offset); in ixgbe_write_eeprom_buffer_bit_bang_generic()
1339 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? in ixgbe_write_eeprom_buffer_bit_bang_generic()
1340 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); in ixgbe_write_eeprom_buffer_bit_bang_generic()
1341 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_write_eeprom_buffer_bit_bang_generic()
1353 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1354 * @hw: pointer to hardware structure
1362 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eeprom_buffer_bit_bang() argument
1374 status = ixgbe_acquire_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1377 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { in ixgbe_write_eeprom_buffer_bit_bang()
1378 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1385 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1388 ixgbe_shift_out_eeprom_bits(hw, in ixgbe_write_eeprom_buffer_bit_bang()
1392 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1398 if ((hw->eeprom.address_bits == 8) && in ixgbe_write_eeprom_buffer_bit_bang()
1402 /* Send the Write command (8-bit opcode + addr) */ in ixgbe_write_eeprom_buffer_bit_bang()
1403 ixgbe_shift_out_eeprom_bits(hw, write_opcode, in ixgbe_write_eeprom_buffer_bit_bang()
1405 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_write_eeprom_buffer_bit_bang()
1406 hw->eeprom.address_bits); in ixgbe_write_eeprom_buffer_bit_bang()
1408 page_size = hw->eeprom.word_page_size; in ixgbe_write_eeprom_buffer_bit_bang()
1414 ixgbe_shift_out_eeprom_bits(hw, word, 16); in ixgbe_write_eeprom_buffer_bit_bang()
1420 if (((offset + i) & (page_size - 1)) == in ixgbe_write_eeprom_buffer_bit_bang()
1421 (page_size - 1)) in ixgbe_write_eeprom_buffer_bit_bang()
1425 ixgbe_standby_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1428 /* Done with writing - release the EEPROM */ in ixgbe_write_eeprom_buffer_bit_bang()
1429 ixgbe_release_eeprom(hw); in ixgbe_write_eeprom_buffer_bit_bang()
1436 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1437 * @hw: pointer to hardware structure
1444 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eeprom_generic() argument
1450 hw->eeprom.ops.init_params(hw); in ixgbe_write_eeprom_generic()
1452 if (offset >= hw->eeprom.word_size) { in ixgbe_write_eeprom_generic()
1457 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); in ixgbe_write_eeprom_generic()
1464 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1465 * @hw: pointer to hardware structure
1470 * Reads 16 bit word(s) from EEPROM through bit-bang method
1472 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang_generic() argument
1480 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1487 if (offset + words > hw->eeprom.word_size) { in ixgbe_read_eeprom_buffer_bit_bang_generic()
1498 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? in ixgbe_read_eeprom_buffer_bit_bang_generic()
1499 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); in ixgbe_read_eeprom_buffer_bit_bang_generic()
1501 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, in ixgbe_read_eeprom_buffer_bit_bang_generic()
1513 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1514 * @hw: pointer to hardware structure
1519 * Reads 16 bit word(s) from EEPROM through bit-bang method
1521 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_bit_bang() argument
1532 status = ixgbe_acquire_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1535 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { in ixgbe_read_eeprom_buffer_bit_bang()
1536 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1543 ixgbe_standby_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1548 if ((hw->eeprom.address_bits == 8) && in ixgbe_read_eeprom_buffer_bit_bang()
1553 ixgbe_shift_out_eeprom_bits(hw, read_opcode, in ixgbe_read_eeprom_buffer_bit_bang()
1555 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), in ixgbe_read_eeprom_buffer_bit_bang()
1556 hw->eeprom.address_bits); in ixgbe_read_eeprom_buffer_bit_bang()
1559 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); in ixgbe_read_eeprom_buffer_bit_bang()
1564 ixgbe_release_eeprom(hw); in ixgbe_read_eeprom_buffer_bit_bang()
1571 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1572 * @hw: pointer to hardware structure
1576 * Reads 16 bit value from EEPROM through bit-bang method
1578 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_bit_bang_generic() argument
1585 hw->eeprom.ops.init_params(hw); in ixgbe_read_eeprom_bit_bang_generic()
1587 if (offset >= hw->eeprom.word_size) { in ixgbe_read_eeprom_bit_bang_generic()
1592 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_read_eeprom_bit_bang_generic()
1599 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1600 * @hw: pointer to hardware structure
1607 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eerd_buffer_generic() argument
1616 hw->eeprom.ops.init_params(hw); in ixgbe_read_eerd_buffer_generic()
1624 if (offset >= hw->eeprom.word_size) { in ixgbe_read_eerd_buffer_generic()
1634 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); in ixgbe_read_eerd_buffer_generic()
1635 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); in ixgbe_read_eerd_buffer_generic()
1638 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> in ixgbe_read_eerd_buffer_generic()
1650 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1651 * @hw: pointer to hardware structure
1658 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, in ixgbe_detect_eeprom_page_size_generic() argument
1670 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; in ixgbe_detect_eeprom_page_size_generic()
1671 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, in ixgbe_detect_eeprom_page_size_generic()
1673 hw->eeprom.word_page_size = 0; in ixgbe_detect_eeprom_page_size_generic()
1677 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); in ixgbe_detect_eeprom_page_size_generic()
1685 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; in ixgbe_detect_eeprom_page_size_generic()
1688 hw->eeprom.word_page_size); in ixgbe_detect_eeprom_page_size_generic()
1694 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1695 * @hw: pointer to hardware structure
1701 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) in ixgbe_read_eerd_generic() argument
1703 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); in ixgbe_read_eerd_generic()
1707 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1708 * @hw: pointer to hardware structure
1715 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, in ixgbe_write_eewr_buffer_generic() argument
1724 hw->eeprom.ops.init_params(hw); in ixgbe_write_eewr_buffer_generic()
1732 if (offset >= hw->eeprom.word_size) { in ixgbe_write_eewr_buffer_generic()
1743 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1749 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); in ixgbe_write_eewr_buffer_generic()
1751 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); in ixgbe_write_eewr_buffer_generic()
1763 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1764 * @hw: pointer to hardware structure
1770 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) in ixgbe_write_eewr_generic() argument
1772 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); in ixgbe_write_eewr_generic()
1776 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1777 * @hw: pointer to hardware structure
1783 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) in ixgbe_poll_eerd_eewr_done() argument
1793 reg = IXGBE_READ_REG(hw, IXGBE_EERD); in ixgbe_poll_eerd_eewr_done()
1795 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); in ixgbe_poll_eerd_eewr_done()
1812 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1813 * @hw: pointer to hardware structure
1815 * Prepares EEPROM for access using bit-bang method. This function should
1818 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) in ixgbe_acquire_eeprom() argument
1826 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) in ixgbe_acquire_eeprom()
1831 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_acquire_eeprom()
1835 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_acquire_eeprom()
1838 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_acquire_eeprom()
1847 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_acquire_eeprom()
1850 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_acquire_eeprom()
1858 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_acquire_eeprom()
1859 IXGBE_WRITE_FLUSH(hw); in ixgbe_acquire_eeprom()
1867 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1868 * @hw: pointer to hardware structure
1870 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1872 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_get_eeprom_semaphore() argument
1888 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); in ixgbe_get_eeprom_semaphore()
1897 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " in ixgbe_get_eeprom_semaphore()
1905 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1913 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); in ixgbe_get_eeprom_semaphore()
1921 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); in ixgbe_get_eeprom_semaphore()
1925 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); in ixgbe_get_eeprom_semaphore()
1931 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); in ixgbe_get_eeprom_semaphore()
1945 ixgbe_release_eeprom_semaphore(hw); in ixgbe_get_eeprom_semaphore()
1958 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1959 * @hw: pointer to hardware structure
1963 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) in ixgbe_release_eeprom_semaphore() argument
1969 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); in ixgbe_release_eeprom_semaphore()
1973 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); in ixgbe_release_eeprom_semaphore()
1974 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom_semaphore()
1978 * ixgbe_ready_eeprom - Polls for EEPROM ready
1979 * @hw: pointer to hardware structure
1981 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) in ixgbe_ready_eeprom() argument
1996 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, in ixgbe_ready_eeprom()
1998 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); in ixgbe_ready_eeprom()
2003 ixgbe_standby_eeprom(hw); in ixgbe_ready_eeprom()
2007 * On some parts, SPI write time could vary from 0-20mSec on 3.3V in ixgbe_ready_eeprom()
2008 * devices (and only 0-5mSec on 5V devices) in ixgbe_ready_eeprom()
2019 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
2020 * @hw: pointer to hardware structure
2022 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) in ixgbe_standby_eeprom() argument
2028 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_standby_eeprom()
2032 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_standby_eeprom()
2033 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
2036 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_standby_eeprom()
2037 IXGBE_WRITE_FLUSH(hw); in ixgbe_standby_eeprom()
2042 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
2043 * @hw: pointer to hardware structure
2047 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, in ixgbe_shift_out_eeprom_bits() argument
2056 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_shift_out_eeprom_bits()
2062 mask = 0x01 << (count - 1); in ixgbe_shift_out_eeprom_bits()
2077 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_shift_out_eeprom_bits()
2078 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
2082 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
2083 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_out_eeprom_bits()
2094 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_shift_out_eeprom_bits()
2095 IXGBE_WRITE_FLUSH(hw); in ixgbe_shift_out_eeprom_bits()
2099 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
2100 * @hw: pointer to hardware structure
2103 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) in ixgbe_shift_in_eeprom_bits() argument
2118 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_shift_in_eeprom_bits()
2124 ixgbe_raise_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
2126 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_shift_in_eeprom_bits()
2132 ixgbe_lower_eeprom_clk(hw, &eec); in ixgbe_shift_in_eeprom_bits()
2139 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2140 * @hw: pointer to hardware structure
2143 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_raise_eeprom_clk() argument
2152 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); in ixgbe_raise_eeprom_clk()
2153 IXGBE_WRITE_FLUSH(hw); in ixgbe_raise_eeprom_clk()
2158 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2159 * @hw: pointer to hardware structure
2162 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) in ixgbe_lower_eeprom_clk() argument
2171 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), *eec); in ixgbe_lower_eeprom_clk()
2172 IXGBE_WRITE_FLUSH(hw); in ixgbe_lower_eeprom_clk()
2177 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2178 * @hw: pointer to hardware structure
2180 static void ixgbe_release_eeprom(struct ixgbe_hw *hw) in ixgbe_release_eeprom() argument
2186 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); in ixgbe_release_eeprom()
2191 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_release_eeprom()
2192 IXGBE_WRITE_FLUSH(hw); in ixgbe_release_eeprom()
2198 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), eec); in ixgbe_release_eeprom()
2200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); in ixgbe_release_eeprom()
2203 msec_delay(hw->eeprom.semaphore_delay); in ixgbe_release_eeprom()
2207 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2208 * @hw: pointer to hardware structure
2210 * Returns a negative error code on error, or the 16-bit checksum
2212 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_calc_eeprom_checksum_generic() argument
2223 /* Include 0x0-0x3F in the checksum */ in ixgbe_calc_eeprom_checksum_generic()
2225 if (hw->eeprom.ops.read(hw, i, &word)) { in ixgbe_calc_eeprom_checksum_generic()
2234 if (hw->eeprom.ops.read(hw, i, &pointer)) { in ixgbe_calc_eeprom_checksum_generic()
2243 if (hw->eeprom.ops.read(hw, pointer, &length)) { in ixgbe_calc_eeprom_checksum_generic()
2252 if (hw->eeprom.ops.read(hw, j, &word)) { in ixgbe_calc_eeprom_checksum_generic()
2260 checksum = (u16)IXGBE_EEPROM_SUM - checksum; in ixgbe_calc_eeprom_checksum_generic()
2266 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2267 * @hw: pointer to hardware structure
2273 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, in ixgbe_validate_eeprom_checksum_generic() argument
2286 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_validate_eeprom_checksum_generic()
2292 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_validate_eeprom_checksum_generic()
2298 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); in ixgbe_validate_eeprom_checksum_generic()
2318 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2319 * @hw: pointer to hardware structure
2321 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) in ixgbe_update_eeprom_checksum_generic() argument
2332 status = hw->eeprom.ops.read(hw, 0, &checksum); in ixgbe_update_eeprom_checksum_generic()
2338 status = hw->eeprom.ops.calc_checksum(hw); in ixgbe_update_eeprom_checksum_generic()
2344 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum); in ixgbe_update_eeprom_checksum_generic()
2350 * ixgbe_validate_mac_addr - Validate MAC address
2376 * ixgbe_set_rar_generic - Set Rx address register
2377 * @hw: pointer to hardware structure
2385 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, in ixgbe_set_rar_generic() argument
2389 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_rar_generic()
2401 hw->mac.ops.set_vmdq(hw, index, vmdq); in ixgbe_set_rar_generic()
2404 * HW expects these in little endian so we reverse the byte in ixgbe_set_rar_generic()
2416 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_set_rar_generic()
2423 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); in ixgbe_set_rar_generic()
2424 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_set_rar_generic()
2430 * ixgbe_clear_rar_generic - Remove Rx address register
2431 * @hw: pointer to hardware structure
2436 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_clear_rar_generic() argument
2439 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_rar_generic()
2455 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); in ixgbe_clear_rar_generic()
2458 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); in ixgbe_clear_rar_generic()
2459 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); in ixgbe_clear_rar_generic()
2462 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_clear_rar_generic()
2468 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2469 * @hw: pointer to hardware structure
2475 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) in ixgbe_init_rx_addrs_generic() argument
2478 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_init_rx_addrs_generic()
2487 if (ixgbe_validate_mac_addr(hw->mac.addr) == in ixgbe_init_rx_addrs_generic()
2490 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); in ixgbe_init_rx_addrs_generic()
2493 hw->mac.addr[0], hw->mac.addr[1], in ixgbe_init_rx_addrs_generic()
2494 hw->mac.addr[2]); in ixgbe_init_rx_addrs_generic()
2495 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], in ixgbe_init_rx_addrs_generic()
2496 hw->mac.addr[4], hw->mac.addr[5]); in ixgbe_init_rx_addrs_generic()
2501 hw->mac.addr[0], hw->mac.addr[1], in ixgbe_init_rx_addrs_generic()
2502 hw->mac.addr[2]); in ixgbe_init_rx_addrs_generic()
2503 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], in ixgbe_init_rx_addrs_generic()
2504 hw->mac.addr[4], hw->mac.addr[5]); in ixgbe_init_rx_addrs_generic()
2506 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); in ixgbe_init_rx_addrs_generic()
2510 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); in ixgbe_init_rx_addrs_generic()
2512 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_init_rx_addrs_generic()
2514 hw->addr_ctrl.rar_used_count = 1; in ixgbe_init_rx_addrs_generic()
2517 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); in ixgbe_init_rx_addrs_generic()
2519 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); in ixgbe_init_rx_addrs_generic()
2520 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); in ixgbe_init_rx_addrs_generic()
2524 hw->addr_ctrl.mta_in_use = 0; in ixgbe_init_rx_addrs_generic()
2525 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_init_rx_addrs_generic()
2528 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_init_rx_addrs_generic()
2529 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); in ixgbe_init_rx_addrs_generic()
2531 ixgbe_init_uta_tables(hw); in ixgbe_init_rx_addrs_generic()
2537 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2538 * @hw: pointer to hardware structure
2544 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) in ixgbe_add_uc_addr() argument
2546 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_add_uc_addr()
2558 if (hw->addr_ctrl.rar_used_count < rar_entries) { in ixgbe_add_uc_addr()
2559 rar = hw->addr_ctrl.rar_used_count; in ixgbe_add_uc_addr()
2560 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); in ixgbe_add_uc_addr()
2562 hw->addr_ctrl.rar_used_count++; in ixgbe_add_uc_addr()
2564 hw->addr_ctrl.overflow_promisc++; in ixgbe_add_uc_addr()
2571 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2572 * @hw: pointer to hardware structure
2584 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, in ixgbe_update_uc_addr_list_generic() argument
2589 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; in ixgbe_update_uc_addr_list_generic()
2600 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; in ixgbe_update_uc_addr_list_generic()
2601 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; in ixgbe_update_uc_addr_list_generic()
2602 hw->addr_ctrl.overflow_promisc = 0; in ixgbe_update_uc_addr_list_generic()
2605 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); in ixgbe_update_uc_addr_list_generic()
2607 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); in ixgbe_update_uc_addr_list_generic()
2608 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); in ixgbe_update_uc_addr_list_generic()
2614 addr = next(hw, &addr_list, &vmdq); in ixgbe_update_uc_addr_list_generic()
2615 ixgbe_add_uc_addr(hw, addr, vmdq); in ixgbe_update_uc_addr_list_generic()
2618 if (hw->addr_ctrl.overflow_promisc) { in ixgbe_update_uc_addr_list_generic()
2620 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { in ixgbe_update_uc_addr_list_generic()
2622 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_update_uc_addr_list_generic()
2624 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); in ixgbe_update_uc_addr_list_generic()
2628 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { in ixgbe_update_uc_addr_list_generic()
2630 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_update_uc_addr_list_generic()
2632 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); in ixgbe_update_uc_addr_list_generic()
2641 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2642 * @hw: pointer to hardware structure
2646 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2647 * incoming rx multicast addresses, to determine the bit-vector to check in
2648 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2652 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_mta_vector() argument
2658 switch (hw->mac.mc_filter_type) { in ixgbe_mta_vector()
2677 /* vector can only be 12-bits or boundary will be exceeded */ in ixgbe_mta_vector()
2683 * ixgbe_set_mta - Set bit-vector in multicast table
2684 * @hw: pointer to hardware structure
2687 * Sets the bit-vector in the multicast table.
2689 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) in ixgbe_set_mta() argument
2697 hw->addr_ctrl.mta_in_use++; in ixgbe_set_mta()
2699 vector = ixgbe_mta_vector(hw, mc_addr); in ixgbe_set_mta()
2700 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); in ixgbe_set_mta()
2703 * The MTA is a register array of 128 32-bit registers. It is treated in ixgbe_set_mta()
2713 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); in ixgbe_set_mta()
2717 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2718 * @hw: pointer to hardware structure
2727 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, in ixgbe_update_mc_addr_list_generic() argument
2740 hw->addr_ctrl.num_mc_addrs = mc_addr_count; in ixgbe_update_mc_addr_list_generic()
2741 hw->addr_ctrl.mta_in_use = 0; in ixgbe_update_mc_addr_list_generic()
2746 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in ixgbe_update_mc_addr_list_generic()
2752 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); in ixgbe_update_mc_addr_list_generic()
2756 for (i = 0; i < hw->mac.mcft_size; i++) in ixgbe_update_mc_addr_list_generic()
2757 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, in ixgbe_update_mc_addr_list_generic()
2758 hw->mac.mta_shadow[i]); in ixgbe_update_mc_addr_list_generic()
2760 if (hw->addr_ctrl.mta_in_use > 0) in ixgbe_update_mc_addr_list_generic()
2761 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, in ixgbe_update_mc_addr_list_generic()
2762 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); in ixgbe_update_mc_addr_list_generic()
2769 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2770 * @hw: pointer to hardware structure
2774 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) in ixgbe_enable_mc_generic() argument
2776 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_enable_mc_generic()
2780 if (a->mta_in_use > 0) in ixgbe_enable_mc_generic()
2781 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | in ixgbe_enable_mc_generic()
2782 hw->mac.mc_filter_type); in ixgbe_enable_mc_generic()
2788 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2789 * @hw: pointer to hardware structure
2793 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) in ixgbe_disable_mc_generic() argument
2795 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; in ixgbe_disable_mc_generic()
2799 if (a->mta_in_use > 0) in ixgbe_disable_mc_generic()
2800 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); in ixgbe_disable_mc_generic()
2806 * ixgbe_fc_enable_generic - Enable flow control
2807 * @hw: pointer to hardware structure
2809 * Enable flow control according to the current settings.
2811 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) in ixgbe_fc_enable_generic() argument
2822 if (!hw->fc.pause_time) { in ixgbe_fc_enable_generic()
2829 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2830 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2831 if (!hw->fc.low_water[i] || in ixgbe_fc_enable_generic()
2832 hw->fc.low_water[i] >= hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2841 hw->mac.ops.fc_autoneg(hw); in ixgbe_fc_enable_generic()
2843 /* Disable any previous flow control settings */ in ixgbe_fc_enable_generic()
2844 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); in ixgbe_fc_enable_generic()
2847 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); in ixgbe_fc_enable_generic()
2852 * 0: Flow control is completely disabled in ixgbe_fc_enable_generic()
2853 * 1: Rx flow control is enabled (we can receive pause frames, in ixgbe_fc_enable_generic()
2855 * 2: Tx flow control is enabled (we can send pause frames but in ixgbe_fc_enable_generic()
2857 * 3: Both Rx and Tx flow control (symmetric) are enabled. in ixgbe_fc_enable_generic()
2860 switch (hw->fc.current_mode) { in ixgbe_fc_enable_generic()
2863 * Flow control is disabled by software override or autoneg. in ixgbe_fc_enable_generic()
2864 * The code below will actually disable it in the HW. in ixgbe_fc_enable_generic()
2869 * Rx Flow control is enabled and Tx Flow control is in ixgbe_fc_enable_generic()
2880 * Tx Flow control is enabled, and Rx Flow control is in ixgbe_fc_enable_generic()
2886 /* Flow control (both Rx and Tx) is enabled by SW override. */ in ixgbe_fc_enable_generic()
2892 "Flow control param set incorrectly\n"); in ixgbe_fc_enable_generic()
2898 /* Set 802.3x based flow control settings. */ in ixgbe_fc_enable_generic()
2900 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); in ixgbe_fc_enable_generic()
2901 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); in ixgbe_fc_enable_generic()
2906 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && in ixgbe_fc_enable_generic()
2907 hw->fc.high_water[i]) { in ixgbe_fc_enable_generic()
2908 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; in ixgbe_fc_enable_generic()
2909 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); in ixgbe_fc_enable_generic()
2910 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_fc_enable_generic()
2912 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); in ixgbe_fc_enable_generic()
2916 * to the Rx packet buffer size - 24KB. This allows in ixgbe_fc_enable_generic()
2920 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576; in ixgbe_fc_enable_generic()
2923 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); in ixgbe_fc_enable_generic()
2927 reg = hw->fc.pause_time * 0x00010001; in ixgbe_fc_enable_generic()
2929 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_fc_enable_generic()
2931 /* Configure flow control refresh threshold value */ in ixgbe_fc_enable_generic()
2932 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); in ixgbe_fc_enable_generic()
2939 * ixgbe_negotiate_fc - Negotiate flow control
2940 * @hw: pointer to hardware structure
2941 * @adv_reg: flow control advertised settings
2942 * @lp_reg: link partner's flow control settings
2951 s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, in ixgbe_negotiate_fc() argument
2956 "Local or link partner's advertised flow control " in ixgbe_negotiate_fc()
2966 * FULL flow control because we could not advertise RX in ixgbe_negotiate_fc()
2970 if (hw->fc.requested_mode == ixgbe_fc_full) { in ixgbe_negotiate_fc()
2971 hw->fc.current_mode = ixgbe_fc_full; in ixgbe_negotiate_fc()
2972 DEBUGOUT("Flow Control = FULL.\n"); in ixgbe_negotiate_fc()
2974 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2975 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); in ixgbe_negotiate_fc()
2979 hw->fc.current_mode = ixgbe_fc_tx_pause; in ixgbe_negotiate_fc()
2980 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2983 hw->fc.current_mode = ixgbe_fc_rx_pause; in ixgbe_negotiate_fc()
2984 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); in ixgbe_negotiate_fc()
2986 hw->fc.current_mode = ixgbe_fc_none; in ixgbe_negotiate_fc()
2987 DEBUGOUT("Flow Control = NONE.\n"); in ixgbe_negotiate_fc()
2993 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2994 * @hw: pointer to hardware structure
2996 * Enable flow control according on 1 gig fiber.
2998 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_fiber() argument
3005 * - link is up but AN did not complete, or if in ixgbe_fc_autoneg_fiber()
3006 * - link is up and AN completed but timed out in ixgbe_fc_autoneg_fiber()
3009 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); in ixgbe_fc_autoneg_fiber()
3012 DEBUGOUT("Auto-Negotiation did not complete or timed out\n"); in ixgbe_fc_autoneg_fiber()
3016 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); in ixgbe_fc_autoneg_fiber()
3017 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); in ixgbe_fc_autoneg_fiber()
3019 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, in ixgbe_fc_autoneg_fiber()
3030 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
3031 * @hw: pointer to hardware structure
3033 * Enable flow control according to IEEE clause 37.
3035 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_backplane() argument
3042 * - backplane autoneg was not completed, or if in ixgbe_fc_autoneg_backplane()
3043 * - we are 82599 and link partner is not AN enabled in ixgbe_fc_autoneg_backplane()
3045 links = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_fc_autoneg_backplane()
3047 DEBUGOUT("Auto-Negotiation did not complete\n"); in ixgbe_fc_autoneg_backplane()
3051 if (hw->mac.type == ixgbe_mac_82599EB) { in ixgbe_fc_autoneg_backplane()
3052 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); in ixgbe_fc_autoneg_backplane()
3060 * local flow control settings accordingly in ixgbe_fc_autoneg_backplane()
3062 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_fc_autoneg_backplane()
3063 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_fc_autoneg_backplane()
3065 ret_val = ixgbe_negotiate_fc(hw, autoc_reg, in ixgbe_fc_autoneg_backplane()
3074 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
3075 * @hw: pointer to hardware structure
3077 * Enable flow control according to IEEE clause 37.
3079 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) in ixgbe_fc_autoneg_copper() argument
3084 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, in ixgbe_fc_autoneg_copper()
3087 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, in ixgbe_fc_autoneg_copper()
3091 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, in ixgbe_fc_autoneg_copper()
3098 * ixgbe_fc_autoneg - Configure flow control
3099 * @hw: pointer to hardware structure
3101 * Compares our advertised flow control capabilities to those advertised by
3102 * our link partner, and determines the proper flow control mode to use.
3104 void ixgbe_fc_autoneg(struct ixgbe_hw *hw) in ixgbe_fc_autoneg() argument
3115 * - FC autoneg is disabled, or if in ixgbe_fc_autoneg()
3116 * - link is not up. in ixgbe_fc_autoneg()
3118 if (hw->fc.disable_fc_autoneg) { in ixgbe_fc_autoneg()
3121 "Flow control autoneg is disabled"); in ixgbe_fc_autoneg()
3125 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_fc_autoneg()
3131 switch (hw->phy.media_type) { in ixgbe_fc_autoneg()
3132 /* Autoneg flow control on fiber adapters */ in ixgbe_fc_autoneg()
3137 ret_val = ixgbe_fc_autoneg_fiber(hw); in ixgbe_fc_autoneg()
3140 /* Autoneg flow control on backplane adapters */ in ixgbe_fc_autoneg()
3142 ret_val = ixgbe_fc_autoneg_backplane(hw); in ixgbe_fc_autoneg()
3145 /* Autoneg flow control on copper adapters */ in ixgbe_fc_autoneg()
3147 if (ixgbe_device_supports_autoneg_fc(hw)) in ixgbe_fc_autoneg()
3148 ret_val = ixgbe_fc_autoneg_copper(hw); in ixgbe_fc_autoneg()
3157 hw->fc.fc_was_autonegged = true; in ixgbe_fc_autoneg()
3159 hw->fc.fc_was_autonegged = false; in ixgbe_fc_autoneg()
3160 hw->fc.current_mode = hw->fc.requested_mode; in ixgbe_fc_autoneg()
3165 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3166 * @hw: pointer to hardware structure
3168 * System-wide timeout range is encoded in PCIe Device Control2 register.
3174 static u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) in ixgbe_pcie_timeout_poll() argument
3179 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); in ixgbe_pcie_timeout_poll()
3212 * ixgbe_disable_pcie_primary - Disable PCI-express primary access
3213 * @hw: pointer to hardware structure
3215 * Disables PCI-Express primary access and verifies there are no pending
3220 s32 ixgbe_disable_pcie_primary(struct ixgbe_hw *hw) in ixgbe_disable_pcie_primary() argument
3229 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); in ixgbe_disable_pcie_primary()
3232 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) || in ixgbe_disable_pcie_primary()
3233 IXGBE_REMOVED(hw->hw_addr)) in ixgbe_disable_pcie_primary()
3239 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) in ixgbe_disable_pcie_primary()
3244 * Two consecutive resets are required via CTRL.RST per datasheet in ixgbe_disable_pcie_primary()
3251 DEBUGOUT("GIO Primary Disable bit didn't clear - requesting resets\n"); in ixgbe_disable_pcie_primary()
3252 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_disable_pcie_primary()
3254 if (hw->mac.type >= ixgbe_mac_X550) in ixgbe_disable_pcie_primary()
3261 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_disable_pcie_primary()
3264 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_disable_pcie_primary()
3265 if (IXGBE_REMOVED(hw->hw_addr)) in ixgbe_disable_pcie_primary()
3280 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3281 * @hw: pointer to hardware structure
3287 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_acquire_swfw_sync() argument
3302 if (ixgbe_get_eeprom_semaphore(hw)) in ixgbe_acquire_swfw_sync()
3305 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_acquire_swfw_sync()
3308 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_acquire_swfw_sync()
3309 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
3313 ixgbe_release_eeprom_semaphore(hw); in ixgbe_acquire_swfw_sync()
3320 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); in ixgbe_acquire_swfw_sync()
3327 * ixgbe_release_swfw_sync - Release SWFW semaphore
3328 * @hw: pointer to hardware structure
3334 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask) in ixgbe_release_swfw_sync() argument
3341 ixgbe_get_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
3343 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); in ixgbe_release_swfw_sync()
3345 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); in ixgbe_release_swfw_sync()
3347 ixgbe_release_eeprom_semaphore(hw); in ixgbe_release_swfw_sync()
3351 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3352 * @hw: pointer to hardware structure
3354 * Stops the receive data path and waits for the HW to internally empty
3357 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) in ixgbe_disable_sec_rx_path_generic() argument
3367 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_disable_sec_rx_path_generic()
3369 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_disable_sec_rx_path_generic()
3371 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); in ixgbe_disable_sec_rx_path_generic()
3375 /* Use interrupt-safe sleep just in case */ in ixgbe_disable_sec_rx_path_generic()
3388 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3389 * @hw: pointer to hardware structure
3395 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_generic() argument
3398 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_generic()
3403 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3404 * @hw: pointer to hardware structure
3411 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked) in prot_autoc_write_generic() argument
3415 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val); in prot_autoc_write_generic()
3420 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3421 * @hw: pointer to hardware structure
3425 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) in ixgbe_enable_sec_rx_path_generic() argument
3431 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); in ixgbe_enable_sec_rx_path_generic()
3433 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); in ixgbe_enable_sec_rx_path_generic()
3434 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_sec_rx_path_generic()
3440 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3441 * @hw: pointer to hardware structure
3446 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_generic() argument
3451 ixgbe_enable_rx(hw); in ixgbe_enable_rx_dma_generic()
3453 ixgbe_disable_rx(hw); in ixgbe_enable_rx_dma_generic()
3459 * ixgbe_blink_led_start_generic - Blink LED based on index.
3460 * @hw: pointer to hardware structure
3463 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_start_generic() argument
3468 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_start_generic()
3478 * Link must be up to auto-blink the LEDs; in ixgbe_blink_led_start_generic()
3481 hw->mac.ops.check_link(hw, &speed, &link_up, false); in ixgbe_blink_led_start_generic()
3484 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_start_generic()
3491 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_start_generic()
3495 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
3501 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_start_generic()
3502 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_start_generic()
3509 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3510 * @hw: pointer to hardware structure
3513 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) in ixgbe_blink_led_stop_generic() argument
3516 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); in ixgbe_blink_led_stop_generic()
3525 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg); in ixgbe_blink_led_stop_generic()
3532 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked); in ixgbe_blink_led_stop_generic()
3539 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); in ixgbe_blink_led_stop_generic()
3540 IXGBE_WRITE_FLUSH(hw); in ixgbe_blink_led_stop_generic()
3547 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3548 * @hw: pointer to hardware structure
3555 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, in ixgbe_get_san_mac_addr_offset() argument
3566 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, in ixgbe_get_san_mac_addr_offset()
3578 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3579 * @hw: pointer to hardware structure
3583 * per-port, so set_lan_id() must be called before reading the addresses.
3585 * upon for non-SFP connections, so we must call it here.
3587 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_get_san_mac_addr_generic() argument
3599 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_get_san_mac_addr_generic()
3604 hw->mac.ops.set_lan_id(hw); in ixgbe_get_san_mac_addr_generic()
3606 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_get_san_mac_addr_generic()
3609 ret_val = hw->eeprom.ops.read(hw, san_mac_offset, in ixgbe_get_san_mac_addr_generic()
3634 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3635 * @hw: pointer to hardware structure
3640 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) in ixgbe_set_san_mac_addr_generic() argument
3649 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); in ixgbe_set_san_mac_addr_generic()
3654 hw->mac.ops.set_lan_id(hw); in ixgbe_set_san_mac_addr_generic()
3656 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : in ixgbe_set_san_mac_addr_generic()
3662 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); in ixgbe_set_san_mac_addr_generic()
3670 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3671 * @hw: pointer to hardware structure
3673 * Read PCIe configuration space, and get the MSI-X vector count from
3676 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) in ixgbe_get_pcie_msix_count_generic() argument
3682 switch (hw->mac.type) { in ixgbe_get_pcie_msix_count_generic()
3700 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); in ixgbe_get_pcie_msix_count_generic()
3701 if (IXGBE_REMOVED(hw->hw_addr)) in ixgbe_get_pcie_msix_count_generic()
3705 /* MSI-X count is zero-based in HW */ in ixgbe_get_pcie_msix_count_generic()
3715 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3716 * @hw: pointer to hardware structure
3723 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) in ixgbe_insert_mac_addr_generic() argument
3733 /* swap bytes for HW little endian */ in ixgbe_insert_mac_addr_generic()
3745 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { in ixgbe_insert_mac_addr_generic()
3746 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); in ixgbe_insert_mac_addr_generic()
3752 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); in ixgbe_insert_mac_addr_generic()
3758 if (rar < hw->mac.rar_highwater) { in ixgbe_insert_mac_addr_generic()
3760 ixgbe_set_vmdq(hw, rar, vmdq); in ixgbe_insert_mac_addr_generic()
3764 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); in ixgbe_insert_mac_addr_generic()
3765 } else if (rar == hw->mac.rar_highwater) { in ixgbe_insert_mac_addr_generic()
3767 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); in ixgbe_insert_mac_addr_generic()
3768 hw->mac.rar_highwater++; in ixgbe_insert_mac_addr_generic()
3769 } else if (rar >= hw->mac.num_rar_entries) { in ixgbe_insert_mac_addr_generic()
3778 ixgbe_clear_vmdq(hw, rar, 0); in ixgbe_insert_mac_addr_generic()
3784 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3785 * @hw: pointer to hardware struct
3789 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_clear_vmdq_generic() argument
3792 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_clear_vmdq_generic()
3803 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
3804 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
3806 if (IXGBE_REMOVED(hw->hw_addr)) in ixgbe_clear_vmdq_generic()
3814 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_clear_vmdq_generic()
3815 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_clear_vmdq_generic()
3818 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_clear_vmdq_generic()
3819 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_clear_vmdq_generic()
3823 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); in ixgbe_clear_vmdq_generic()
3825 mpsar_hi &= ~(1 << (vmdq - 32)); in ixgbe_clear_vmdq_generic()
3826 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); in ixgbe_clear_vmdq_generic()
3831 rar != 0 && rar != hw->mac.san_mac_rar_index) in ixgbe_clear_vmdq_generic()
3832 hw->mac.ops.clear_rar(hw, rar); in ixgbe_clear_vmdq_generic()
3838 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3839 * @hw: pointer to hardware struct
3843 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) in ixgbe_set_vmdq_generic() argument
3846 u32 rar_entries = hw->mac.num_rar_entries; in ixgbe_set_vmdq_generic()
3858 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); in ixgbe_set_vmdq_generic()
3860 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); in ixgbe_set_vmdq_generic()
3862 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); in ixgbe_set_vmdq_generic()
3863 mpsar |= 1 << (vmdq - 32); in ixgbe_set_vmdq_generic()
3864 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); in ixgbe_set_vmdq_generic()
3870 * ixgbe_set_vmdq_san_mac_generic - Associate default VMDq pool index with
3872 * @hw: pointer to hardware struct
3878 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3880 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) in ixgbe_set_vmdq_san_mac_generic() argument
3882 u32 rar = hw->mac.san_mac_rar_index; in ixgbe_set_vmdq_san_mac_generic()
3887 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); in ixgbe_set_vmdq_san_mac_generic()
3888 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3890 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); in ixgbe_set_vmdq_san_mac_generic()
3891 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); in ixgbe_set_vmdq_san_mac_generic()
3898 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3899 * @hw: pointer to hardware structure
3901 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) in ixgbe_init_uta_tables_generic() argument
3909 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); in ixgbe_init_uta_tables_generic()
3915 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3916 * @hw: pointer to hardware structure
3925 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan, bool vlvf_bypass) in ixgbe_find_vlvf_slot() argument
3946 * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1 in ixgbe_find_vlvf_slot()
3948 for (regindex = IXGBE_VLVF_ENTRIES; --regindex;) { in ixgbe_find_vlvf_slot()
3949 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); in ixgbe_find_vlvf_slot()
3966 * ixgbe_set_vfta_generic - Set VLAN filter table
3967 * @hw: pointer to hardware structure
3975 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vfta_generic() argument
3987 * this is a 2 part operation - first the VFTA, then the in ixgbe_set_vfta_generic()
3993 * The VFTA is a bitstring made up of 128 32-bit registers in ixgbe_set_vfta_generic()
3995 * bits[11-5]: which register in ixgbe_set_vfta_generic()
3996 * bits[4-0]: which bit in the register in ixgbe_set_vfta_generic()
4000 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regidx)); in ixgbe_set_vfta_generic()
4013 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, &vfta_delta, in ixgbe_set_vfta_generic()
4024 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regidx), vfta); in ixgbe_set_vfta_generic()
4030 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
4031 * @hw: pointer to hardware structure
4042 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, in ixgbe_set_vlvf_generic() argument
4061 if (!(IXGBE_READ_REG(hw, IXGBE_VT_CTL) & IXGBE_VT_CTL_VT_ENABLE)) in ixgbe_set_vlvf_generic()
4064 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan, vlvf_bypass); in ixgbe_set_vlvf_generic()
4068 bits = IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32)); in ixgbe_set_vlvf_generic()
4079 !IXGBE_READ_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + 1 - vind / 32))) { in ixgbe_set_vlvf_generic()
4085 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vlan / 32), vfta); in ixgbe_set_vlvf_generic()
4088 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); in ixgbe_set_vlvf_generic()
4089 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), 0); in ixgbe_set_vlvf_generic()
4112 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(vlvf_index * 2 + vind / 32), bits); in ixgbe_set_vlvf_generic()
4113 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), IXGBE_VLVF_VIEN | vlan); in ixgbe_set_vlvf_generic()
4119 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4120 * @hw: pointer to hardware structure
4124 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) in ixgbe_clear_vfta_generic() argument
4130 for (offset = 0; offset < hw->mac.vft_size; offset++) in ixgbe_clear_vfta_generic()
4131 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); in ixgbe_clear_vfta_generic()
4134 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); in ixgbe_clear_vfta_generic()
4135 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); in ixgbe_clear_vfta_generic()
4136 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2 + 1), 0); in ixgbe_clear_vfta_generic()
4144 * ixgbe_toggle_txdctl_generic - Toggle VF's queues
4145 * @hw: pointer to hardware structure
4150 s32 ixgbe_toggle_txdctl_generic(struct ixgbe_hw *hw, u32 vf_number) in ixgbe_toggle_txdctl_generic() argument
4162 reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_toggle_txdctl_generic()
4183 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); in ixgbe_toggle_txdctl_generic()
4185 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); in ixgbe_toggle_txdctl_generic()
4186 IXGBE_WRITE_FLUSH(hw); in ixgbe_toggle_txdctl_generic()
4189 reg = IXGBE_READ_REG(hw, IXGBE_PVFTXDCTL(offset)); in ixgbe_toggle_txdctl_generic()
4191 IXGBE_WRITE_REG(hw, IXGBE_PVFTXDCTL(offset), reg); in ixgbe_toggle_txdctl_generic()
4192 IXGBE_WRITE_FLUSH(hw); in ixgbe_toggle_txdctl_generic()
4199 * ixgbe_need_crosstalk_fix - Determine if we need to do cross talk fix
4200 * @hw: pointer to hardware structure
4205 static bool ixgbe_need_crosstalk_fix(struct ixgbe_hw *hw) in ixgbe_need_crosstalk_fix() argument
4209 if (!hw->need_crosstalk_fix) in ixgbe_need_crosstalk_fix()
4213 switch (hw->mac.ops.get_media_type(hw)) { in ixgbe_need_crosstalk_fix()
4225 * ixgbe_check_mac_link_generic - Determine link and speed status
4226 * @hw: pointer to hardware structure
4233 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, in ixgbe_check_mac_link_generic() argument
4244 if (ixgbe_need_crosstalk_fix(hw)) { in ixgbe_check_mac_link_generic()
4247 switch (hw->mac.type) { in ixgbe_check_mac_link_generic()
4249 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
4254 sfp_cage_full = IXGBE_READ_REG(hw, IXGBE_ESDP) & in ixgbe_check_mac_link_generic()
4258 /* sanity check - No SFP+ devices here */ in ixgbe_check_mac_link_generic()
4271 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
4273 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
4281 for (i = 0; i < hw->mac.max_link_up_time; i++) { in ixgbe_check_mac_link_generic()
4289 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
4293 if (ixgbe_need_crosstalk_fix(hw)) { in ixgbe_check_mac_link_generic()
4299 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_check_mac_link_generic()
4316 if (hw->mac.type >= ixgbe_mac_X550) { in ixgbe_check_mac_link_generic()
4326 if (hw->mac.type == ixgbe_mac_X550) { in ixgbe_check_mac_link_generic()
4333 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T || in ixgbe_check_mac_link_generic()
4334 hw->device_id == IXGBE_DEV_ID_X550EM_A_1G_T_L) in ixgbe_check_mac_link_generic()
4345 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4347 * @hw: pointer to hardware structure
4354 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, in ixgbe_get_wwn_prefix_generic() argument
4368 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) in ixgbe_get_wwn_prefix_generic()
4377 if (hw->eeprom.ops.read(hw, offset, &caps)) in ixgbe_get_wwn_prefix_generic()
4384 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { in ixgbe_get_wwn_prefix_generic()
4390 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) in ixgbe_get_wwn_prefix_generic()
4403 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4404 * @hw: pointer to hardware structure
4409 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) in ixgbe_get_fcoe_boot_status_generic() argument
4421 status = hw->eeprom.ops.read(hw, offset, &caps); in ixgbe_get_fcoe_boot_status_generic()
4429 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); in ixgbe_get_fcoe_boot_status_generic()
4438 status = hw->eeprom.ops.read(hw, offset, &flags); in ixgbe_get_fcoe_boot_status_generic()
4452 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4453 * @hw: pointer to hardware structure
4454 * @enable: enable or disable switch for MAC anti-spoofing
4455 * @vf: Virtual Function pool - VF Pool to set for MAC anti-spoofing
4458 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_mac_anti_spoofing() argument
4464 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_mac_anti_spoofing()
4467 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_mac_anti_spoofing()
4472 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_mac_anti_spoofing()
4476 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4477 * @hw: pointer to hardware structure
4478 * @enable: enable or disable switch for VLAN anti-spoofing
4479 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4482 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) in ixgbe_set_vlan_anti_spoofing() argument
4488 if (hw->mac.type == ixgbe_mac_82598EB) in ixgbe_set_vlan_anti_spoofing()
4491 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); in ixgbe_set_vlan_anti_spoofing()
4496 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); in ixgbe_set_vlan_anti_spoofing()
4500 * ixgbe_get_device_caps_generic - Get additional device capabilities
4501 * @hw: pointer to hardware structure
4507 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) in ixgbe_get_device_caps_generic() argument
4511 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); in ixgbe_get_device_caps_generic()
4517 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4518 * @hw: pointer to hardware structure
4521 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) in ixgbe_enable_relaxed_ordering_gen2() argument
4529 for (i = 0; i < hw->mac.max_tx_queues; i++) { in ixgbe_enable_relaxed_ordering_gen2()
4530 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); in ixgbe_enable_relaxed_ordering_gen2()
4532 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); in ixgbe_enable_relaxed_ordering_gen2()
4535 for (i = 0; i < hw->mac.max_rx_queues; i++) { in ixgbe_enable_relaxed_ordering_gen2()
4536 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); in ixgbe_enable_relaxed_ordering_gen2()
4539 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); in ixgbe_enable_relaxed_ordering_gen2()
4545 * ixgbe_calculate_checksum - Calculate checksum for buffer
4564 return (u8) (0 - sum); in ixgbe_calculate_checksum()
4568 * ixgbe_hic_unlocked - Issue command to manageability block unlocked
4569 * @hw: pointer to the HW structure
4581 s32 ixgbe_hic_unlocked(struct ixgbe_hw *hw, u32 *buffer, u32 length, in ixgbe_hic_unlocked() argument
4595 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS); in ixgbe_hic_unlocked()
4596 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI); in ixgbe_hic_unlocked()
4599 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
4617 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_hic_unlocked()
4621 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); in ixgbe_hic_unlocked()
4624 hicr = IXGBE_READ_REG(hw, IXGBE_HICR); in ixgbe_hic_unlocked()
4639 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) { in ixgbe_hic_unlocked()
4649 * ixgbe_host_interface_command - Issue command to manageability block
4650 * @hw: pointer to the HW structure
4666 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, in ixgbe_host_interface_command() argument
4684 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
4688 status = ixgbe_hic_unlocked(hw, buffer, length, timeout); in ixgbe_host_interface_command()
4700 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
4709 if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD || in ixgbe_host_interface_command()
4710 resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) { in ixgbe_host_interface_command()
4712 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, in ixgbe_host_interface_command()
4716 buf_len = (((u16)(resp->cmd_or_resp.ret_status) << 3) in ixgbe_host_interface_command()
4717 & 0xF00) | resp->buf_len; in ixgbe_host_interface_command()
4720 buf_len = resp->buf_len; in ixgbe_host_interface_command()
4736 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); in ixgbe_host_interface_command()
4741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); in ixgbe_host_interface_command()
4747 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4748 * @hw: pointer to the HW structure
4761 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, in ixgbe_set_fw_drv_ver_generic() argument
4775 fw_cmd.port_num = (u8)hw->bus.func; in ixgbe_set_fw_drv_ver_generic()
4787 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, in ixgbe_set_fw_drv_ver_generic()
4807 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4808 * @hw: pointer to hardware structure
4813 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, in ixgbe_set_rxpba_generic() argument
4816 u32 pbsize = hw->mac.rx_pb_size; in ixgbe_set_rxpba_generic()
4821 pbsize -= headroom; in ixgbe_set_rxpba_generic()
4835 pbsize -= rxpktsize * (num_pb / 2); in ixgbe_set_rxpba_generic()
4838 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
4839 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; in ixgbe_set_rxpba_generic()
4841 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
4844 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; in ixgbe_set_rxpba_generic()
4846 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); in ixgbe_set_rxpba_generic()
4854 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; in ixgbe_set_rxpba_generic()
4856 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); in ixgbe_set_rxpba_generic()
4857 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); in ixgbe_set_rxpba_generic()
4862 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
4863 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); in ixgbe_set_rxpba_generic()
4864 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); in ixgbe_set_rxpba_generic()
4869 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4870 * @hw: pointer to the hardware structure
4876 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw) in ixgbe_clear_tx_pending() argument
4885 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) in ixgbe_clear_tx_pending()
4893 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); in ixgbe_clear_tx_pending()
4894 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); in ixgbe_clear_tx_pending()
4897 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
4904 poll = ixgbe_pcie_timeout_poll(hw); in ixgbe_clear_tx_pending()
4907 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS); in ixgbe_clear_tx_pending()
4908 if (IXGBE_REMOVED(hw->hw_addr)) in ixgbe_clear_tx_pending()
4915 /* initiate cleaning flow for buffers in the PCIe transaction layer */ in ixgbe_clear_tx_pending()
4916 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); in ixgbe_clear_tx_pending()
4917 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, in ixgbe_clear_tx_pending()
4921 IXGBE_WRITE_FLUSH(hw); in ixgbe_clear_tx_pending()
4925 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); in ixgbe_clear_tx_pending()
4926 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); in ixgbe_clear_tx_pending()
4943 * ixgbe_get_thermal_sensor_data_generic - Gathers thermal sensor data
4944 * @hw: pointer to hardware structure
4948 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw) in ixgbe_get_thermal_sensor_data_generic() argument
4958 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_get_thermal_sensor_data_generic()
4963 if ((hw->mac.type != ixgbe_mac_82599EB) || in ixgbe_get_thermal_sensor_data_generic()
4964 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) { in ixgbe_get_thermal_sensor_data_generic()
4969 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset); in ixgbe_get_thermal_sensor_data_generic()
4978 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg); in ixgbe_get_thermal_sensor_data_generic()
4993 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i), in ixgbe_get_thermal_sensor_data_generic()
5004 status = hw->phy.ops.read_i2c_byte(hw, in ixgbe_get_thermal_sensor_data_generic()
5007 &data->sensor[i].temp); in ixgbe_get_thermal_sensor_data_generic()
5017 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
5018 * @hw: pointer to hardware structure
5023 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw) in ixgbe_init_thermal_sensor_thresh_generic() argument
5036 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; in ixgbe_init_thermal_sensor_thresh_generic()
5043 if ((hw->mac.type != ixgbe_mac_82599EB) || in ixgbe_init_thermal_sensor_thresh_generic()
5044 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) in ixgbe_init_thermal_sensor_thresh_generic()
5048 if (hw->eeprom.ops.read(hw, offset, &ets_offset)) in ixgbe_init_thermal_sensor_thresh_generic()
5054 if (hw->eeprom.ops.read(hw, offset, &ets_cfg)) in ixgbe_init_thermal_sensor_thresh_generic()
5066 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) { in ixgbe_init_thermal_sensor_thresh_generic()
5078 hw->phy.ops.write_i2c_byte(hw, in ixgbe_init_thermal_sensor_thresh_generic()
5083 data->sensor[i].location = sensor_location; in ixgbe_init_thermal_sensor_thresh_generic()
5084 data->sensor[i].caution_thresh = therm_limit; in ixgbe_init_thermal_sensor_thresh_generic()
5085 data->sensor[i].max_op_thresh = therm_limit - in ixgbe_init_thermal_sensor_thresh_generic()
5098 * ixgbe_bypass_rw_generic - Bit bang data into by_pass FW
5100 * @hw: pointer to hardware structure
5104 * Bit-bangs the cmd to the by_pass FW status points to what is returned.
5107 s32 ixgbe_bypass_rw_generic(struct ixgbe_hw *hw, u32 cmd, u32 *status) in ixgbe_bypass_rw_generic() argument
5119 switch (hw->mac.type) { in ixgbe_bypass_rw_generic()
5141 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_bypass_rw_generic()
5147 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5148 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5153 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5154 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5158 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5159 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5164 if ((cmd >> (31 - i)) & 0x01) { in ixgbe_bypass_rw_generic()
5166 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5169 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5171 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5176 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5180 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5181 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5184 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_bypass_rw_generic()
5195 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5196 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5200 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_bypass_rw_generic()
5201 IXGBE_WRITE_FLUSH(hw); in ixgbe_bypass_rw_generic()
5210 * ixgbe_bypass_valid_rd_generic - Verify valid return from bit-bang.
5211 * @in_reg: The register cmd for the bit-bang read.
5212 * @out_reg: The register returned from a bit-bang read.
5231 * - All the event actions in ixgbe_bypass_valid_rd_generic()
5232 * - The timeout value in ixgbe_bypass_valid_rd_generic()
5247 * - time valid bit in ixgbe_bypass_valid_rd_generic()
5248 * - time we last sent in ixgbe_bypass_valid_rd_generic()
5266 * ixgbe_bypass_set_generic - Set a bypass field in the FW CTRL Regiter.
5268 * @hw: pointer to hardware structure
5269 * @ctrl: The control word we are setting.
5276 s32 ixgbe_bypass_set_generic(struct ixgbe_hw *hw, u32 ctrl, u32 event, in ixgbe_bypass_set_generic() argument
5284 cmd = ctrl; /* just reading only need control number */ in ixgbe_bypass_set_generic()
5285 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) in ixgbe_bypass_set_generic()
5290 if (ixgbe_bypass_rw_generic(hw, cmd, &by_ctl)) in ixgbe_bypass_set_generic()
5300 if (ixgbe_bypass_rw_generic(hw, verify, &by_ctl)) in ixgbe_bypass_set_generic()
5312 * ixgbe_bypass_rd_eep_generic - Read the bypass FW eeprom addres.
5314 * @hw: pointer to hardware structure
5318 s32 ixgbe_bypass_rd_eep_generic(struct ixgbe_hw *hw, u32 addr, u8 *value) in ixgbe_bypass_rd_eep_generic() argument
5327 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) in ixgbe_bypass_rd_eep_generic()
5335 if (ixgbe_bypass_rw_generic(hw, cmd, &status)) in ixgbe_bypass_rd_eep_generic()
5344 * ixgbe_get_orom_version - Return option ROM from EEPROM
5346 * @hw: pointer to hardware structure
5349 * if valid option ROM version, nvm_ver->or_valid set to true
5350 * else nvm_ver->or_valid is false.
5352 void ixgbe_get_orom_version(struct ixgbe_hw *hw, in ixgbe_get_orom_version() argument
5357 nvm_ver->or_valid = false; in ixgbe_get_orom_version()
5359 hw->eeprom.ops.read(hw, NVM_OROM_OFFSET, &offset); in ixgbe_get_orom_version()
5365 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_HI, &eeprom_cfg_blkh); in ixgbe_get_orom_version()
5366 hw->eeprom.ops.read(hw, offset + NVM_OROM_BLK_LOW, &eeprom_cfg_blkl); in ixgbe_get_orom_version()
5374 nvm_ver->or_valid = true; in ixgbe_get_orom_version()
5375 nvm_ver->or_major = eeprom_cfg_blkl >> NVM_OROM_SHIFT; in ixgbe_get_orom_version()
5376 nvm_ver->or_build = (eeprom_cfg_blkl << NVM_OROM_SHIFT) | in ixgbe_get_orom_version()
5378 nvm_ver->or_patch = eeprom_cfg_blkh & NVM_OROM_PATCH_MASK; in ixgbe_get_orom_version()
5382 * ixgbe_get_oem_prod_version - Return OEM Product version
5384 * @hw: pointer to hardware structure
5387 * if valid OEM product version, nvm_ver->oem_valid set to true
5388 * else nvm_ver->oem_valid is false.
5390 void ixgbe_get_oem_prod_version(struct ixgbe_hw *hw, in ixgbe_get_oem_prod_version() argument
5395 nvm_ver->oem_valid = false; in ixgbe_get_oem_prod_version()
5396 hw->eeprom.ops.read(hw, NVM_OEM_PROD_VER_PTR, &offset); in ixgbe_get_oem_prod_version()
5403 hw->eeprom.ops.read(hw, offset, &mod_len); in ixgbe_get_oem_prod_version()
5404 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_CAP_OFF, &cap); in ixgbe_get_oem_prod_version()
5411 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_L, &prod_ver); in ixgbe_get_oem_prod_version()
5412 hw->eeprom.ops.read(hw, offset + NVM_OEM_PROD_VER_OFF_H, &rel_num); in ixgbe_get_oem_prod_version()
5419 nvm_ver->oem_major = prod_ver >> NVM_VER_SHIFT; in ixgbe_get_oem_prod_version()
5420 nvm_ver->oem_minor = prod_ver & NVM_VER_MASK; in ixgbe_get_oem_prod_version()
5421 nvm_ver->oem_release = rel_num; in ixgbe_get_oem_prod_version()
5422 nvm_ver->oem_valid = true; in ixgbe_get_oem_prod_version()
5426 * ixgbe_get_etk_id - Return Etrack ID from EEPROM
5428 * @hw: pointer to hardware structure
5433 void ixgbe_get_etk_id(struct ixgbe_hw *hw, struct ixgbe_nvm_version *nvm_ver) in ixgbe_get_etk_id() argument
5437 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_LOW, &etk_id_l)) in ixgbe_get_etk_id()
5439 if (hw->eeprom.ops.read(hw, NVM_ETK_OFF_HI, &etk_id_h)) in ixgbe_get_etk_id()
5446 nvm_ver->etk_id = etk_id_h; in ixgbe_get_etk_id()
5447 nvm_ver->etk_id |= (etk_id_l << NVM_ETK_SHIFT); in ixgbe_get_etk_id()
5449 nvm_ver->etk_id = etk_id_l; in ixgbe_get_etk_id()
5450 nvm_ver->etk_id |= (etk_id_h << NVM_ETK_SHIFT); in ixgbe_get_etk_id()
5455 * ixgbe_get_nvm_version - Return version of NVM and its components
5457 * @hw: pointer to hardware structure
5462 void ixgbe_get_nvm_version(struct ixgbe_hw *hw, in ixgbe_get_nvm_version() argument
5471 /* eeprom version is mac-type specific */ in ixgbe_get_nvm_version()
5472 switch (hw->mac.type) { in ixgbe_get_nvm_version()
5475 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_82598, &word)) in ixgbe_get_nvm_version()
5477 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) in ixgbe_get_nvm_version()
5479 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) in ixgbe_get_nvm_version()
5481 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); in ixgbe_get_nvm_version()
5485 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) in ixgbe_get_nvm_version()
5487 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) in ixgbe_get_nvm_version()
5489 nvm_ver->nvm_minor = ((word & NVM_EEP_MINOR_MASK) in ixgbe_get_nvm_version()
5491 nvm_ver->nvm_id = (word & NVM_EEP_ID_MASK); in ixgbe_get_nvm_version()
5498 if (ixgbe_read_eeprom(hw, NVM_EEP_OFFSET_X540, &word)) in ixgbe_get_nvm_version()
5500 nvm_ver->nvm_major = ((word & NVM_EEP_MAJOR_MASK) in ixgbe_get_nvm_version()
5502 nvm_ver->nvm_minor = (word & NVM_EEP_X550_MINOR_MASK); in ixgbe_get_nvm_version()
5509 /* phy version is mac-type specific */ in ixgbe_get_nvm_version()
5510 switch (hw->mac.type) { in ixgbe_get_nvm_version()
5516 if (ixgbe_read_eeprom(hw, NVM_EEP_PHY_OFF_X540, &word)) in ixgbe_get_nvm_version()
5518 nvm_ver->phy_fw_maj = ((word & NVM_PHY_MAJOR_MASK) in ixgbe_get_nvm_version()
5520 nvm_ver->phy_fw_min = ((word & NVM_PHY_MINOR_MASK) in ixgbe_get_nvm_version()
5522 nvm_ver->phy_fw_id = (word & NVM_PHY_ID_MASK); in ixgbe_get_nvm_version()
5528 ixgbe_get_etk_id(hw, nvm_ver); in ixgbe_get_nvm_version()
5531 if (ixgbe_read_eeprom(hw, NVM_DS_OFFSET, &word)) in ixgbe_get_nvm_version()
5533 nvm_ver->devstart_major = ((word & NVM_DS_MAJOR_MASK) >> NVM_DS_SHIFT); in ixgbe_get_nvm_version()
5534 nvm_ver->devstart_minor = (word & NVM_DS_MINOR_MASK); in ixgbe_get_nvm_version()
5537 if (ixgbe_read_eeprom(hw, NVM_OEM_OFFSET, &nvm_ver->oem_specific)) in ixgbe_get_nvm_version()
5538 nvm_ver->oem_specific = NVM_VER_INVALID; in ixgbe_get_nvm_version()
5541 if (ixgbe_get_phy_firmware_version(hw, &phy_ver)) in ixgbe_get_nvm_version()
5543 nvm_ver->phy_vend_maj = ((phy_ver & NVM_PHYVEND_MAJOR_MASK) in ixgbe_get_nvm_version()
5545 nvm_ver->phy_vend_min = (phy_ver & NVM_PHYVEND_MINOR_MASK); in ixgbe_get_nvm_version()
5548 ixgbe_get_orom_version(hw, nvm_ver); in ixgbe_get_nvm_version()
5553 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
5554 * @hw: pointer to hardware structure
5557 * Read the rtrup2tc HW register and resolve its content into map
5559 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) in ixgbe_dcb_get_rtrup2tc_generic() argument
5563 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); in ixgbe_dcb_get_rtrup2tc_generic()
5570 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw) in ixgbe_disable_rx_generic() argument
5575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_disable_rx_generic()
5577 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_disable_rx_generic()
5578 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_disable_rx_generic()
5581 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_disable_rx_generic()
5582 hw->mac.set_lben = true; in ixgbe_disable_rx_generic()
5584 hw->mac.set_lben = false; in ixgbe_disable_rx_generic()
5588 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); in ixgbe_disable_rx_generic()
5592 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw) in ixgbe_enable_rx_generic() argument
5597 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_enable_rx_generic()
5598 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN)); in ixgbe_enable_rx_generic()
5600 if (hw->mac.type != ixgbe_mac_82598EB) { in ixgbe_enable_rx_generic()
5601 if (hw->mac.set_lben) { in ixgbe_enable_rx_generic()
5602 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); in ixgbe_enable_rx_generic()
5604 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); in ixgbe_enable_rx_generic()
5605 hw->mac.set_lben = false; in ixgbe_enable_rx_generic()
5611 * ixgbe_mng_present - returns true when management capability is present
5612 * @hw: pointer to hardware structure
5614 bool ixgbe_mng_present(struct ixgbe_hw *hw) in ixgbe_mng_present() argument
5618 if (hw->mac.type < ixgbe_mac_82599EB) in ixgbe_mng_present()
5621 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); in ixgbe_mng_present()
5627 * ixgbe_mng_enabled - Is the manageability engine enabled?
5628 * @hw: pointer to hardware structure
5632 bool ixgbe_mng_enabled(struct ixgbe_hw *hw) in ixgbe_mng_enabled() argument
5636 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)); in ixgbe_mng_enabled()
5640 manc = IXGBE_READ_REG(hw, IXGBE_MANC); in ixgbe_mng_enabled()
5644 if (hw->mac.type <= ixgbe_mac_X540) { in ixgbe_mng_enabled()
5645 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS_BY_MAC(hw)); in ixgbe_mng_enabled()
5654 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
5655 * @hw: pointer to hardware structure
5661 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_multispeed_fiber() argument
5674 /* Mask off requested but non-supported speeds */ in ixgbe_setup_mac_link_multispeed_fiber()
5675 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg); in ixgbe_setup_mac_link_multispeed_fiber()
5689 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
5692 ixgbe_set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
5703 /* Allow module to change analog characteristics (1G->10G) */ in ixgbe_setup_mac_link_multispeed_fiber()
5706 status = ixgbe_setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
5713 ixgbe_flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
5724 status = ixgbe_check_link(hw, &link_speed, in ixgbe_setup_mac_link_multispeed_fiber()
5740 switch (hw->phy.media_type) { in ixgbe_setup_mac_link_multispeed_fiber()
5743 ixgbe_set_rate_select_speed(hw, in ixgbe_setup_mac_link_multispeed_fiber()
5754 /* Allow module to change analog characteristics (10G->1G) */ in ixgbe_setup_mac_link_multispeed_fiber()
5757 status = ixgbe_setup_mac_link(hw, in ixgbe_setup_mac_link_multispeed_fiber()
5764 ixgbe_flap_tx_laser(hw); in ixgbe_setup_mac_link_multispeed_fiber()
5770 status = ixgbe_check_link(hw, &link_speed, &link_up, false); in ixgbe_setup_mac_link_multispeed_fiber()
5783 status = ixgbe_setup_mac_link_multispeed_fiber(hw, in ixgbe_setup_mac_link_multispeed_fiber()
5789 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_multispeed_fiber()
5792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
5795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_multispeed_fiber()
5801 * ixgbe_set_soft_rate_select_speed - Set module link speed
5802 * @hw: pointer to hardware structure
5807 void ixgbe_set_soft_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_soft_rate_select_speed() argument
5827 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
5837 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB, in ixgbe_set_soft_rate_select_speed()
5846 status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()
5856 status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB, in ixgbe_set_soft_rate_select_speed()