Lines Matching +full:hw +full:- +full:timeout +full:- +full:ms
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
48 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
51 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
54 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
56 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
58 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) in ixgbe_init_mac_link_ops_82599() argument
63 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 !ixgbe_mng_enabled(hw)) { in ixgbe_init_mac_link_ops_82599()
73 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
75 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
77 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
81 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
82 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
85 if (hw->phy.multispeed_fiber) { in ixgbe_init_mac_link_ops_82599()
87 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
88 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
89 mac->ops.set_rate_select_speed = in ixgbe_init_mac_link_ops_82599()
91 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) in ixgbe_init_mac_link_ops_82599()
92 mac->ops.set_rate_select_speed = in ixgbe_init_mac_link_ops_82599()
95 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && in ixgbe_init_mac_link_ops_82599()
96 (hw->phy.smart_speed == ixgbe_smart_speed_auto || in ixgbe_init_mac_link_ops_82599()
97 hw->phy.smart_speed == ixgbe_smart_speed_on) && in ixgbe_init_mac_link_ops_82599()
98 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { in ixgbe_init_mac_link_ops_82599()
99 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; in ixgbe_init_mac_link_ops_82599()
101 mac->ops.setup_link = ixgbe_setup_mac_link_82599; in ixgbe_init_mac_link_ops_82599()
107 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
108 * @hw: pointer to hardware structure
115 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) in ixgbe_init_phy_ops_82599() argument
117 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_phy_ops_82599()
118 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_phy_ops_82599()
124 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { in ixgbe_init_phy_ops_82599()
126 hw->phy.qsfp_shared_i2c_bus = true; in ixgbe_init_phy_ops_82599()
129 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_init_phy_ops_82599()
135 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_init_phy_ops_82599()
136 IXGBE_WRITE_FLUSH(hw); in ixgbe_init_phy_ops_82599()
138 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
139 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; in ixgbe_init_phy_ops_82599()
142 ret_val = phy->ops.identify(hw); in ixgbe_init_phy_ops_82599()
147 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_init_phy_ops_82599()
148 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) in ixgbe_init_phy_ops_82599()
149 hw->phy.ops.reset = NULL; in ixgbe_init_phy_ops_82599()
152 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { in ixgbe_init_phy_ops_82599()
153 mac->ops.setup_link = ixgbe_setup_copper_link_82599; in ixgbe_init_phy_ops_82599()
154 mac->ops.get_link_capabilities = in ixgbe_init_phy_ops_82599()
159 switch (hw->phy.type) { in ixgbe_init_phy_ops_82599()
161 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; in ixgbe_init_phy_ops_82599()
162 phy->ops.check_link = ixgbe_check_phy_link_tnx; in ixgbe_init_phy_ops_82599()
163 phy->ops.get_firmware_version = in ixgbe_init_phy_ops_82599()
173 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) in ixgbe_setup_sfp_modules_82599() argument
180 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { in ixgbe_setup_sfp_modules_82599()
181 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_setup_sfp_modules_82599()
183 hw->phy.ops.reset = NULL; in ixgbe_setup_sfp_modules_82599()
185 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, in ixgbe_setup_sfp_modules_82599()
191 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_setup_sfp_modules_82599()
198 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
201 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); in ixgbe_setup_sfp_modules_82599()
202 IXGBE_WRITE_FLUSH(hw); in ixgbe_setup_sfp_modules_82599()
203 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) in ixgbe_setup_sfp_modules_82599()
208 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
212 msec_delay(hw->eeprom.semaphore_delay); in ixgbe_setup_sfp_modules_82599()
215 ret_val = hw->mac.ops.prot_autoc_write(hw, in ixgbe_setup_sfp_modules_82599()
216 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, in ixgbe_setup_sfp_modules_82599()
232 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_setup_sfp_modules_82599()
234 msec_delay(hw->eeprom.semaphore_delay); in ixgbe_setup_sfp_modules_82599()
241 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
242 * @hw: pointer to hardware structure
246 * For this part (82599) we need to wrap read-modify-writes with a possible
250 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val) in prot_autoc_read_82599() argument
256 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { in prot_autoc_read_82599()
257 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_read_82599()
265 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); in prot_autoc_read_82599()
270 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
271 * @hw: pointer to hardware structure
279 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked) in prot_autoc_write_82599() argument
284 if (ixgbe_check_reset_blocked(hw)) in prot_autoc_write_82599()
288 * - We didn't do it already (in the read part of a read-modify-write) in prot_autoc_write_82599()
289 * - LESM is enabled. in prot_autoc_write_82599()
291 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { in prot_autoc_write_82599()
292 ret_val = hw->mac.ops.acquire_swfw_sync(hw, in prot_autoc_write_82599()
300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); in prot_autoc_write_82599()
301 ret_val = ixgbe_reset_pipeline_82599(hw); in prot_autoc_write_82599()
308 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in prot_autoc_write_82599()
314 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
315 * @hw: pointer to hardware structure
321 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw) in ixgbe_init_ops_82599() argument
323 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_82599()
324 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_82599()
325 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_82599()
331 ixgbe_init_phy_ops_generic(hw); in ixgbe_init_ops_82599()
332 ret_val = ixgbe_init_ops_generic(hw); in ixgbe_init_ops_82599()
335 phy->ops.identify = ixgbe_identify_phy_82599; in ixgbe_init_ops_82599()
336 phy->ops.init = ixgbe_init_phy_ops_82599; in ixgbe_init_ops_82599()
339 mac->ops.reset_hw = ixgbe_reset_hw_82599; in ixgbe_init_ops_82599()
340 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; in ixgbe_init_ops_82599()
341 mac->ops.get_media_type = ixgbe_get_media_type_82599; in ixgbe_init_ops_82599()
342 mac->ops.get_supported_physical_layer = in ixgbe_init_ops_82599()
344 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; in ixgbe_init_ops_82599()
345 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; in ixgbe_init_ops_82599()
346 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; in ixgbe_init_ops_82599()
347 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; in ixgbe_init_ops_82599()
348 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; in ixgbe_init_ops_82599()
349 mac->ops.start_hw = ixgbe_start_hw_82599; in ixgbe_init_ops_82599()
350 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; in ixgbe_init_ops_82599()
351 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; in ixgbe_init_ops_82599()
352 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; in ixgbe_init_ops_82599()
353 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; in ixgbe_init_ops_82599()
354 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; in ixgbe_init_ops_82599()
355 mac->ops.prot_autoc_read = prot_autoc_read_82599; in ixgbe_init_ops_82599()
356 mac->ops.prot_autoc_write = prot_autoc_write_82599; in ixgbe_init_ops_82599()
359 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; in ixgbe_init_ops_82599()
360 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; in ixgbe_init_ops_82599()
361 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; in ixgbe_init_ops_82599()
362 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; in ixgbe_init_ops_82599()
363 mac->rar_highwater = 1; in ixgbe_init_ops_82599()
364 mac->ops.set_vfta = ixgbe_set_vfta_generic; in ixgbe_init_ops_82599()
365 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; in ixgbe_init_ops_82599()
366 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; in ixgbe_init_ops_82599()
367 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; in ixgbe_init_ops_82599()
368 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; in ixgbe_init_ops_82599()
369 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; in ixgbe_init_ops_82599()
370 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; in ixgbe_init_ops_82599()
373 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; in ixgbe_init_ops_82599()
374 mac->ops.check_link = ixgbe_check_mac_link_generic; in ixgbe_init_ops_82599()
375 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; in ixgbe_init_ops_82599()
376 ixgbe_init_mac_link_ops_82599(hw); in ixgbe_init_ops_82599()
378 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; in ixgbe_init_ops_82599()
379 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; in ixgbe_init_ops_82599()
380 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; in ixgbe_init_ops_82599()
381 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; in ixgbe_init_ops_82599()
382 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; in ixgbe_init_ops_82599()
383 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; in ixgbe_init_ops_82599()
384 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); in ixgbe_init_ops_82599()
386 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) in ixgbe_init_ops_82599()
390 hw->mbx.ops[i].init_params = ixgbe_init_mbx_params_pf; in ixgbe_init_ops_82599()
393 eeprom->ops.read = ixgbe_read_eeprom_82599; in ixgbe_init_ops_82599()
394 eeprom->ops.read_buffer = ixgbe_read_eeprom_buffer_82599; in ixgbe_init_ops_82599()
397 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; in ixgbe_init_ops_82599()
399 mac->ops.get_thermal_sensor_data = in ixgbe_init_ops_82599()
401 mac->ops.init_thermal_sensor_thresh = in ixgbe_init_ops_82599()
404 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; in ixgbe_init_ops_82599()
405 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; in ixgbe_init_ops_82599()
406 mac->ops.bypass_set = ixgbe_bypass_set_generic; in ixgbe_init_ops_82599()
407 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; in ixgbe_init_ops_82599()
409 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; in ixgbe_init_ops_82599()
415 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
416 * @hw: pointer to hardware structure
422 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, in ixgbe_get_link_capabilities_82599() argument
433 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || in ixgbe_get_link_capabilities_82599()
434 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || in ixgbe_get_link_capabilities_82599()
435 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || in ixgbe_get_link_capabilities_82599()
436 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || in ixgbe_get_link_capabilities_82599()
437 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || in ixgbe_get_link_capabilities_82599()
438 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 || in ixgbe_get_link_capabilities_82599()
439 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 || in ixgbe_get_link_capabilities_82599()
440 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1) { in ixgbe_get_link_capabilities_82599()
446 if (hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core0 || in ixgbe_get_link_capabilities_82599()
447 hw->phy.sfp_type == ixgbe_sfp_type_da_cu_core1) { in ixgbe_get_link_capabilities_82599()
451 if (hw->phy.multispeed_fiber) in ixgbe_get_link_capabilities_82599()
462 if (hw->mac.orig_link_settings_stored) in ixgbe_get_link_capabilities_82599()
463 autoc = hw->mac.orig_autoc; in ixgbe_get_link_capabilities_82599()
465 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_get_link_capabilities_82599()
522 if (hw->phy.multispeed_fiber) { in ixgbe_get_link_capabilities_82599()
526 /* QSFP must not enable full auto-negotiation in ixgbe_get_link_capabilities_82599()
529 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) in ixgbe_get_link_capabilities_82599()
540 * ixgbe_get_media_type_82599 - Get media type
541 * @hw: pointer to hardware structure
545 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) in ixgbe_get_media_type_82599() argument
552 switch (hw->phy.type) { in ixgbe_get_media_type_82599()
561 switch (hw->device_id) { in ixgbe_get_media_type_82599()
593 hw->phy.multispeed_fiber = true; in ixgbe_get_media_type_82599()
604 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
605 * @hw: pointer to hardware structure
610 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) in ixgbe_stop_mac_link_on_d3_82599() argument
616 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); in ixgbe_stop_mac_link_on_d3_82599()
618 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && in ixgbe_stop_mac_link_on_d3_82599()
620 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_stop_mac_link_on_d3_82599()
622 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); in ixgbe_stop_mac_link_on_d3_82599()
627 * ixgbe_start_mac_link_82599 - Setup MAC link settings
628 * @hw: pointer to hardware structure
634 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, in ixgbe_start_mac_link_82599() argument
649 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { in ixgbe_start_mac_link_82599()
650 status = hw->mac.ops.acquire_swfw_sync(hw, in ixgbe_start_mac_link_82599()
659 ixgbe_reset_pipeline_82599(hw); in ixgbe_start_mac_link_82599()
662 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); in ixgbe_start_mac_link_82599()
666 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_start_mac_link_82599()
675 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_start_mac_link_82599()
695 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
696 * @hw: pointer to hardware structure
702 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_disable_tx_laser_multispeed_fiber() argument
704 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_disable_tx_laser_multispeed_fiber()
707 if (ixgbe_check_reset_blocked(hw)) in ixgbe_disable_tx_laser_multispeed_fiber()
712 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_disable_tx_laser_multispeed_fiber()
713 IXGBE_WRITE_FLUSH(hw); in ixgbe_disable_tx_laser_multispeed_fiber()
718 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
719 * @hw: pointer to hardware structure
725 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_enable_tx_laser_multispeed_fiber() argument
727 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_enable_tx_laser_multispeed_fiber()
729 /* Enable Tx laser; allow 100ms to light up */ in ixgbe_enable_tx_laser_multispeed_fiber()
731 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_enable_tx_laser_multispeed_fiber()
732 IXGBE_WRITE_FLUSH(hw); in ixgbe_enable_tx_laser_multispeed_fiber()
737 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
738 * @hw: pointer to hardware structure
743 * so, we set the speed then disable and re-enable the Tx laser, to
748 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) in ixgbe_flap_tx_laser_multispeed_fiber() argument
753 if (ixgbe_check_reset_blocked(hw)) in ixgbe_flap_tx_laser_multispeed_fiber()
756 if (hw->mac.autotry_restart) { in ixgbe_flap_tx_laser_multispeed_fiber()
757 ixgbe_disable_tx_laser_multispeed_fiber(hw); in ixgbe_flap_tx_laser_multispeed_fiber()
758 ixgbe_enable_tx_laser_multispeed_fiber(hw); in ixgbe_flap_tx_laser_multispeed_fiber()
759 hw->mac.autotry_restart = false; in ixgbe_flap_tx_laser_multispeed_fiber()
764 * ixgbe_set_hard_rate_select_speed - Set module link speed
765 * @hw: pointer to hardware structure
770 void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, in ixgbe_set_hard_rate_select_speed() argument
773 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_set_hard_rate_select_speed()
788 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); in ixgbe_set_hard_rate_select_speed()
789 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_hard_rate_select_speed()
793 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
794 * @hw: pointer to hardware structure
800 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_smartspeed() argument
808 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_setup_mac_link_smartspeed()
813 hw->phy.autoneg_advertised = 0; in ixgbe_setup_mac_link_smartspeed()
816 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; in ixgbe_setup_mac_link_smartspeed()
819 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; in ixgbe_setup_mac_link_smartspeed()
822 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; in ixgbe_setup_mac_link_smartspeed()
832 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
834 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
841 * Section 73.10.2, we may have to wait up to 500ms if KR is in ixgbe_setup_mac_link_smartspeed()
842 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per in ixgbe_setup_mac_link_smartspeed()
849 status = ixgbe_check_link(hw, &link_speed, &link_up, in ixgbe_setup_mac_link_smartspeed()
868 hw->phy.smart_speed_active = true; in ixgbe_setup_mac_link_smartspeed()
869 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
875 * Wait for the controller to acquire link. 600ms will allow for in ixgbe_setup_mac_link_smartspeed()
878 * connect attempts as defined in the AN MAS table 73-7. in ixgbe_setup_mac_link_smartspeed()
884 status = ixgbe_check_link(hw, &link_speed, &link_up, false); in ixgbe_setup_mac_link_smartspeed()
893 hw->phy.smart_speed_active = false; in ixgbe_setup_mac_link_smartspeed()
894 status = ixgbe_setup_mac_link_82599(hw, speed, in ixgbe_setup_mac_link_smartspeed()
905 * ixgbe_setup_mac_link_82599 - Set MAC link speed
906 * @hw: pointer to hardware structure
912 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, in ixgbe_setup_mac_link_82599() argument
919 …u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this … in ixgbe_setup_mac_link_82599()
922 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_setup_mac_link_82599()
931 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg); in ixgbe_setup_mac_link_82599()
943 if (hw->mac.orig_link_settings_stored) in ixgbe_setup_mac_link_82599()
944 orig_autoc = hw->mac.orig_autoc; in ixgbe_setup_mac_link_82599()
960 (hw->phy.smart_speed_active == false)) in ixgbe_setup_mac_link_82599()
980 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) in ixgbe_setup_mac_link_82599()
989 status = hw->mac.ops.prot_autoc_write(hw, autoc, false); in ixgbe_setup_mac_link_82599()
1001 IXGBE_READ_REG(hw, IXGBE_LINKS); in ixgbe_setup_mac_link_82599()
1023 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1024 * @hw: pointer to hardware structure
1030 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, in ixgbe_setup_copper_link_82599() argument
1039 status = hw->phy.ops.setup_link_speed(hw, speed, in ixgbe_setup_copper_link_82599()
1042 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); in ixgbe_setup_copper_link_82599()
1048 * ixgbe_reset_hw_82599 - Perform hardware reset
1049 * @hw: pointer to hardware structure
1055 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw) in ixgbe_reset_hw_82599() argument
1067 status = hw->mac.ops.stop_adapter(hw); in ixgbe_reset_hw_82599()
1072 ixgbe_clear_tx_pending(hw); in ixgbe_reset_hw_82599()
1077 status = hw->phy.ops.init(hw); in ixgbe_reset_hw_82599()
1083 if (hw->phy.sfp_setup_needed) { in ixgbe_reset_hw_82599()
1084 status = hw->mac.ops.setup_sfp(hw); in ixgbe_reset_hw_82599()
1085 hw->phy.sfp_setup_needed = false; in ixgbe_reset_hw_82599()
1092 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL) in ixgbe_reset_hw_82599()
1093 hw->phy.ops.reset(hw); in ixgbe_reset_hw_82599()
1096 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; in ixgbe_reset_hw_82599()
1106 if (!hw->force_full_reset) { in ixgbe_reset_hw_82599()
1107 hw->mac.ops.check_link(hw, &link_speed, &link_up, false); in ixgbe_reset_hw_82599()
1112 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); in ixgbe_reset_hw_82599()
1113 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); in ixgbe_reset_hw_82599()
1114 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_hw_82599()
1116 /* Poll for reset bit to self-clear meaning reset is complete */ in ixgbe_reset_hw_82599()
1119 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); in ixgbe_reset_hw_82599()
1134 * allow time for any pending HW events to complete. in ixgbe_reset_hw_82599()
1136 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { in ixgbe_reset_hw_82599()
1137 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; in ixgbe_reset_hw_82599()
1146 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_reset_hw_82599()
1147 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_reset_hw_82599()
1152 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
1153 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_hw_82599()
1156 if (hw->mac.orig_link_settings_stored == false) { in ixgbe_reset_hw_82599()
1157 hw->mac.orig_autoc = autoc; in ixgbe_reset_hw_82599()
1158 hw->mac.orig_autoc2 = autoc2; in ixgbe_reset_hw_82599()
1159 hw->mac.orig_link_settings_stored = true; in ixgbe_reset_hw_82599()
1162 /* If MNG FW is running on a multi-speed device that in ixgbe_reset_hw_82599()
1168 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || in ixgbe_reset_hw_82599()
1169 hw->wol_enabled) in ixgbe_reset_hw_82599()
1170 hw->mac.orig_autoc = in ixgbe_reset_hw_82599()
1171 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | in ixgbe_reset_hw_82599()
1174 if (autoc != hw->mac.orig_autoc) { in ixgbe_reset_hw_82599()
1175 status = hw->mac.ops.prot_autoc_write(hw, in ixgbe_reset_hw_82599()
1176 hw->mac.orig_autoc, in ixgbe_reset_hw_82599()
1183 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { in ixgbe_reset_hw_82599()
1185 autoc2 |= (hw->mac.orig_autoc2 & in ixgbe_reset_hw_82599()
1187 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); in ixgbe_reset_hw_82599()
1192 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); in ixgbe_reset_hw_82599()
1199 hw->mac.num_rar_entries = 128; in ixgbe_reset_hw_82599()
1200 hw->mac.ops.init_rx_addrs(hw); in ixgbe_reset_hw_82599()
1203 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); in ixgbe_reset_hw_82599()
1206 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { in ixgbe_reset_hw_82599()
1208 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; in ixgbe_reset_hw_82599()
1210 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1211 hw->mac.san_addr, 0, IXGBE_RAH_AV); in ixgbe_reset_hw_82599()
1214 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, in ixgbe_reset_hw_82599()
1218 hw->mac.num_rar_entries--; in ixgbe_reset_hw_82599()
1222 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, in ixgbe_reset_hw_82599()
1223 &hw->mac.wwpn_prefix); in ixgbe_reset_hw_82599()
1230 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1231 * @hw: pointer to hardware structure
1234 static s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, u32 *fdircmd) in ixgbe_fdir_check_cmd_complete() argument
1239 *fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD); in ixgbe_fdir_check_cmd_complete()
1249 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1250 * @hw: pointer to hardware structure
1252 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw) in ixgbe_reinit_fdir_tables_82599() argument
1256 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); in ixgbe_reinit_fdir_tables_82599()
1266 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_reinit_fdir_tables_82599()
1268 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n"); in ixgbe_reinit_fdir_tables_82599()
1272 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0); in ixgbe_reinit_fdir_tables_82599()
1273 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1277 * before re-writing the FDIRCTRL control register with the same value. in ixgbe_reinit_fdir_tables_82599()
1278 * - write 1 to bit 8 of FDIRCMD register & in ixgbe_reinit_fdir_tables_82599()
1279 * - write 0 to bit 8 of FDIRCMD register in ixgbe_reinit_fdir_tables_82599()
1281 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_reinit_fdir_tables_82599()
1282 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | in ixgbe_reinit_fdir_tables_82599()
1284 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1285 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_reinit_fdir_tables_82599()
1286 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & in ixgbe_reinit_fdir_tables_82599()
1288 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1293 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00); in ixgbe_reinit_fdir_tables_82599()
1294 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1296 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); in ixgbe_reinit_fdir_tables_82599()
1297 IXGBE_WRITE_FLUSH(hw); in ixgbe_reinit_fdir_tables_82599()
1299 /* Poll init-done after we write FDIRCTRL register */ in ixgbe_reinit_fdir_tables_82599()
1301 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & in ixgbe_reinit_fdir_tables_82599()
1312 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT); in ixgbe_reinit_fdir_tables_82599()
1313 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT); in ixgbe_reinit_fdir_tables_82599()
1314 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); in ixgbe_reinit_fdir_tables_82599()
1315 IXGBE_READ_REG(hw, IXGBE_FDIRMISS); in ixgbe_reinit_fdir_tables_82599()
1316 IXGBE_READ_REG(hw, IXGBE_FDIRLEN); in ixgbe_reinit_fdir_tables_82599()
1322 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1323 * @hw: pointer to hardware structure
1326 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl) in ixgbe_fdir_enable_82599() argument
1333 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY); in ixgbe_fdir_enable_82599()
1334 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY); in ixgbe_fdir_enable_82599()
1337 * Poll init-done after we write the register. Estimated times: in ixgbe_fdir_enable_82599()
1340 * 100M: PBALLOC = 11b, timing is 6ms in ixgbe_fdir_enable_82599()
1349 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl); in ixgbe_fdir_enable_82599()
1350 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_enable_82599()
1352 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) & in ixgbe_fdir_enable_82599()
1363 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1364 * @hw: pointer to hardware structure
1368 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl) in ixgbe_init_fdir_signature_82599() argument
1374 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_signature_82599()
1383 ixgbe_fdir_enable_82599(hw, fdirctrl); in ixgbe_init_fdir_signature_82599()
1389 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1390 * @hw: pointer to hardware structure
1393 * @cloud_mode: true - cloud mode, false - other mode
1395 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl, in ixgbe_init_fdir_perfect_82599() argument
1406 * Move the flexible bytes to use the ethertype - shift 6 words in ixgbe_init_fdir_perfect_82599()
1422 ixgbe_fdir_enable_82599(hw, fdirctrl); in ixgbe_init_fdir_perfect_82599()
1428 * ixgbe_set_fdir_drop_queue_82599 - Set Flow Director drop queue
1429 * @hw: pointer to hardware structure
1432 void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue) in ixgbe_set_fdir_drop_queue_82599() argument
1438 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL); in ixgbe_set_fdir_drop_queue_82599()
1443 if ((hw->mac.type == ixgbe_mac_X550) || in ixgbe_set_fdir_drop_queue_82599()
1444 (hw->mac.type == ixgbe_mac_X550EM_x) || in ixgbe_set_fdir_drop_queue_82599()
1445 (hw->mac.type == ixgbe_mac_X550EM_a)) in ixgbe_set_fdir_drop_queue_82599()
1448 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_set_fdir_drop_queue_82599()
1449 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) | in ixgbe_set_fdir_drop_queue_82599()
1451 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_fdir_drop_queue_82599()
1452 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_set_fdir_drop_queue_82599()
1453 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) & in ixgbe_set_fdir_drop_queue_82599()
1455 IXGBE_WRITE_FLUSH(hw); in ixgbe_set_fdir_drop_queue_82599()
1458 ixgbe_fdir_enable_82599(hw, fdirctrl); in ixgbe_set_fdir_drop_queue_82599()
1476 sig_hash ^= lo_hash_dword << (16 - n); \
1482 sig_hash ^= hi_hash_dword << (16 - n); \
1486 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1553 * ixgbe_fdir_add_signature_filter_82599 - Adds a signature hash filter
1554 * @hw: pointer to hardware structure
1562 void ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_add_signature_filter_82599() argument
1581 (IXGBE_ATR_L4TYPE_TUNNEL_MASK - 1); in ixgbe_fdir_add_signature_filter_82599()
1604 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits in ixgbe_fdir_add_signature_filter_82599()
1605 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH. in ixgbe_fdir_add_signature_filter_82599()
1609 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd); in ixgbe_fdir_add_signature_filter_82599()
1626 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1647 input->dword_stream[i] &= input_mask->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1650 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]); in ixgbe_atr_compute_perfect_hash_82599()
1654 hi_dword ^= input->dword_stream[i]; in ixgbe_atr_compute_perfect_hash_82599()
1681 input->formatted.bkt_hash = bucket_hash & 0x1FFF; in ixgbe_atr_compute_perfect_hash_82599()
1685 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1695 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port); in ixgbe_get_fdirtcpm_82599()
1697 mask |= (u32)IXGBE_NTOHS(input_mask->formatted.src_port); in ixgbe_get_fdirtcpm_82599()
1706 * that are either all or in part big-endian. As a result on big-endian
1707 * systems we will end up byte swapping the value to little-endian before
1709 * big-endian format.
1721 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw, in ixgbe_fdir_set_input_mask_82599() argument
1742 if (input_mask->formatted.bkt_hash) in ixgbe_fdir_set_input_mask_82599()
1746 switch (input_mask->formatted.vm_pool & 0x7F) { in ixgbe_fdir_set_input_mask_82599()
1756 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) { in ixgbe_fdir_set_input_mask_82599()
1759 if (input_mask->formatted.dst_port || in ixgbe_fdir_set_input_mask_82599()
1760 input_mask->formatted.src_port) { in ixgbe_fdir_set_input_mask_82599()
1771 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) { in ixgbe_fdir_set_input_mask_82599()
1794 switch (input_mask->formatted.flex_bytes & 0xFFFF) { in ixgbe_fdir_set_input_mask_82599()
1811 switch (input_mask->formatted.inner_mac[0] & 0xFF) { in ixgbe_fdir_set_input_mask_82599()
1822 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) { in ixgbe_fdir_set_input_mask_82599()
1837 switch (input_mask->formatted.tunnel_type & 0xFFFF) { in ixgbe_fdir_set_input_mask_82599()
1847 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m); in ixgbe_fdir_set_input_mask_82599()
1853 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1854 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1855 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1856 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1857 switch (hw->mac.type) { in ixgbe_fdir_set_input_mask_82599()
1861 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1868 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */ in ixgbe_fdir_set_input_mask_82599()
1869 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm); in ixgbe_fdir_set_input_mask_82599()
1877 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1878 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1880 switch (hw->mac.type) { in ixgbe_fdir_set_input_mask_82599()
1884 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm); in ixgbe_fdir_set_input_mask_82599()
1890 /* store source and destination IP masks (big-enian) */ in ixgbe_fdir_set_input_mask_82599()
1891 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M, in ixgbe_fdir_set_input_mask_82599()
1892 ~input_mask->formatted.src_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1893 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M, in ixgbe_fdir_set_input_mask_82599()
1894 ~input_mask->formatted.dst_ip[0]); in ixgbe_fdir_set_input_mask_82599()
1895 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, 0xFFFFFFFF); in ixgbe_fdir_set_input_mask_82599()
1900 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_write_perfect_filter_82599() argument
1913 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), in ixgbe_fdir_write_perfect_filter_82599()
1914 input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1915 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), in ixgbe_fdir_write_perfect_filter_82599()
1916 input->formatted.src_ip[1]); in ixgbe_fdir_write_perfect_filter_82599()
1917 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), in ixgbe_fdir_write_perfect_filter_82599()
1918 input->formatted.src_ip[2]); in ixgbe_fdir_write_perfect_filter_82599()
1920 /* record the source address (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1921 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, in ixgbe_fdir_write_perfect_filter_82599()
1922 input->formatted.src_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1925 * (big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1926 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, in ixgbe_fdir_write_perfect_filter_82599()
1927 input->formatted.dst_ip[0]); in ixgbe_fdir_write_perfect_filter_82599()
1929 /* record source and destination port (little-endian)*/ in ixgbe_fdir_write_perfect_filter_82599()
1930 fdirport = IXGBE_NTOHS(input->formatted.dst_port); in ixgbe_fdir_write_perfect_filter_82599()
1932 fdirport |= (u32)IXGBE_NTOHS(input->formatted.src_port); in ixgbe_fdir_write_perfect_filter_82599()
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport); in ixgbe_fdir_write_perfect_filter_82599()
1936 /* record VLAN (little-endian) and flex_bytes(big-endian) */ in ixgbe_fdir_write_perfect_filter_82599()
1937 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes); in ixgbe_fdir_write_perfect_filter_82599()
1939 fdirvlan |= (u32)IXGBE_NTOHS(input->formatted.vlan_id); in ixgbe_fdir_write_perfect_filter_82599()
1940 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan); in ixgbe_fdir_write_perfect_filter_82599()
1943 if (input->formatted.tunnel_type != 0) in ixgbe_fdir_write_perfect_filter_82599()
1946 addr_low = ((u32)input->formatted.inner_mac[0] | in ixgbe_fdir_write_perfect_filter_82599()
1947 ((u32)input->formatted.inner_mac[1] << 8) | in ixgbe_fdir_write_perfect_filter_82599()
1948 ((u32)input->formatted.inner_mac[2] << 16) | in ixgbe_fdir_write_perfect_filter_82599()
1949 ((u32)input->formatted.inner_mac[3] << 24)); in ixgbe_fdir_write_perfect_filter_82599()
1950 addr_high = ((u32)input->formatted.inner_mac[4] | in ixgbe_fdir_write_perfect_filter_82599()
1951 ((u32)input->formatted.inner_mac[5] << 8)); in ixgbe_fdir_write_perfect_filter_82599()
1953 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low); in ixgbe_fdir_write_perfect_filter_82599()
1954 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type); in ixgbe_fdir_write_perfect_filter_82599()
1955 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni); in ixgbe_fdir_write_perfect_filter_82599()
1959 fdirhash = input->formatted.bkt_hash; in ixgbe_fdir_write_perfect_filter_82599()
1961 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_write_perfect_filter_82599()
1967 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_write_perfect_filter_82599()
1974 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK) in ixgbe_fdir_write_perfect_filter_82599()
1976 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1978 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT; in ixgbe_fdir_write_perfect_filter_82599()
1980 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd); in ixgbe_fdir_write_perfect_filter_82599()
1981 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_fdir_write_perfect_filter_82599()
1990 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_erase_perfect_filter_82599() argument
1999 fdirhash = input->formatted.bkt_hash; in ixgbe_fdir_erase_perfect_filter_82599()
2001 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_erase_perfect_filter_82599()
2003 /* flush hash to HW */ in ixgbe_fdir_erase_perfect_filter_82599()
2004 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_erase_perfect_filter_82599()
2007 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT); in ixgbe_fdir_erase_perfect_filter_82599()
2009 err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd); in ixgbe_fdir_erase_perfect_filter_82599()
2017 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash); in ixgbe_fdir_erase_perfect_filter_82599()
2018 IXGBE_WRITE_FLUSH(hw); in ixgbe_fdir_erase_perfect_filter_82599()
2019 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, in ixgbe_fdir_erase_perfect_filter_82599()
2027 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2028 * @hw: pointer to hardware structure
2038 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw, in ixgbe_fdir_add_perfect_filter_82599() argument
2052 switch (input->formatted.flow_type) { in ixgbe_fdir_add_perfect_filter_82599()
2055 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK; in ixgbe_fdir_add_perfect_filter_82599()
2056 if (input->formatted.dst_port || input->formatted.src_port) { in ixgbe_fdir_add_perfect_filter_82599()
2063 if (input->formatted.dst_port || input->formatted.src_port) { in ixgbe_fdir_add_perfect_filter_82599()
2067 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | in ixgbe_fdir_add_perfect_filter_82599()
2074 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK | in ixgbe_fdir_add_perfect_filter_82599()
2082 /* program input mask into the HW */ in ixgbe_fdir_add_perfect_filter_82599()
2083 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode); in ixgbe_fdir_add_perfect_filter_82599()
2091 return ixgbe_fdir_write_perfect_filter_82599(hw, input, in ixgbe_fdir_add_perfect_filter_82599()
2096 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2097 * @hw: pointer to hardware structure
2103 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val) in ixgbe_read_analog_reg8_82599() argument
2109 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | in ixgbe_read_analog_reg8_82599()
2111 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_analog_reg8_82599()
2113 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); in ixgbe_read_analog_reg8_82599()
2120 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2121 * @hw: pointer to hardware structure
2127 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val) in ixgbe_write_analog_reg8_82599() argument
2134 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); in ixgbe_write_analog_reg8_82599()
2135 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_analog_reg8_82599()
2142 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2143 * @hw: pointer to hardware structure
2147 * Then performs revision-specific operations, if any.
2149 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw) in ixgbe_start_hw_82599() argument
2155 ret_val = ixgbe_start_hw_generic(hw); in ixgbe_start_hw_82599()
2159 ixgbe_start_hw_gen2(hw); in ixgbe_start_hw_82599()
2162 hw->mac.autotry_restart = true; in ixgbe_start_hw_82599()
2165 ret_val = ixgbe_verify_fw_version_82599(hw); in ixgbe_start_hw_82599()
2171 * ixgbe_identify_phy_82599 - Get physical layer module
2172 * @hw: pointer to hardware structure
2175 * If PHY already detected, maintains current PHY type in hw struct,
2178 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw) in ixgbe_identify_phy_82599() argument
2184 /* Detect PHY if not unknown - returns success if already detected. */ in ixgbe_identify_phy_82599()
2185 status = ixgbe_identify_phy_generic(hw); in ixgbe_identify_phy_82599()
2187 /* 82599 10GBASE-T requires an external PHY */ in ixgbe_identify_phy_82599()
2188 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) in ixgbe_identify_phy_82599()
2191 status = ixgbe_identify_module_generic(hw); in ixgbe_identify_phy_82599()
2195 if (hw->phy.type == ixgbe_phy_unknown) { in ixgbe_identify_phy_82599()
2196 hw->phy.type = ixgbe_phy_none; in ixgbe_identify_phy_82599()
2201 if (hw->phy.type == ixgbe_phy_sfp_unsupported) in ixgbe_identify_phy_82599()
2208 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2209 * @hw: pointer to hardware structure
2213 u64 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) in ixgbe_get_supported_physical_layer_82599() argument
2216 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_get_supported_physical_layer_82599()
2217 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_get_supported_physical_layer_82599()
2225 hw->phy.ops.identify(hw); in ixgbe_get_supported_physical_layer_82599()
2227 switch (hw->phy.type) { in ixgbe_get_supported_physical_layer_82599()
2230 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, in ixgbe_get_supported_physical_layer_82599()
2287 * test KR mode - we need to id KR mode correctly before SFP module. in ixgbe_get_supported_physical_layer_82599()
2289 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); in ixgbe_get_supported_physical_layer_82599()
2295 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2296 * @hw: pointer to hardware structure
2301 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval) in ixgbe_enable_rx_dma_82599() argument
2313 hw->mac.ops.disable_sec_rx_path(hw); in ixgbe_enable_rx_dma_82599()
2316 ixgbe_enable_rx(hw); in ixgbe_enable_rx_dma_82599()
2318 ixgbe_disable_rx(hw); in ixgbe_enable_rx_dma_82599()
2320 hw->mac.ops.enable_sec_rx_path(hw); in ixgbe_enable_rx_dma_82599()
2326 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2327 * @hw: pointer to hardware structure
2335 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) in ixgbe_verify_fw_version_82599() argument
2344 if (hw->phy.media_type != ixgbe_media_type_fiber) { in ixgbe_verify_fw_version_82599()
2350 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { in ixgbe_verify_fw_version_82599()
2360 if (hw->eeprom.ops.read(hw, (fw_offset + in ixgbe_verify_fw_version_82599()
2374 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + in ixgbe_verify_fw_version_82599()
2390 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2391 * @hw: pointer to hardware structure
2396 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) in ixgbe_verify_lesm_fw_enabled_82599() argument
2405 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); in ixgbe_verify_lesm_fw_enabled_82599()
2412 status = hw->eeprom.ops.read(hw, (fw_offset + in ixgbe_verify_lesm_fw_enabled_82599()
2421 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + in ixgbe_verify_lesm_fw_enabled_82599()
2434 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2437 * @hw: pointer to hardware structure
2444 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset, in ixgbe_read_eeprom_buffer_82599() argument
2447 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_buffer_82599()
2456 if ((eeprom->type == ixgbe_eeprom_spi) && in ixgbe_read_eeprom_buffer_82599()
2457 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR)) in ixgbe_read_eeprom_buffer_82599()
2458 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words, in ixgbe_read_eeprom_buffer_82599()
2461 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset, in ixgbe_read_eeprom_buffer_82599()
2469 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2472 * @hw: pointer to hardware structure
2478 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, in ixgbe_read_eeprom_82599() argument
2481 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_read_eeprom_82599()
2490 if ((eeprom->type == ixgbe_eeprom_spi) && in ixgbe_read_eeprom_82599()
2492 ret_val = ixgbe_read_eerd_generic(hw, offset, data); in ixgbe_read_eeprom_82599()
2494 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); in ixgbe_read_eeprom_82599()
2500 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2502 * @hw: pointer to hardware structure
2507 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) in ixgbe_reset_pipeline_82599() argument
2514 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); in ixgbe_reset_pipeline_82599()
2517 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); in ixgbe_reset_pipeline_82599()
2518 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_pipeline_82599()
2521 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); in ixgbe_reset_pipeline_82599()
2524 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, in ixgbe_reset_pipeline_82599()
2529 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); in ixgbe_reset_pipeline_82599()
2544 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); in ixgbe_reset_pipeline_82599()
2545 IXGBE_WRITE_FLUSH(hw); in ixgbe_reset_pipeline_82599()
2551 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2552 * @hw: pointer to hardware structure
2560 static s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_read_i2c_byte_82599() argument
2565 s32 timeout = 200; in ixgbe_read_i2c_byte_82599() local
2569 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2571 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2573 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_read_i2c_byte_82599()
2574 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_i2c_byte_82599()
2576 while (timeout) { in ixgbe_read_i2c_byte_82599()
2577 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2582 timeout--; in ixgbe_read_i2c_byte_82599()
2585 if (!timeout) { in ixgbe_read_i2c_byte_82599()
2587 " acquiring I2C bus timeout.\n"); in ixgbe_read_i2c_byte_82599()
2593 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); in ixgbe_read_i2c_byte_82599()
2597 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_read_i2c_byte_82599()
2599 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_read_i2c_byte_82599()
2601 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_read_i2c_byte_82599()
2602 IXGBE_WRITE_FLUSH(hw); in ixgbe_read_i2c_byte_82599()
2609 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2610 * @hw: pointer to hardware structure
2618 static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset, in ixgbe_write_i2c_byte_82599() argument
2623 s32 timeout = 200; in ixgbe_write_i2c_byte_82599() local
2627 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2629 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2631 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_write_i2c_byte_82599()
2632 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_i2c_byte_82599()
2634 while (timeout) { in ixgbe_write_i2c_byte_82599()
2635 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2640 timeout--; in ixgbe_write_i2c_byte_82599()
2643 if (!timeout) { in ixgbe_write_i2c_byte_82599()
2645 " acquiring I2C bus timeout.\n"); in ixgbe_write_i2c_byte_82599()
2651 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); in ixgbe_write_i2c_byte_82599()
2655 if (hw->phy.qsfp_shared_i2c_bus == true) { in ixgbe_write_i2c_byte_82599()
2657 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); in ixgbe_write_i2c_byte_82599()
2659 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); in ixgbe_write_i2c_byte_82599()
2660 IXGBE_WRITE_FLUSH(hw); in ixgbe_write_i2c_byte_82599()