48 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
51 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
52 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
54 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
57 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
60 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
63 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
64 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
65 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
66 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
68 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
80 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)  in ixgbe_set_pcie_completion_timeout()  argument
82 	u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);  in ixgbe_set_pcie_completion_timeout()
103 	pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);  in ixgbe_set_pcie_completion_timeout()
105 	IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);  in ixgbe_set_pcie_completion_timeout()
109 	IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);  in ixgbe_set_pcie_completion_timeout()
119 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)  in ixgbe_init_ops_82598()  argument
121 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_init_ops_82598()
122 	struct ixgbe_phy_info *phy = &hw->phy;  in ixgbe_init_ops_82598()
127 	ret_val = ixgbe_init_phy_ops_generic(hw);  in ixgbe_init_ops_82598()
128 	ret_val = ixgbe_init_ops_generic(hw);  in ixgbe_init_ops_82598()
161 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);  in ixgbe_init_ops_82598()
191 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)  in ixgbe_init_phy_ops_82598()  argument
193 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_init_phy_ops_82598()
194 	struct ixgbe_phy_info *phy = &hw->phy;  in ixgbe_init_phy_ops_82598()
201 	phy->ops.identify(hw);  in ixgbe_init_phy_ops_82598()
204 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {  in ixgbe_init_phy_ops_82598()
210 	switch (hw->phy.type) {  in ixgbe_init_phy_ops_82598()
221 		ret_val = phy->ops.identify_sfp(hw);  in ixgbe_init_phy_ops_82598()
224 		else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {  in ixgbe_init_phy_ops_82598()
230 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,  in ixgbe_init_phy_ops_82598()
254 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)  in ixgbe_start_hw_82598()  argument
262 	ret_val = ixgbe_start_hw_generic(hw);  in ixgbe_start_hw_82598()
267 	for (i = 0; ((i < hw->mac.max_tx_queues) &&  in ixgbe_start_hw_82598()
269 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));  in ixgbe_start_hw_82598()
271 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);  in ixgbe_start_hw_82598()
274 	for (i = 0; ((i < hw->mac.max_rx_queues) &&  in ixgbe_start_hw_82598()
276 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));  in ixgbe_start_hw_82598()
279 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);  in ixgbe_start_hw_82598()
283 	ixgbe_set_pcie_completion_timeout(hw);  in ixgbe_start_hw_82598()
296 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,  in ixgbe_get_link_capabilities_82598()  argument
310 	if (hw->mac.orig_link_settings_stored)  in ixgbe_get_link_capabilities_82598()
311 		autoc = hw->mac.orig_autoc;  in ixgbe_get_link_capabilities_82598()
313 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_get_link_capabilities_82598()
355 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)  in ixgbe_get_media_type_82598()  argument
362 	switch (hw->phy.type) {  in ixgbe_get_media_type_82598()
372 	switch (hw->device_id) {  in ixgbe_get_media_type_82598()
408 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)  in ixgbe_fc_enable_82598()  argument
422 	if (!hw->fc.pause_time) {  in ixgbe_fc_enable_82598()
429 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
430 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
431 			if (!hw->fc.low_water[i] ||  in ixgbe_fc_enable_82598()
432 			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
445 	hw->mac.ops.check_link(hw, &link_speed, &link_up, false);  in ixgbe_fc_enable_82598()
447 		switch (hw->fc.requested_mode) {  in ixgbe_fc_enable_82598()
449 			hw->fc.requested_mode = ixgbe_fc_tx_pause;  in ixgbe_fc_enable_82598()
452 			hw->fc.requested_mode = ixgbe_fc_none;  in ixgbe_fc_enable_82598()
461 	ixgbe_fc_autoneg(hw);  in ixgbe_fc_enable_82598()
464 	fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);  in ixgbe_fc_enable_82598()
467 	rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);  in ixgbe_fc_enable_82598()
480 	switch (hw->fc.current_mode) {  in ixgbe_fc_enable_82598()
519 	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);  in ixgbe_fc_enable_82598()
520 	IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);  in ixgbe_fc_enable_82598()
524 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
525 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
526 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_fc_enable_82598()
527 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_fc_enable_82598()
528 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);  in ixgbe_fc_enable_82598()
529 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);  in ixgbe_fc_enable_82598()
531 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);  in ixgbe_fc_enable_82598()
532 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);  in ixgbe_fc_enable_82598()
538 	reg = hw->fc.pause_time * 0x00010001;  in ixgbe_fc_enable_82598()
540 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);  in ixgbe_fc_enable_82598()
543 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);  in ixgbe_fc_enable_82598()
557 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_start_mac_link_82598()  argument
568 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_start_mac_link_82598()
570 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);  in ixgbe_start_mac_link_82598()
580 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_start_mac_link_82598()
605 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)  in ixgbe_validate_link_ready()  argument
610 	if (hw->device_id != IXGBE_DEV_ID_82598AT2)  in ixgbe_validate_link_ready()
615 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,  in ixgbe_validate_link_ready()
642 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_check_mac_link_82598()  argument
658 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_check_mac_link_82598()
659 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);  in ixgbe_check_mac_link_82598()
660 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);  in ixgbe_check_mac_link_82598()
661 		hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,  in ixgbe_check_mac_link_82598()
664 			for (i = 0; i < hw->mac.max_link_up_time; i++) {  in ixgbe_check_mac_link_82598()
673 				hw->phy.ops.read_reg(hw, 0xC79F,  in ixgbe_check_mac_link_82598()
676 				hw->phy.ops.read_reg(hw, 0xC00C,  in ixgbe_check_mac_link_82598()
691 	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_check_mac_link_82598()
693 		for (i = 0; i < hw->mac.max_link_up_time; i++) {  in ixgbe_check_mac_link_82598()
701 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);  in ixgbe_check_mac_link_82598()
715 	if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&  in ixgbe_check_mac_link_82598()
716 	    (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))  in ixgbe_check_mac_link_82598()
731 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,  in ixgbe_setup_mac_link_82598()  argument
738 	u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_setup_mac_link_82598()
745 	ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);  in ixgbe_setup_mac_link_82598()
760 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);  in ixgbe_setup_mac_link_82598()
769 		status = ixgbe_start_mac_link_82598(hw,  in ixgbe_setup_mac_link_82598()
785 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,  in ixgbe_setup_copper_link_82598()  argument
794 	status = hw->phy.ops.setup_link_speed(hw, speed,  in ixgbe_setup_copper_link_82598()
797 	ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);  in ixgbe_setup_copper_link_82598()
810 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)  in ixgbe_reset_hw_82598()  argument
823 	status = hw->mac.ops.stop_adapter(hw);  in ixgbe_reset_hw_82598()
832 	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);  in ixgbe_reset_hw_82598()
835 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
838 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
841 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
844 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
847 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
850 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
853 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
856 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
861 	if (hw->phy.reset_disable == false) {  in ixgbe_reset_hw_82598()
865 		phy_status = hw->phy.ops.init(hw);  in ixgbe_reset_hw_82598()
871 		hw->phy.ops.reset(hw);  in ixgbe_reset_hw_82598()
879 	ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;  in ixgbe_reset_hw_82598()
880 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);  in ixgbe_reset_hw_82598()
881 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_reset_hw_82598()
886 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);  in ixgbe_reset_hw_82598()
902 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {  in ixgbe_reset_hw_82598()
903 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;  in ixgbe_reset_hw_82598()
907 	gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);  in ixgbe_reset_hw_82598()
909 	IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);  in ixgbe_reset_hw_82598()
916 	autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_reset_hw_82598()
917 	if (hw->mac.orig_link_settings_stored == false) {  in ixgbe_reset_hw_82598()
918 		hw->mac.orig_autoc = autoc;  in ixgbe_reset_hw_82598()
919 		hw->mac.orig_link_settings_stored = true;  in ixgbe_reset_hw_82598()
920 	} else if (autoc != hw->mac.orig_autoc) {  in ixgbe_reset_hw_82598()
921 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);  in ixgbe_reset_hw_82598()
925 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);  in ixgbe_reset_hw_82598()
931 	hw->mac.ops.init_rx_addrs(hw);  in ixgbe_reset_hw_82598()
946 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_set_vmdq_82598()  argument
949 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_set_vmdq_82598()
959 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));  in ixgbe_set_vmdq_82598()
962 	IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);  in ixgbe_set_vmdq_82598()
972 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)  in ixgbe_clear_vmdq_82598()  argument
975 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_clear_vmdq_82598()
985 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));  in ixgbe_clear_vmdq_82598()
988 		IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);  in ixgbe_clear_vmdq_82598()
1004 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,  in ixgbe_set_vfta_82598()  argument
1027 	bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));  in ixgbe_set_vfta_82598()
1030 	IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);  in ixgbe_set_vfta_82598()
1035 	bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));  in ixgbe_set_vfta_82598()
1042 	IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);  in ixgbe_set_vfta_82598()
1053 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)  in ixgbe_clear_vfta_82598()  argument
1060 	for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
1061 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);  in ixgbe_clear_vfta_82598()
1064 		for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
1065 			IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),  in ixgbe_clear_vfta_82598()
1079 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)  in ixgbe_read_analog_reg8_82598()  argument
1085 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,  in ixgbe_read_analog_reg8_82598()
1087 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_read_analog_reg8_82598()
1089 	atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);  in ixgbe_read_analog_reg8_82598()
1103 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)  in ixgbe_write_analog_reg8_82598()  argument
1110 	IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);  in ixgbe_write_analog_reg8_82598()
1111 	IXGBE_WRITE_FLUSH(hw);  in ixgbe_write_analog_reg8_82598()
1126 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,  in ixgbe_read_i2c_phy_82598()  argument
1138 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)  in ixgbe_read_i2c_phy_82598()
1143 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)  in ixgbe_read_i2c_phy_82598()
1146 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_read_i2c_phy_82598()
1154 		hw->phy.ops.write_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1161 			hw->phy.ops.read_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1178 		hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,  in ixgbe_read_i2c_phy_82598()
1187 	hw->mac.ops.release_swfw_sync(hw, gssr);  in ixgbe_read_i2c_phy_82598()
1199 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,  in ixgbe_read_i2c_eeprom_82598()  argument
1202 	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,  in ixgbe_read_i2c_eeprom_82598()
1214 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,  in ixgbe_read_i2c_sff8472_82598()  argument
1217 	return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,  in ixgbe_read_i2c_sff8472_82598()
1227 u64 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)  in ixgbe_get_supported_physical_layer_82598()  argument
1230 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);  in ixgbe_get_supported_physical_layer_82598()
1237 	hw->phy.ops.identify(hw);  in ixgbe_get_supported_physical_layer_82598()
1241 	switch (hw->phy.type) {  in ixgbe_get_supported_physical_layer_82598()
1244 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,  in ixgbe_get_supported_physical_layer_82598()
1284 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_get_supported_physical_layer_82598()
1285 		hw->phy.ops.identify_sfp(hw);  in ixgbe_get_supported_physical_layer_82598()
1287 		switch (hw->phy.sfp_type) {  in ixgbe_get_supported_physical_layer_82598()
1303 	switch (hw->device_id) {  in ixgbe_get_supported_physical_layer_82598()
1331 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)  in ixgbe_set_lan_id_multi_port_pcie_82598()  argument
1333 	struct ixgbe_bus_info *bus = &hw->bus;  in ixgbe_set_lan_id_multi_port_pcie_82598()
1339 	ixgbe_set_lan_id_multi_port_pcie(hw);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1342 	hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1345 		hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1362 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)  in ixgbe_enable_relaxed_ordering_82598()  argument
1370 	for (i = 0; ((i < hw->mac.max_tx_queues) &&  in ixgbe_enable_relaxed_ordering_82598()
1372 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));  in ixgbe_enable_relaxed_ordering_82598()
1374 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);  in ixgbe_enable_relaxed_ordering_82598()
1377 	for (i = 0; ((i < hw->mac.max_rx_queues) &&  in ixgbe_enable_relaxed_ordering_82598()
1379 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));  in ixgbe_enable_relaxed_ordering_82598()
1382 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);  in ixgbe_enable_relaxed_ordering_82598()
1394 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,  in ixgbe_set_rxpba_82598()  argument
1410 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);  in ixgbe_set_rxpba_82598()
1418 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);  in ixgbe_set_rxpba_82598()
1424 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);  in ixgbe_set_rxpba_82598()
1434 s32 ixgbe_enable_rx_dma_82598(struct ixgbe_hw *hw, u32 regval)  in ixgbe_enable_rx_dma_82598()  argument
1438 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);  in ixgbe_enable_rx_dma_82598()