2   SPDX-License-Identifier: BSD-3-Clause
4   Copyright (c) 2001-2020, Intel Corporation
71  * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
76  * than the 10ms recommended by the pci-e spec.  To address this we need to
113  * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
121 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_init_ops_82598()
122 	struct ixgbe_phy_info *phy = &hw->phy;  in ixgbe_init_ops_82598()
131 	phy->ops.init = ixgbe_init_phy_ops_82598;  in ixgbe_init_ops_82598()
134 	mac->ops.start_hw = ixgbe_start_hw_82598;  in ixgbe_init_ops_82598()
135 	mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_82598;  in ixgbe_init_ops_82598()
136 	mac->ops.reset_hw = ixgbe_reset_hw_82598;  in ixgbe_init_ops_82598()
137 	mac->ops.get_media_type = ixgbe_get_media_type_82598;  in ixgbe_init_ops_82598()
138 	mac->ops.get_supported_physical_layer =  in ixgbe_init_ops_82598()
140 	mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82598;  in ixgbe_init_ops_82598()
141 	mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82598;  in ixgbe_init_ops_82598()
142 	mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie_82598;  in ixgbe_init_ops_82598()
143 	mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82598;  in ixgbe_init_ops_82598()
146 	mac->ops.set_vmdq = ixgbe_set_vmdq_82598;  in ixgbe_init_ops_82598()
147 	mac->ops.clear_vmdq = ixgbe_clear_vmdq_82598;  in ixgbe_init_ops_82598()
148 	mac->ops.set_vfta = ixgbe_set_vfta_82598;  in ixgbe_init_ops_82598()
149 	mac->ops.set_vlvf = NULL;  in ixgbe_init_ops_82598()
150 	mac->ops.clear_vfta = ixgbe_clear_vfta_82598;  in ixgbe_init_ops_82598()
153 	mac->ops.fc_enable = ixgbe_fc_enable_82598;  in ixgbe_init_ops_82598()
155 	mac->mcft_size		= IXGBE_82598_MC_TBL_SIZE;  in ixgbe_init_ops_82598()
156 	mac->vft_size		= IXGBE_82598_VFT_TBL_SIZE;  in ixgbe_init_ops_82598()
157 	mac->num_rar_entries	= IXGBE_82598_RAR_ENTRIES;  in ixgbe_init_ops_82598()
158 	mac->rx_pb_size		= IXGBE_82598_RX_PB_SIZE;  in ixgbe_init_ops_82598()
159 	mac->max_rx_queues	= IXGBE_82598_MAX_RX_QUEUES;  in ixgbe_init_ops_82598()
160 	mac->max_tx_queues	= IXGBE_82598_MAX_TX_QUEUES;  in ixgbe_init_ops_82598()
161 	mac->max_msix_vectors	= ixgbe_get_pcie_msix_count_generic(hw);  in ixgbe_init_ops_82598()
164 	phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_82598;  in ixgbe_init_ops_82598()
165 	phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_82598;  in ixgbe_init_ops_82598()
168 	mac->ops.check_link = ixgbe_check_mac_link_82598;  in ixgbe_init_ops_82598()
169 	mac->ops.setup_link = ixgbe_setup_mac_link_82598;  in ixgbe_init_ops_82598()
170 	mac->ops.flap_tx_laser = NULL;  in ixgbe_init_ops_82598()
171 	mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82598;  in ixgbe_init_ops_82598()
172 	mac->ops.setup_rxpba = ixgbe_set_rxpba_82598;  in ixgbe_init_ops_82598()
175 	mac->ops.set_fw_drv_ver = NULL;  in ixgbe_init_ops_82598()
177 	mac->ops.get_rtrup2tc = NULL;  in ixgbe_init_ops_82598()
183  * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
193 	struct ixgbe_mac_info *mac = &hw->mac;  in ixgbe_init_phy_ops_82598()
194 	struct ixgbe_phy_info *phy = &hw->phy;  in ixgbe_init_phy_ops_82598()
201 	phy->ops.identify(hw);  in ixgbe_init_phy_ops_82598()
204 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {  in ixgbe_init_phy_ops_82598()
205 		mac->ops.setup_link = ixgbe_setup_copper_link_82598;  in ixgbe_init_phy_ops_82598()
206 		mac->ops.get_link_capabilities =  in ixgbe_init_phy_ops_82598()
210 	switch (hw->phy.type) {  in ixgbe_init_phy_ops_82598()
212 		phy->ops.setup_link = ixgbe_setup_phy_link_tnx;  in ixgbe_init_phy_ops_82598()
213 		phy->ops.check_link = ixgbe_check_phy_link_tnx;  in ixgbe_init_phy_ops_82598()
214 		phy->ops.get_firmware_version =  in ixgbe_init_phy_ops_82598()
218 		phy->ops.reset = ixgbe_reset_phy_nl;  in ixgbe_init_phy_ops_82598()
221 		ret_val = phy->ops.identify_sfp(hw);  in ixgbe_init_phy_ops_82598()
224 		else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {  in ixgbe_init_phy_ops_82598()
247  * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
267 	for (i = 0; ((i < hw->mac.max_tx_queues) &&  in ixgbe_start_hw_82598()
274 	for (i = 0; ((i < hw->mac.max_rx_queues) &&  in ixgbe_start_hw_82598()
289  * ixgbe_get_link_capabilities_82598 - Determines link capabilities
292  * @autoneg: boolean auto-negotiation value
310 	if (hw->mac.orig_link_settings_stored)  in ixgbe_get_link_capabilities_82598()
311 		autoc = hw->mac.orig_autoc;  in ixgbe_get_link_capabilities_82598()
350  * ixgbe_get_media_type_82598 - Determines media type
362 	switch (hw->phy.type) {  in ixgbe_get_media_type_82598()
372 	switch (hw->device_id) {  in ixgbe_get_media_type_82598()
403  * ixgbe_fc_enable_82598 - Enable flow control
422 	if (!hw->fc.pause_time) {  in ixgbe_fc_enable_82598()
429 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
430 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
431 			if (!hw->fc.low_water[i] ||  in ixgbe_fc_enable_82598()
432 			    hw->fc.low_water[i] >= hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
445 	hw->mac.ops.check_link(hw, &link_speed, &link_up, false);  in ixgbe_fc_enable_82598()
447 		switch (hw->fc.requested_mode) {  in ixgbe_fc_enable_82598()
449 			hw->fc.requested_mode = ixgbe_fc_tx_pause;  in ixgbe_fc_enable_82598()
452 			hw->fc.requested_mode = ixgbe_fc_none;  in ixgbe_fc_enable_82598()
480 	switch (hw->fc.current_mode) {  in ixgbe_fc_enable_82598()
524 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&  in ixgbe_fc_enable_82598()
525 		    hw->fc.high_water[i]) {  in ixgbe_fc_enable_82598()
526 			fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_fc_enable_82598()
527 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_fc_enable_82598()
538 	reg = hw->fc.pause_time * 0x00010001;  in ixgbe_fc_enable_82598()
543 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);  in ixgbe_fc_enable_82598()
550  * ixgbe_start_mac_link_82598 - Configures MAC link settings
599  * ixgbe_validate_link_ready - Function looks for phy link
610 	if (hw->device_id != IXGBE_DEV_ID_82598AT2)  in ixgbe_validate_link_ready()
615 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,  in ixgbe_validate_link_ready()
634  * ixgbe_check_mac_link_82598 - Get link/speed status
658 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_check_mac_link_82598()
659 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);  in ixgbe_check_mac_link_82598()
660 		hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);  in ixgbe_check_mac_link_82598()
661 		hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,  in ixgbe_check_mac_link_82598()
664 			for (i = 0; i < hw->mac.max_link_up_time; i++) {  in ixgbe_check_mac_link_82598()
673 				hw->phy.ops.read_reg(hw, 0xC79F,  in ixgbe_check_mac_link_82598()
676 				hw->phy.ops.read_reg(hw, 0xC00C,  in ixgbe_check_mac_link_82598()
693 		for (i = 0; i < hw->mac.max_link_up_time; i++) {  in ixgbe_check_mac_link_82598()
715 	if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&  in ixgbe_check_mac_link_82598()
724  * ixgbe_setup_mac_link_82598 - Set MAC link speed
778  * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
794 	status = hw->phy.ops.setup_link_speed(hw, speed,  in ixgbe_setup_copper_link_82598()
803  * ixgbe_reset_hw_82598 - Performs hardware reset
823 	status = hw->mac.ops.stop_adapter(hw);  in ixgbe_reset_hw_82598()
832 	hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);  in ixgbe_reset_hw_82598()
835 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
838 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,  in ixgbe_reset_hw_82598()
841 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
844 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,  in ixgbe_reset_hw_82598()
847 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
850 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,  in ixgbe_reset_hw_82598()
853 		hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
856 		hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,  in ixgbe_reset_hw_82598()
861 	if (hw->phy.reset_disable == false) {  in ixgbe_reset_hw_82598()
865 		phy_status = hw->phy.ops.init(hw);  in ixgbe_reset_hw_82598()
871 		hw->phy.ops.reset(hw);  in ixgbe_reset_hw_82598()
883 	/* Poll for reset bit to self-clear indicating reset is complete */  in ixgbe_reset_hw_82598()
902 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {  in ixgbe_reset_hw_82598()
903 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;  in ixgbe_reset_hw_82598()
917 	if (hw->mac.orig_link_settings_stored == false) {  in ixgbe_reset_hw_82598()
918 		hw->mac.orig_autoc = autoc;  in ixgbe_reset_hw_82598()
919 		hw->mac.orig_link_settings_stored = true;  in ixgbe_reset_hw_82598()
920 	} else if (autoc != hw->mac.orig_autoc) {  in ixgbe_reset_hw_82598()
921 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);  in ixgbe_reset_hw_82598()
925 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);  in ixgbe_reset_hw_82598()
931 	hw->mac.ops.init_rx_addrs(hw);  in ixgbe_reset_hw_82598()
941  * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
949 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_set_vmdq_82598()
967  * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
975 	u32 rar_entries = hw->mac.num_rar_entries;  in ixgbe_clear_vmdq_82598()
995  * ixgbe_set_vfta_82598 - Set VLAN filter table
1000  * @vlvf_bypass: boolean flag - unused
1019 	/* Determine 32-bit word position in array */  in ixgbe_set_vfta_82598()
1048  * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1060 	for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
1064 		for (offset = 0; offset < hw->mac.vft_size; offset++)  in ixgbe_clear_vfta_82598()
1072  * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1074  * @reg: analog register to read
1077  * Performs read operation to Atlas analog register specified.
1096  * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1101  * Performs write operation to Atlas analog register specified.
1118  * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
1143 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)  in ixgbe_read_i2c_phy_82598()
1146 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_read_i2c_phy_82598()
1154 		hw->phy.ops.write_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1161 			hw->phy.ops.read_reg_mdi(hw,  in ixgbe_read_i2c_phy_82598()
1172 			DEBUGOUT("EEPROM read did not pass.\n");  in ixgbe_read_i2c_phy_82598()
1178 		hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,  in ixgbe_read_i2c_phy_82598()
1187 	hw->mac.ops.release_swfw_sync(hw, gssr);  in ixgbe_read_i2c_phy_82598()
1192  * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1207  * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1212  * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1222  * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1237 	hw->phy.ops.identify(hw);  in ixgbe_get_supported_physical_layer_82598()
1240 	 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */  in ixgbe_get_supported_physical_layer_82598()
1241 	switch (hw->phy.type) {  in ixgbe_get_supported_physical_layer_82598()
1244 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,  in ixgbe_get_supported_physical_layer_82598()
1284 	if (hw->phy.type == ixgbe_phy_nl) {  in ixgbe_get_supported_physical_layer_82598()
1285 		hw->phy.ops.identify_sfp(hw);  in ixgbe_get_supported_physical_layer_82598()
1287 		switch (hw->phy.sfp_type) {  in ixgbe_get_supported_physical_layer_82598()
1303 	switch (hw->device_id) {  in ixgbe_get_supported_physical_layer_82598()
1324  * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1333 	struct ixgbe_bus_info *bus = &hw->bus;  in ixgbe_set_lan_id_multi_port_pcie_82598()
1342 	hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1345 		hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);  in ixgbe_set_lan_id_multi_port_pcie_82598()
1352 			bus->func = 0;  in ixgbe_set_lan_id_multi_port_pcie_82598()
1358  * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1370 	for (i = 0; ((i < hw->mac.max_tx_queues) &&  in ixgbe_enable_relaxed_ordering_82598()
1377 	for (i = 0; ((i < hw->mac.max_rx_queues) &&  in ixgbe_enable_relaxed_ordering_82598()
1388  * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1411 		/* Setup the last four at 48KB...don't re-init i */  in ixgbe_set_rxpba_82598()
1428  * ixgbe_enable_rx_dma_82598 - Enable the Rx DMA unit