Lines Matching +full:0 +full:x0a10
198 #define PCI_CFG_RETRY_TIMEOUT 0x41
200 #define PCI_VENDOR_INTEL 0x8086
201 #define PCI_PRODUCT_INTEL_WL_22500_1 0x2723 /* Wi-Fi 6 AX200 */
202 #define PCI_PRODUCT_INTEL_WL_22500_2 0x02f0 /* Wi-Fi 6 AX201 */
203 #define PCI_PRODUCT_INTEL_WL_22500_3 0xa0f0 /* Wi-Fi 6 AX201 */
204 #define PCI_PRODUCT_INTEL_WL_22500_4 0x34f0 /* Wi-Fi 6 AX201 */
205 #define PCI_PRODUCT_INTEL_WL_22500_5 0x06f0 /* Wi-Fi 6 AX201 */
206 #define PCI_PRODUCT_INTEL_WL_22500_6 0x43f0 /* Wi-Fi 6 AX201 */
207 #define PCI_PRODUCT_INTEL_WL_22500_7 0x3df0 /* Wi-Fi 6 AX201 */
208 #define PCI_PRODUCT_INTEL_WL_22500_8 0x4df0 /* Wi-Fi 6 AX201 */
209 #define PCI_PRODUCT_INTEL_WL_22500_9 0x2725 /* Wi-Fi 6 AX210 */
210 #define PCI_PRODUCT_INTEL_WL_22500_10 0x2726 /* Wi-Fi 6 AX211 */
211 #define PCI_PRODUCT_INTEL_WL_22500_11 0x51f0 /* Wi-Fi 6 AX211 */
212 #define PCI_PRODUCT_INTEL_WL_22500_12 0x7a70 /* Wi-Fi 6 AX211 */
213 #define PCI_PRODUCT_INTEL_WL_22500_13 0x7af0 /* Wi-Fi 6 AX211 */
214 #define PCI_PRODUCT_INTEL_WL_22500_14 0x7e40 /* Wi-Fi 6 AX210 */
215 #define PCI_PRODUCT_INTEL_WL_22500_15 0x7f70 /* Wi-Fi 6 AX211 */
216 #define PCI_PRODUCT_INTEL_WL_22500_16 0x54f0 /* Wi-Fi 6 AX211 */
217 #define PCI_PRODUCT_INTEL_WL_22500_17 0x51f1 /* Wi-Fi 6 AX211 */
296 #define IWX_RIDX_CCK 0
326 #if 0
376 #if 0
437 #if 0
456 #if 0
491 #if 0
543 #if 0
572 #if 0
586 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
589 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
592 #define DPRINTF(x) do { if (sc->sc_debug == IWX_DEBUG_ANY) { printf x; } } while (0)
594 #define DPRINTF(x) do { ; } while (0)
635 #define IEEE80211_HTOP0_SCO_SCN 0
636 #define IEEE80211_VHTOP0_CHAN_WIDTH_HT 0
639 #define IEEE80211_HT_RATESET_SISO 0
664 for (i = 0; i < sc->n_cmd_versions; i++) { in iwx_lookup_cmd_ver()
679 for (i = 0; i < sc->n_cmd_versions; i++) { in iwx_lookup_notif_ver()
699 return 0; in iwx_store_cscheme()
715 return 0; in iwx_ctxt_info_alloc_dma()
728 for (i = 0; i < dram->paging_cnt; i++) in iwx_ctxt_info_free_paging()
732 dram->paging_cnt = 0; in iwx_ctxt_info_free_paging()
739 int i = 0; in iwx_get_num_sections()
756 int i, ret, fw_cnt = 0; in iwx_init_fw_sec()
760 dram->lmac_cnt = iwx_get_num_sections(fws, 0); in iwx_init_fw_sec()
787 for (i = 0; i < dram->lmac_cnt; i++) { in iwx_init_fw_sec()
795 "%s: firmware LMAC section %d at 0x%llx size %lld\n", in iwx_init_fw_sec()
803 for (i = 0; i < dram->umac_cnt; i++) { in iwx_init_fw_sec()
812 "%s: firmware UMAC section %d at 0x%llx size %lld\n", in iwx_init_fw_sec()
829 for (i = 0; i < dram->paging_cnt; i++) { in iwx_init_fw_sec()
840 "%s: firmware paging section %d at 0x%llx size %lld\n", in iwx_init_fw_sec()
846 return 0; in iwx_init_fw_sec()
862 #if 0
868 uint32_t size = 0;
873 return 0;
878 err = iwx_dma_contig_alloc(sc->sc_dmat, fw_mon, size, 0);
883 "%s: allocated 0x%08x bytes for firmware monitor.\n",
889 fw_mon->size = 0;
899 return 0;
916 return 0;
920 return 0;
929 #if 0 in iwx_apply_debug_destination()
954 for (i = 0; i < sc->sc_fw.n_dest_reg; i++) { in iwx_apply_debug_destination()
1007 return 0; in iwx_apply_debug_destination()
1009 return 0; in iwx_apply_debug_destination()
1048 uint32_t control_flags = 0; in iwx_ctxt_info_init()
1053 memset(ctxt_info, 0, sizeof(*ctxt_info)); in iwx_ctxt_info_init()
1055 ctxt_info->version.version = 0; in iwx_ctxt_info_init()
1061 KASSERT(IWX_RX_QUEUE_CB_SIZE(IWX_MQ_RX_TABLE_SIZE) < 0xF, in iwx_ctxt_info_init()
1106 IWX_WRITE(sc, IWX_CSR_CTXT_INFO_BA, paddr & 0xffffffff); in iwx_ctxt_info_init()
1121 return 0; in iwx_ctxt_info_init()
1135 if (sc->sc_fw.iml == NULL || sc->sc_fw.iml_len == 0) { in iwx_ctxt_info_gen3_init()
1152 memset(prph_scratch, 0, sizeof(*prph_scratch)); in iwx_ctxt_info_gen3_init()
1154 prph_sc_ctrl->version.version = 0; in iwx_ctxt_info_gen3_init()
1178 memset(ctxt_info_gen3, 0, sizeof(*ctxt_info_gen3)); in iwx_ctxt_info_gen3_init()
1201 IWX_WRITE(sc, IWX_CSR_CTXT_INFO_ADDR, paddr & 0xffffffff); in iwx_ctxt_info_gen3_init()
1205 IWX_WRITE(sc, IWX_CSR_IML_DATA_ADDR, paddr & 0xffffffff); in iwx_ctxt_info_gen3_init()
1226 return 0; in iwx_ctxt_info_gen3_init()
1238 for (i = 0; i < dram->lmac_cnt + dram->umac_cnt; i++) in iwx_ctxt_info_free_fw_img()
1242 dram->lmac_cnt = 0; in iwx_ctxt_info_free_fw_img()
1243 dram->umac_cnt = 0; in iwx_ctxt_info_free_fw_img()
1277 return 0; in iwx_firmware_store_section()
1303 return 0; in iwx_set_default_calib()
1311 fw->fw_rawsize = 0; in iwx_fw_info_free()
1313 memset(fw->fw_sects, 0, sizeof(fw->fw_sects)); in iwx_fw_info_free()
1316 fw->iml_len = 0; in iwx_fw_info_free()
1319 #define IWX_FW_ADDR_CACHE_CONTROL 0xC0000000
1329 int err = 0; in iwx_read_firmware()
1334 return 0; in iwx_read_firmware()
1351 sc->sc_capaflags = 0; in iwx_read_firmware()
1353 memset(sc->sc_enabled_capa, 0, sizeof(sc->sc_enabled_capa)); in iwx_read_firmware()
1354 memset(sc->sc_ucode_api, 0, sizeof(sc->sc_ucode_api)); in iwx_read_firmware()
1355 sc->n_cmd_versions = 0; in iwx_read_firmware()
1358 if (*(const uint32_t *)fwp->data != 0 in iwx_read_firmware()
1498 for (i = 0; i < 32; i++) { in iwx_read_firmware()
1499 if ((le32toh(api->api_flags) & (1 << i)) == 0) in iwx_read_firmware()
1518 for (i = 0; i < 32; i++) { in iwx_read_firmware()
1519 if ((le32toh(capa->api_capa) & (1 << i)) == 0) in iwx_read_firmware()
1566 le32toh(((const uint32_t *)tlv_data)[0]), in iwx_read_firmware()
1575 if (*fw->dbg_dest_ver != 0) { in iwx_read_firmware()
1588 fw->n_dest_reg /= sizeof(dest_v1->reg_ops[0]); in iwx_read_firmware()
1638 sc->sc_uc.uc_lmac_error_event_table[0] = in iwx_read_firmware()
1652 fw->iml_len = 0; in iwx_read_firmware()
1669 if (sc->n_cmd_versions != 0) { in iwx_read_firmware()
1677 memcpy(&sc->cmd_versions[0], tlv_data, tlv_len); in iwx_read_firmware()
1692 case 0x1000003: in iwx_read_firmware()
1693 case 0x1000004: in iwx_read_firmware()
1697 case 0x1000000: in iwx_read_firmware()
1698 case 0x1000002: in iwx_read_firmware()
1713 case 0x100000b: in iwx_read_firmware()
1717 case 0x101: in iwx_read_firmware()
1721 case 0x100000c: in iwx_read_firmware()
1744 KASSERT(err == 0, ("unhandled fw parse error")); in iwx_read_firmware()
1766 return 0x00ffffff; in iwx_prph_addr_mask()
1768 return 0x000fffff; in iwx_prph_addr_mask()
1818 int offs, err = 0; in iwx_read_mem()
1823 for (offs = 0; offs < dwords; offs++) in iwx_read_mem()
1841 return 0; in iwx_poll_bit()
1851 if (sc->sc_nic_locks > 0) { in iwx_nic_lock()
1871 return 0; in iwx_nic_lock()
1877 if (sc->sc_nic_locks <= 0) in iwx_nic_assert_locked()
1884 if (sc->sc_nic_locks > 0) { in iwx_nic_unlock()
1885 if (--sc->sc_nic_locks == 0) in iwx_nic_unlock()
1903 return 0; in iwx_set_bits_mask_prph()
1911 return iwx_set_bits_mask_prph(sc, reg, bits, ~0); in iwx_set_bits_prph()
1917 return iwx_set_bits_mask_prph(sc, reg, 0, ~bits); in iwx_clear_bits_prph()
1923 if (error != 0) in iwx_dma_map_addr()
1926 *(bus_addr_t *)arg = segs[0].ds_addr; in iwx_dma_map_addr()
1941 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size, in iwx_dma_contig_alloc()
1942 1, size, 0, NULL, NULL, &dma->tag); in iwx_dma_contig_alloc()
1943 if (error != 0) in iwx_dma_contig_alloc()
1948 if (error != 0) in iwx_dma_contig_alloc()
1953 if (error != 0) { in iwx_dma_contig_alloc()
1961 return 0; in iwx_dma_contig_alloc()
1990 ring->cur = 0; in iwx_alloc_rx_ring()
2031 err = bus_dma_tag_create(sc->sc_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in iwx_alloc_rx_ring()
2033 0, NULL, NULL, &ring->data_dmat); in iwx_alloc_rx_ring()
2035 for (i = 0; i < IWX_RX_MQ_RING_COUNT; i++) { in iwx_alloc_rx_ring()
2038 memset(data, 0, sizeof(*data)); in iwx_alloc_rx_ring()
2039 err = bus_dmamap_create(ring->data_dmat, 0, &data->map); in iwx_alloc_rx_ring()
2050 return 0; in iwx_alloc_rx_ring()
2063 iwx_write_umac_prph(sc, IWX_RFH_RXF_DMA_CFG_GEN3, 0); in iwx_disable_rx_dma()
2065 iwx_write_prph(sc, IWX_RFH_RXF_DMA_CFG, 0); in iwx_disable_rx_dma()
2066 for (ntries = 0; ntries < 1000; ntries++) { in iwx_disable_rx_dma()
2085 ring->cur = 0; in iwx_reset_rx_ring()
2090 *status = 0; in iwx_reset_rx_ring()
2092 memset(ring->stat, 0, sizeof(*ring->stat)); in iwx_reset_rx_ring()
2107 for (i = 0; i < IWX_RX_MQ_RING_COUNT; i++) { in iwx_free_rx_ring()
2138 ring->queued = 0; in iwx_alloc_tx_ring()
2139 ring->cur = 0; in iwx_alloc_tx_ring()
2140 ring->cur_hw = 0; in iwx_alloc_tx_ring()
2141 ring->tail = 0; in iwx_alloc_tx_ring()
2142 ring->tail_hw = 0; in iwx_alloc_tx_ring()
2160 * The command is queue sc->txq[0], our default queue is sc->txq[1]. in iwx_alloc_tx_ring()
2163 * which aggregation is enabled. We map TID 0-7 to sc->txq[2:9]. in iwx_alloc_tx_ring()
2202 err = bus_dma_tag_create(sc->sc_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in iwx_alloc_tx_ring()
2204 mapsize, 0, NULL, NULL, &ring->data_dmat); in iwx_alloc_tx_ring()
2207 for (i = 0; i < IWX_TX_RING_COUNT; i++) { in iwx_alloc_tx_ring()
2213 err = bus_dmamap_create(ring->data_dmat, 0, &data->map); in iwx_alloc_tx_ring()
2221 return 0; in iwx_alloc_tx_ring()
2232 for (i = 0; i < IWX_TX_RING_COUNT; i++) { in iwx_reset_tx_ring()
2245 memset(ring->bc_tbl.vaddr, 0, ring->bc_tbl.size); in iwx_reset_tx_ring()
2248 memset(ring->desc, 0, ring->desc_dma.size); in iwx_reset_tx_ring()
2253 for (i = 0; i < nitems(sc->aggqid); i++) { in iwx_reset_tx_ring()
2255 sc->aggqid[i] = 0; in iwx_reset_tx_ring()
2259 ring->queued = 0; in iwx_reset_tx_ring()
2260 ring->cur = 0; in iwx_reset_tx_ring()
2261 ring->cur_hw = 0; in iwx_reset_tx_ring()
2262 ring->tail = 0; in iwx_reset_tx_ring()
2263 ring->tail_hw = 0; in iwx_reset_tx_ring()
2264 ring->tid = 0; in iwx_reset_tx_ring()
2276 for (i = 0; i < IWX_TX_RING_COUNT; i++) { in iwx_free_tx_ring()
2329 rv = (v & IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0; in iwx_check_rfkill()
2379 #if 0
2391 IWX_WRITE(sc, IWX_CSR_INT_MASK, 0); in iwx_disable_interrupts()
2394 IWX_WRITE(sc, IWX_CSR_INT, ~0); in iwx_disable_interrupts()
2395 IWX_WRITE(sc, IWX_CSR_FH_INT_STATUS, ~0); in iwx_disable_interrupts()
2409 memset(sc->ict_dma.vaddr, 0, IWX_ICT_SIZE); in iwx_ict_reset()
2410 sc->ict_cur = 0; in iwx_ict_reset()
2422 IWX_WRITE(sc, IWX_CSR_INT, ~0); in iwx_ict_reset()
2451 int t = 0; in iwx_prepare_card_hw()
2455 return 0; in iwx_prepare_card_hw()
2461 for (ntries = 0; ntries < 10; ntries++) { in iwx_prepare_card_hw()
2468 return 0; in iwx_prepare_card_hw()
2514 if (error != 0) { in iwx_apm_config()
2521 #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 in iwx_apm_config()
2523 #define PCI_PCIE_DCSR2 0x28 in iwx_apm_config()
2526 #define PCI_PCIE_DCSR2_LTREN 0x00000400 in iwx_apm_config()
2527 sc->sc_ltr_enabled = (cap & PCI_PCIE_DCSR2_LTREN) ? 1 : 0; in iwx_apm_config()
2528 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 in iwx_apm_config()
2547 int err = 0; in iwx_apm_init()
2625 iwx_conf_msix_hw(sc, 0); in iwx_init_msix_hw()
2639 int vector = 0; in iwx_conf_msix_hw()
2658 IWX_WRITE(sc, IWX_CSR_MSIX_FH_INT_MASK_AD, ~0); in iwx_conf_msix_hw()
2659 IWX_WRITE(sc, IWX_CSR_MSIX_HW_INT_MASK_AD, ~0); in iwx_conf_msix_hw()
2662 IWX_WRITE_1(sc, IWX_CSR_MSIX_RX_IVAR(0), in iwx_conf_msix_hw()
2730 if (hpm != 0xa5a5a5a0 && (hpm & IWX_PERSISTENCE_BIT)) { in iwx_clear_persistence_bit()
2741 return 0; in iwx_clear_persistence_bit()
2794 return 0; in iwx_start_hw()
2807 for (i = 0; i < nitems(sc->txq); i++) in iwx_stop_device()
2809 #if 0 in iwx_stop_device()
2811 for (i = 0; i < IEEE80211_NUM_TID; i++) { in iwx_stop_device()
2815 ieee80211_delba_request(ic, ni, 0, 1, i); in iwx_stop_device()
2821 if (sc->sc_nic_locks > 0) in iwx_stop_device()
2824 sc->sc_nic_locks = 0; in iwx_stop_device()
2862 uint32_t mask, val, reg_val = 0; in iwx_nic_config()
2904 return 0; in iwx_nic_rx_init()
2920 IWX_SETBITS(sc, IWX_CSR_MAC_SHADOW_REG_CTRL, 0x800fffff); in iwx_nic_init()
2922 return 0; in iwx_nic_init()
2956 if (cmd_ver == 0 || cmd_ver == IWX_FW_CMD_VER_UNKNOWN) { in iwx_enable_txq()
2957 memset(&cmd_v0, 0, sizeof(cmd_v0)); in iwx_enable_txq()
2965 hcmd.data[0] = &cmd_v0; in iwx_enable_txq()
2966 hcmd.len[0] = sizeof(cmd_v0); in iwx_enable_txq()
2968 memset(&cmd_v3, 0, sizeof(cmd_v3)); in iwx_enable_txq()
2973 cmd_v3.u.add.flags = htole32(0); in iwx_enable_txq()
2978 hcmd.data[0] = &cmd_v3; in iwx_enable_txq()
2979 hcmd.len[0] = sizeof(cmd_v3); in iwx_enable_txq()
3042 if (cmd_ver == 0 || cmd_ver == IWX_FW_CMD_VER_UNKNOWN) { in iwx_disable_txq()
3043 memset(&cmd_v0, 0, sizeof(cmd_v0)); in iwx_disable_txq()
3046 cmd_v0.flags = htole16(0); /* clear "queue enabled" flag */ in iwx_disable_txq()
3047 cmd_v0.cb_size = htole32(0); in iwx_disable_txq()
3048 cmd_v0.byte_cnt_addr = htole64(0); in iwx_disable_txq()
3049 cmd_v0.tfdq_addr = htole64(0); in iwx_disable_txq()
3051 hcmd.data[0] = &cmd_v0; in iwx_disable_txq()
3052 hcmd.len[0] = sizeof(cmd_v0); in iwx_disable_txq()
3054 memset(&cmd_v3, 0, sizeof(cmd_v3)); in iwx_disable_txq()
3060 hcmd.data[0] = &cmd_v3; in iwx_disable_txq()
3061 hcmd.len[0] = sizeof(cmd_v3); in iwx_disable_txq()
3116 cmd_id = iwx_cmd_id(IWX_SESSION_PROTECTION_CMD, IWX_MAC_CONF_GROUP, 0); in iwx_schedule_session_protection()
3117 err = iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd); in iwx_schedule_session_protection()
3131 .duration_tu = 0, in iwx_unprotect_session()
3136 if ((sc->sc_flags & IWX_FLAG_TE_ACTIVE) == 0) in iwx_unprotect_session()
3139 cmd_id = iwx_cmd_id(IWX_SESSION_PROTECTION_CMD, IWX_MAC_CONF_GROUP, 0); in iwx_unprotect_session()
3140 if (iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd) == 0) in iwx_unprotect_session()
3200 memset(bands, 0, sizeof(bands)); in iwx_init_channel_map()
3204 for (ch_idx = 0; in iwx_init_channel_map()
3208 uint32_t nflags = 0; in iwx_init_channel_map()
3209 int cflags = 0; in iwx_init_channel_map()
3218 if ((ch_flags & IWX_NVM_CHANNEL_VALID) == 0) in iwx_init_channel_map()
3221 if ((ch_flags & IWX_NVM_CHANNEL_40MHZ) != 0) in iwx_init_channel_map()
3239 memset(bands, 0, sizeof(bands)); in iwx_init_channel_map()
3247 uint32_t nflags = 0; in iwx_init_channel_map()
3248 int cflags = 0; in iwx_init_channel_map()
3257 if ((ch_flags & IWX_NVM_CHANNEL_VALID) == 0) in iwx_init_channel_map()
3260 if ((ch_flags & IWX_NVM_CHANNEL_40MHZ) != 0) in iwx_init_channel_map()
3262 if ((ch_flags & IWX_NVM_CHANNEL_80MHZ) != 0) in iwx_init_channel_map()
3264 if ((ch_flags & IWX_NVM_CHANNEL_160MHZ) != 0) in iwx_init_channel_map()
3292 reorder_buf->num_stored = 0; in iwx_init_reorder_buffer()
3294 reorder_buf->last_amsdu = 0; in iwx_init_reorder_buffer()
3295 reorder_buf->last_sub_index = 0; in iwx_init_reorder_buffer()
3296 reorder_buf->removed = 0; in iwx_init_reorder_buffer()
3297 reorder_buf->valid = 0; in iwx_init_reorder_buffer()
3298 reorder_buf->consec_oldsn_drops = 0; in iwx_init_reorder_buffer()
3299 reorder_buf->consec_oldsn_ampdu_gp2 = 0; in iwx_init_reorder_buffer()
3300 reorder_buf->consec_oldsn_prev_drop = 0; in iwx_init_reorder_buffer()
3319 for (i = 0; i < nitems(sc->sc_rxba_data); i++) { in iwx_find_rxba_data()
3336 uint32_t new_baid = 0; in iwx_sta_rx_agg_baid_cfg_cmd()
3341 memset(&cmd, 0, sizeof(cmd)); in iwx_sta_rx_agg_baid_cfg_cmd()
3378 return 0; in iwx_sta_rx_agg_baid_cfg_cmd()
3387 uint8_t baid = 0; in iwx_sta_rx_agg()
3419 if (timeout_val != 0) { in iwx_sta_rx_agg()
3420 DPRINTF(("%s: timeout_val != 0\n", __func__)); in iwx_sta_rx_agg()
3428 } else if (sc->sc_rx_ba_sessions > 0) in iwx_sta_rx_agg()
3447 if (qid == 0) { in iwx_sta_tx_agg_start()
3458 if ((sc->qenablemsk & (1 << qid)) == 0) { in iwx_sta_tx_agg_start()
3486 for (tid = 0; tid < IWX_MAX_TID_COUNT; tid++) { in iwx_ba_rx_task()
3506 iwx_sta_rx_agg(sc, ni, tid, 0, 0, 0, 0); in iwx_ba_rx_task()
3528 uint32_t started_mask = 0; in iwx_ba_tx_task()
3532 for (tid = 0; tid < IWX_MAX_TID_COUNT; tid++) { in iwx_ba_tx_task()
3552 for (tid = 0; tid < IWX_MAX_TID_COUNT; tid++) { in iwx_ba_tx_task()
3567 memset(data->hw_addr, 0, sizeof(data->hw_addr)); in iwx_set_mac_addr_from_csr()
3595 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00 in iwx_is_valid_mac_addr()
3598 return (memcmp(reserved_mac, addr, ETHER_ADDR_LEN) != 0 && in iwx_is_valid_mac_addr()
3599 memcmp(etherbroadcastaddr, addr, sizeof(etherbroadcastaddr)) != 0 && in iwx_is_valid_mac_addr()
3600 memcmp(etheranyaddr, addr, sizeof(etheranyaddr)) != 0 && in iwx_is_valid_mac_addr()
3610 dest[0] = hw_addr[3]; in iwx_flip_hw_address()
3613 dest[3] = hw_addr[0]; in iwx_flip_hw_address()
3617 dest[5] = hw_addr[0]; in iwx_flip_hw_address()
3632 int err = 0; in iwx_nvm_get()
3660 memset(nvm, 0, sizeof(*nvm)); in iwx_nvm_get()
3718 sc->sc_uc.uc_intr = 0; in iwx_load_firmware()
3719 sc->sc_uc.uc_ok = 0; in iwx_load_firmware()
3732 err = msleep(&sc->sc_uc, &sc->sc_mtx, 0, "iwxuc", hz); in iwx_load_firmware()
3752 IWX_WRITE(sc, IWX_CSR_INT, ~0); in iwx_start_fw()
3762 IWX_WRITE(sc, IWX_CSR_INT, ~0); in iwx_start_fw()
3780 uint32_t sha1 = 0; in iwx_pnvm_handle_section()
3781 uint16_t mac_type = 0, rf_id = 0; in iwx_pnvm_handle_section()
3783 int hw_match = 0; in iwx_pnvm_handle_section()
3784 uint32_t size = 0; in iwx_pnvm_handle_section()
3835 if (le32_to_cpup((const uint32_t *)data) == 0xddddeeee) in iwx_pnvm_handle_section()
3844 // XXX:misha pnvm_data is NULL and size is 0 at first pass in iwx_pnvm_handle_section()
3865 if (!hw_match || size == 0) { in iwx_pnvm_handle_section()
3909 if (sc->sc_sku_id[0] == le32toh(sku_id->data[0]) && in iwx_pnvm_parse()
3912 iwx_pnvm_handle_section(sc, data, len) == 0) in iwx_pnvm_parse()
3913 return 0; in iwx_pnvm_parse()
3950 int err = 0; in iwx_load_pnvm()
3953 if (sc->sc_sku_id[0] == 0 && in iwx_load_pnvm()
3954 sc->sc_sku_id[1] == 0 && in iwx_load_pnvm()
3955 sc->sc_sku_id[2] == 0) in iwx_load_pnvm()
3956 return 0; in iwx_load_pnvm()
3993 err = msleep(&sc->sc_init_complete, &sc->sc_mtx, 0, "iwxinit", 2 * hz); in iwx_load_pnvm()
4011 0, sizeof(tx_ant_cmd), &tx_ant_cmd); in iwx_send_tx_ant_cfg()
4025 return iwx_send_cmd_pdu(sc, IWX_PHY_CONFIGURATION_CMD, 0, in iwx_send_phy_cfg_cmd()
4037 cmd_id = iwx_cmd_id(IWX_DQA_ENABLE_CMD, IWX_DATA_PATH_GROUP, 0); in iwx_send_dqa_cmd()
4038 return iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(dqa_cmd), &dqa_cmd); in iwx_send_dqa_cmd()
4064 return 0; in iwx_load_ucode_wait_alive()
4084 sc->sc_init_complete = 0; in iwx_run_init_mvm_ucode()
4100 IWX_INIT_EXTENDED_CFG_CMD), 0, sizeof(init_cfg), &init_cfg); in iwx_run_init_mvm_ucode()
4108 IWX_NVM_ACCESS_COMPLETE), 0, sizeof(nvm_complete), &nvm_complete); in iwx_run_init_mvm_ucode()
4115 err = msleep(&sc->sc_init_complete, &sc->sc_mtx, 0, "iwxinit", 2 * hz); in iwx_run_init_mvm_ucode()
4137 return 0; in iwx_run_init_mvm_ucode()
4148 return 0; in iwx_config_ltr()
4150 return iwx_send_cmd_pdu(sc, IWX_LTR_CONFIG, 0, sizeof(cmd), &cmd); in iwx_config_ltr()
4161 desc[idx].rbid = htole16(idx & 0xffff); in iwx_update_rx_desc()
4180 int fatal = 0; in iwx_rx_addbuf()
4208 return 0; in iwx_rx_addbuf()
4263 total = nbant = noise = 0; in iwx_get_noise()
4264 for (i = 0; i < 3; i++) { in iwx_get_noise()
4265 noise = le32toh(stats->beacon_silence_rssi[i]) & 0xff; in iwx_get_noise()
4273 return (nbant == 0) ? -127 : (total / nbant) - 107; in iwx_get_noise()
4276 #if 0
4303 tid = hasqos ? ieee80211_get_qos(wh) & IEEE80211_QOS_TID : 0;
4307 pn = (uint64_t)ivp[0] |
4332 return 0;
4340 int ret = 0; in iwx_rx_hwdecrypt()
4345 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; in iwx_rx_hwdecrypt()
4347 return 0; in iwx_rx_hwdecrypt()
4350 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; in iwx_rx_hwdecrypt()
4352 return 0; in iwx_rx_hwdecrypt()
4356 if (((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != in iwx_rx_hwdecrypt()
4394 if (chanidx < 0 || chanidx >= nitems(ic->ic_channels)) { in iwx_rx_frame()
4404 for (int i = 0; i < ic->ic_nchans; i++) { in iwx_rx_frame()
4414 #if 0 /* XXX hw decrypt */ in iwx_rx_frame()
4416 iwx_ccmp_decap(sc, m, ni, rxi) != 0) { in iwx_rx_frame()
4428 tap->wr_flags = 0; in iwx_rx_frame()
4434 #if 0 in iwx_rx_frame()
4467 rate = 0; in iwx_rx_frame()
4471 IWX_RATE_MCS_VHT_MSK_V1)) == 0); in iwx_rx_frame()
4478 tap->wr_rate = (0x80 | mcs); in iwx_rx_frame()
4487 case 0xd: tap->wr_rate = 12; break; in iwx_rx_frame()
4488 case 0xf: tap->wr_rate = 18; break; in iwx_rx_frame()
4489 case 0x5: tap->wr_rate = 24; break; in iwx_rx_frame()
4490 case 0x7: tap->wr_rate = 36; break; in iwx_rx_frame()
4491 case 0x9: tap->wr_rate = 48; break; in iwx_rx_frame()
4492 case 0xb: tap->wr_rate = 72; break; in iwx_rx_frame()
4493 case 0x1: tap->wr_rate = 96; break; in iwx_rx_frame()
4494 case 0x3: tap->wr_rate = 108; break; in iwx_rx_frame()
4496 default: tap->wr_rate = 0; in iwx_rx_frame()
4531 int pad = 0; in iwx_rx_mpdu_mq()
4547 printf("%s: Bad CRC or FIFO: 0x%08X\n", __func__, desc->status); in iwx_rx_mpdu_mq()
4576 int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; in iwx_rx_mpdu_mq()
4578 switch (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) { in iwx_rx_mpdu_mq()
4634 if (subframe_idx > 0) in iwx_rx_mpdu_mq()
4642 qos[0] &= ~IEEE80211_QOS_AMSDU; in iwx_rx_mpdu_mq()
4672 rssi = (0 - IWX_MIN_DBM) + rssi; /* normalize */ in iwx_rx_mpdu_mq()
4675 memset(&rxs, 0, sizeof(rxs)); in iwx_rx_mpdu_mq()
4687 if (rxs.c_chain != 0) in iwx_rx_mpdu_mq()
4699 if (ieee80211_add_rx_params(m, &rxs) == 0) { in iwx_rx_mpdu_mq()
4706 #if 0 in iwx_rx_mpdu_mq()
4731 uint8_t num_tbs = le16toh(desc->num_tbs) & 0x1f; in iwx_clear_tx_desc()
4737 memset(tb, 0, sizeof(*tb)); in iwx_clear_tx_desc()
4752 ieee80211_tx_complete(&txd->in->in_ni, txd->m, 0); in iwx_txd_done()
4766 iwx_tx_update_byte_tbl(sc, ring, ring->tail, 0, 0); in iwx_txq_advance()
4769 if (ring->queued < 0) in iwx_txq_advance()
4804 sc->sc_tx_timer[qid] = 0; in iwx_rx_tx_cmd()
4846 if (sc->qfullmsk == 0 /* && ifq_is_oactive(&ifp->if_snd) */) { in iwx_clear_oactive()
4883 sizeof(ba_res->ra_tid[0]) * ra_tid_cnt + in iwx_rx_compressed_ba()
4884 sizeof(ba_res->tfd[0]) * tfd_cnt)) in iwx_rx_compressed_ba()
4887 for (i = 0; i < tfd_cnt; i++) { in iwx_rx_compressed_ba()
4901 #if 0 in iwx_rx_compressed_ba()
4907 sc->sc_tx_timer[qid] = 0; in iwx_rx_compressed_ba()
4964 memset(&cmd, 0, sizeof(cmd)); in iwx_binding_cmd()
4971 cmd.macs[0] = htole32(mac_id); in iwx_binding_cmd()
4981 status = 0; in iwx_binding_cmd()
4984 if (err == 0 && status != 0) in iwx_binding_cmd()
5033 memset(&cmd, 0, sizeof(cmd)); in iwx_phy_ctxt_cmd_uhb_v3_v4()
5074 return iwx_send_cmd_pdu(sc, IWX_PHY_CONTEXT_CMD, 0, sizeof(cmd), &cmd); in iwx_phy_ctxt_cmd_uhb_v3_v4()
5077 #if 0
5088 memset(&cmd, 0, sizeof(cmd));
5135 return iwx_send_cmd_pdu(sc, IWX_PHY_CONTEXT_CMD, 0, sizeof(cmd), &cmd);
5166 #if 0 in iwx_phy_ctxt_cmd()
5182 int err = 0, i, paylen, off/*, s*/; in iwx_send_cmd()
5194 for (i = 0, paylen = 0; i < nitems(hcmd->len); i++) { in iwx_send_cmd()
5225 * group 0 with a "BAD_COMMAND" firmware error. We must pretend in iwx_send_cmd()
5229 if (iwx_cmd_groupid(code) == 0) { in iwx_send_cmd()
5272 paddr = seg[0].ds_addr; in iwx_send_cmd()
5278 memset(cmd, 0, sizeof(*cmd)); in iwx_send_cmd()
5287 for (i = 0, off = 0; i < nitems(hcmd->data); i++) { in iwx_send_cmd()
5288 if (hcmd->len[i] == 0) in iwx_send_cmd()
5295 desc->tbs[0].tb_len = htole16(MIN(hdrlen + paylen, IWX_FIRST_TB_SIZE)); in iwx_send_cmd()
5297 memcpy(&desc->tbs[0].addr, &addr, sizeof(addr)); in iwx_send_cmd()
5328 if (err == 0) { in iwx_send_cmd()
5369 KASSERT(((cmd->flags & IWX_CMD_WANT_RESP) == 0), ("IWX_CMD_WANT_RESP")); in iwx_send_cmd_status()
5436 DPRINTF(("%s: command 0x%x done\n", __func__, code)); in iwx_cmd_done()
5437 if (ring->queued == 0) { in iwx_cmd_done()
5438 DPRINTF(("%s: unexpected firmware response to command 0x%x\n", in iwx_cmd_done()
5440 } else if (ring->queued > 0) in iwx_cmd_done()
5451 for (i = 0; i < rs->rs_nrates; i++) { in iwx_fw_rateidx_ofdm()
5456 return 0; in iwx_fw_rateidx_ofdm()
5466 for (i = 0; i < rs->rs_nrates; i++) { in iwx_fw_rateidx_cck()
5471 return 0; in iwx_fw_rateidx_cck()
5490 for (i = 0; i < rs->rs_nrates; i++) { in iwx_min_basic_rate()
5491 if ((rs->rs_rates[i] & IEEE80211_RATE_BASIC) == 0) in iwx_min_basic_rate()
5520 int type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; in iwx_tx_fill_cmd()
5531 *flags = 0; in iwx_tx_fill_cmd()
5561 if ((*flags & IWX_TX_FLAGS_CMD_RATE) == 0) { in iwx_tx_fill_cmd()
5562 *rate_n_flags = 0; in iwx_tx_fill_cmd()
5599 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d flags=0x%x\n", in iwx_tx_fill_cmd()
5601 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d rate_n_flags=0x%x\n", in iwx_tx_fill_cmd()
5624 * to SRAM- 0 for one chunk, 1 for 2 and so on. in iwx_tx_update_byte_tbl()
5663 uint16_t num_tbs, flags, offload_assist = 0; in iwx_tx()
5698 sc->aggqid[tid] != 0) { in iwx_tx()
5705 memset(desc, 0, sizeof(*desc)); in iwx_tx()
5710 cmd->hdr.flags = 0; in iwx_tx()
5719 if ((m->m_flags & M_AMPDU_MPDU) == 0) in iwx_tx()
5726 tap->wt_flags = 0; in iwx_tx()
5761 pad = 0; in iwx_tx()
5765 memset(tx, 0, sizeof(*tx)); in iwx_tx()
5774 memset(tx, 0, sizeof(*tx)); in iwx_tx()
5818 desc->tbs[0].tb_len = htole16(IWX_FIRST_TB_SIZE); in iwx_tx()
5820 memcpy(&desc->tbs[0].addr, &paddr, sizeof(paddr)); in iwx_tx()
5821 if (data->cmd_paddr >> 32 != (data->cmd_paddr + le32toh(desc->tbs[0].tb_len)) >> 32) in iwx_tx()
5832 for (i = 0; i < nsegs; i++) { in iwx_tx()
5861 return 0; in iwx_tx()
5894 if (resp_len == 0) in iwx_flush_sta_tids()
5914 for (i = 0; i < num_flushed_queues; i++) { in iwx_flush_sta_tids()
5944 memset(&cmd, 0, sizeof(cmd)); in iwx_drain_sta()
5949 cmd.station_flags = drain ? htole32(IWX_STA_FLG_DRAIN_FLOW) : 0; in iwx_drain_sta()
5987 err = iwx_flush_sta_tids(sc, IWX_STATION_ID, 0xffff); in iwx_flush_sta()
5999 err = iwx_drain_sta(sc, in, 0); in iwx_flush_sta()
6012 0, sizeof(struct iwx_beacon_filter_cmd), cmd); in iwx_beacon_filter_send_cmd()
6025 return 0; in iwx_update_beacon_abort()
6069 memset(&cmd, 0, sizeof(cmd)); in iwx_power_mac_update_mode()
6073 err = iwx_send_cmd_pdu(sc, IWX_MAC_PM_POWER_TABLE, 0, in iwx_power_mac_update_mode()
6075 if (err != 0) in iwx_power_mac_update_mode()
6093 IWX_POWER_TABLE_CMD, 0, sizeof(cmd), &cmd); in iwx_power_update_device()
6095 #if 0
6107 if (err == 0)
6119 memset(&cmd, 0, sizeof(cmd)); in iwx_disable_beacon_filter()
6122 if (err == 0) in iwx_disable_beacon_filter()
6123 sc->sc_bf.bf_enabled = 0; in iwx_disable_beacon_filter()
6143 memset(&add_sta_cmd, 0, sizeof(add_sta_cmd)); in iwx_add_sta_cmd()
6164 add_sta_cmd.add_modify = update ? 1 : 0; in iwx_add_sta_cmd()
6178 int hasmimo = 0; in iwx_add_sta_cmd()
6179 for (i = 0; i < htrs->rs_nrates; i++) { in iwx_add_sta_cmd()
6256 if ((sc->sc_flags & IWX_FLAG_STA_ACTIVE) == 0) in iwx_rm_sta_cmd()
6259 memset(&rm_sta_cmd, 0, sizeof(rm_sta_cmd)); in iwx_rm_sta_cmd()
6265 err = iwx_send_cmd_pdu(sc, IWX_REMOVE_STA, 0, sizeof(rm_sta_cmd), in iwx_rm_sta_cmd()
6289 if (cmd_ver != 0 && cmd_ver != IWX_FW_CMD_VER_UNKNOWN) { in iwx_rm_sta()
6296 if ((sc->qenablemsk & (1 << i)) == 0) in iwx_rm_sta()
6316 in->in_flags = 0; in iwx_rm_sta()
6318 sc->sc_rx_ba_sessions = 0; in iwx_rm_sta()
6319 sc->ba_rx.start_tidmask = 0; in iwx_rm_sta()
6320 sc->ba_rx.stop_tidmask = 0; in iwx_rm_sta()
6321 memset(sc->aggqid, 0, sizeof(sc->aggqid)); in iwx_rm_sta()
6322 sc->ba_tx.start_tidmask = 0; in iwx_rm_sta()
6323 sc->ba_tx.stop_tidmask = 0; in iwx_rm_sta()
6327 #if 0 in iwx_rm_sta()
6328 for (i = 0; i < IEEE80211_NUM_TID; i++) { in iwx_rm_sta()
6332 ieee80211_delba_request(ic, ni, 0, 1, i); in iwx_rm_sta()
6336 for (i = 0; i < IWX_MAX_TID_COUNT; i++) { in iwx_rm_sta()
6338 ba->ba_flags = 0; in iwx_rm_sta()
6341 return 0; in iwx_rm_sta()
6355 for (nchan = j = 0; in iwx_umac_scan_fill_channels()
6362 channel_num = ieee80211_mhz2ieee(c->ic_freq, 0); in iwx_umac_scan_fill_channels()
6371 chan->v2.iter_interval = 0; in iwx_umac_scan_fill_channels()
6375 chan->v1.iter_interval = htole16(0); in iwx_umac_scan_fill_channels()
6395 memset(preq, 0, sizeof(*preq)); in iwx_fill_probe_req()
6404 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT | in iwx_fill_probe_req()
6410 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */ in iwx_fill_probe_req()
6411 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */ in iwx_fill_probe_req()
6415 *frm++ = 0; in iwx_fill_probe_req()
6419 preq->mac_header.offset = 0; in iwx_fill_probe_req()
6430 preq->band_data[0].offset = htole16(frm - (uint8_t *)wh); in iwx_fill_probe_req()
6443 *frm++ = 0; in iwx_fill_probe_req()
6446 preq->band_data[0].len = htole16(frm - pos); in iwx_fill_probe_req()
6485 return 0; in iwx_fill_probe_req()
6493 .id = iwx_cmd_id(IWX_SCAN_CFG_CMD, IWX_LONG_GROUP, 0), in iwx_config_umac_scan_reduced()
6494 .len[0] = sizeof(scan_cfg), in iwx_config_umac_scan_reduced()
6495 .data[0] = &scan_cfg, in iwx_config_umac_scan_reduced()
6496 .flags = 0, in iwx_config_umac_scan_reduced()
6506 memset(&scan_cfg, 0, sizeof(scan_cfg)); in iwx_config_umac_scan_reduced()
6514 scan_cfg.bcast_sta_id = 0xff; in iwx_config_umac_scan_reduced()
6527 uint16_t flags = 0; in iwx_scan_umac_flags_v2()
6529 if (ss->ss_nssid == 0) { in iwx_scan_umac_flags_v2()
6586 max_out_time = htole32(0); in iwx_scan_umac_dwell_v10()
6587 suspend_time = htole32(0); in iwx_scan_umac_dwell_v10()
6617 gp->scan_start_mac_id = 0; in iwx_scan_umac_fill_general_p_v10()
6630 cp->n_aps_override[0] = IWX_SCAN_ADWELL_N_APS_GO_FRIENDLY; in iwx_scan_umac_fill_ch_p_v6()
6640 .id = iwx_cmd_id(IWX_SCAN_REQ_UMAC, IWX_LONG_GROUP, 0), in iwx_umac_scan_v14()
6641 .len = { 0, }, in iwx_umac_scan_v14()
6643 .flags = 0, in iwx_umac_scan_v14()
6647 int err, async = bgscan, n_ssid = 0; in iwx_umac_scan_v14()
6649 uint32_t bitmap_ssid = 0; in iwx_umac_scan_v14()
6658 cmd->uid = htole32(0); in iwx_umac_scan_v14()
6664 scan_p->periodic_params.schedule[0].interval = htole16(0); in iwx_umac_scan_v14()
6665 scan_p->periodic_params.schedule[0].iter_count = 1; in iwx_umac_scan_v14()
6674 for (int i=0; i < ss->ss_nssid; i++) { in iwx_umac_scan_v14()
6684 DPRINTF(("%s: bitmap_ssid=0x%x\n", __func__, bitmap_ssid)); in iwx_umac_scan_v14()
6689 hcmd.len[0] = sizeof(*cmd); in iwx_umac_scan_v14()
6690 hcmd.data[0] = (void *)cmd; in iwx_umac_scan_v14()
6691 hcmd.flags |= async ? IWX_CMD_ASYNC : 0; in iwx_umac_scan_v14()
6703 (le16toh(notif->mcc) & 0xff00) >> 8, le16toh(notif->mcc) & 0xff); in iwx_mcc_update()
6706 "(0x%x)\n", DEVNAME(sc), alpha2, le16toh(notif->mcc)); in iwx_mcc_update()
6717 for (i = 0; i < rs->rs_nrates; i++) { in iwx_ridx2rate()
6723 return 0; in iwx_ridx2rate()
6731 for (ridx = 0; ridx < nitems(iwx_rates); ridx++) { in iwx_rval2ridx()
6749 uint8_t cck = 0; in iwx_ack_rates()
6750 uint8_t ofdm = 0; in iwx_ack_rates()
6756 if ((iwx_ridx2rate(rs, i) & IEEE80211_RATE_BASIC) == 0) in iwx_ack_rates()
6764 if ((iwx_ridx2rate(rs, i) & IEEE80211_RATE_BASIC) == 0) in iwx_ack_rates()
6869 ? IWX_MAC_FLG_SHORT_PREAMBLE : 0); in iwx_mac_ctxt_cmd_common()
6872 ? IWX_MAC_FLG_SHORT_SLOT : 0); in iwx_mac_ctxt_cmd_common()
6877 for (int i = 0; i < WME_NUM_AC; i++) { in iwx_mac_ctxt_cmd_common()
6946 sta->assoc_beacon_arrive_time = 0; in iwx_mac_ctxt_cmd_fill_sta()
6950 sta->data_policy = htole32(0); in iwx_mac_ctxt_cmd_fill_sta()
6969 memset(&cmd, 0, sizeof(cmd)); in iwx_mac_ctxt_cmd()
6974 return iwx_send_cmd_pdu(sc, IWX_MAC_CONTEXT_CMD, 0, in iwx_mac_ctxt_cmd()
6994 return iwx_send_cmd_pdu(sc, IWX_MAC_CONTEXT_CMD, 0, sizeof(cmd), &cmd); in iwx_mac_ctxt_cmd()
7005 .len[0] = sizeof(scmd), in iwx_clear_statistics()
7006 .data[0] = &scmd, in iwx_clear_statistics()
7017 return 0; in iwx_clear_statistics()
7024 err = iwx_umac_scan_v14(sc, 0); in iwx_scan()
7030 return 0; in iwx_scan()
7044 return 0; in iwx_bgscan()
7066 return 0; in iwx_enable_mgmt_queue()
7077 if (cmd_ver == 0 || cmd_ver == IWX_FW_CMD_VER_UNKNOWN) in iwx_disable_mgmt_queue()
7078 return 0; in iwx_disable_mgmt_queue()
7090 return 0; in iwx_disable_mgmt_queue()
7100 for (i = 0; i < rs->rs_nrates; i++) { in iwx_rs_rval2idx()
7111 uint16_t htrates = 0; in iwx_rs_ht_rates()
7116 for (i = 0; i < htrs->rs_nrates; i++) { in iwx_rs_ht_rates()
7121 for (i = 0; i < htrs->rs_nrates; i++) { in iwx_rs_ht_rates()
7129 "%s:%d rsidx=%i htrates=0x%x\n", __func__, __LINE__, rsidx, htrates); in iwx_rs_ht_rates()
7139 #define IEEE80211_VHT_MCS_FOR_SS_MASK(n) (0x3 << (2*((n)-1))) in iwx_rs_vht_rates()
7156 if ((ni->ni_htcap & IEEE80211_HTCAP_CHWIDTH40) == 0) in iwx_rs_vht_rates()
7182 memset(&cfg_cmd, 0, sizeof(cfg_cmd)); in iwx_rs_init_v3()
7184 for (i = 0; i < rs->rs_nrates; i++) { in iwx_rs_init_v3()
7236 cmd_id = iwx_cmd_id(IWX_TLC_MNG_CONFIG_CMD, IWX_DATA_PATH_GROUP, 0); in iwx_rs_init_v3()
7250 int sgi80 = 0; in iwx_rs_init_v4()
7253 memset(&cfg_cmd, 0, sizeof(cfg_cmd)); in iwx_rs_init_v4()
7255 for (i = 0; i < rs->rs_nrates; i++) { in iwx_rs_init_v4()
7262 for (i = 0; i < htrs->rs_nrates; i++) { in iwx_rs_init_v4()
7273 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d SISO=0x%x\n", in iwx_rs_init_v4()
7276 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d MIMO2=0x%x\n", in iwx_rs_init_v4()
7288 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d SISO=0x%x\n", in iwx_rs_init_v4()
7291 IWX_DPRINTF(sc, IWX_DEBUG_TXRATE, "%s:%d MIMO2=0x%x\n", in iwx_rs_init_v4()
7298 #if 0 in iwx_rs_init_v4()
7336 cmd_id = iwx_cmd_id(IWX_TLC_MNG_CONFIG_CMD, IWX_DATA_PATH_GROUP, 0); in iwx_rs_init_v4()
7450 (le32toh(notif->flags) & IWX_TLC_NOTIF_FLAG_RATE) == 0) in iwx_rs_update()
7464 memset(&cmd, 0, sizeof(cmd)); in iwx_phy_send_rlc()
7477 return iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd); in iwx_phy_send_rlc()
7542 return 0; in iwx_phy_ctxt_update()
7561 err = iwx_phy_ctxt_update(sc, &sc->sc_phyctxt[0], in iwx_auth()
7562 ic->ic_bsschan, 1, 1, 0, IEEE80211_HTOP0_SCO_SCN, in iwx_auth()
7567 err = iwx_phy_ctxt_update(sc, &sc->sc_phyctxt[0], in iwx_auth()
7568 in->in_ni.ni_chan, 1, 1, 0, IEEE80211_HTOP0_SCO_SCN, in iwx_auth()
7573 ivp->phy_ctxt = &sc->sc_phyctxt[0]; in iwx_auth()
7578 err = iwx_mac_ctxt_cmd(sc, in, IWX_FW_CTXT_ACTION_ADD, 0); in iwx_auth()
7594 err = iwx_add_sta_cmd(sc, in, 0); in iwx_auth()
7608 return 0; in iwx_auth()
7644 iwx_mac_ctxt_cmd(sc, in, IWX_FW_CTXT_ACTION_REMOVE, 0); in iwx_auth()
7682 err = iwx_mac_ctxt_cmd(sc, in, IWX_FW_CTXT_ACTION_REMOVE, 0); in iwx_deauth()
7693 err = iwx_phy_ctxt_update(sc, &sc->sc_phyctxt[0], in iwx_deauth()
7694 &ic->ic_channels[1], 1, 1, 0, IEEE80211_HTOP0_SCO_SCN, in iwx_deauth()
7699 return 0; in iwx_deauth()
7724 0, sco, vht_chan_width); in iwx_run()
7787 return 0; in iwx_run()
7796 return 0; in iwx_run()
7827 for (i = 0; i < nitems(sc->sc_rxba_data); i++) { in iwx_run_stop()
7831 iwx_sta_rx_agg(sc, ni, rxba->tid, 0, 0, 0, 0); in iwx_run_stop()
7846 err = iwx_mac_ctxt_cmd(sc, in, IWX_FW_CTXT_ACTION_MODIFY, 0); in iwx_run_stop()
7852 return 0; in iwx_run_stop()
7862 #if 0
7912 memset(&cmd, 0, sizeof(cmd));
7922 cmd.common.key_offset = 0;
7955 return 0;
7963 int err = 0, s = splnet();
7965 while (sc->setkey_nkeys > 0) {
7970 a->sta_id = 0;
7995 if ((sc->sc_flags & IWX_FLAG_STA_ACTIVE) == 0)
7998 memset(&cmd, 0, sizeof(cmd));
8008 cmd.common.key_offset = 0;
8021 int err = 0; in iwx_newstate_sub()
8097 return 0; in iwx_newstate()
8101 if (err == 0) in iwx_newstate()
8113 if ((sc->sc_flags & (IWX_FLAG_SCANNING | IWX_FLAG_BGSCAN)) == 0) in iwx_endscan()
8193 int hasmimo = 0; in iwx_fill_sf_command()
8194 for (i = 0; i < htrs->rs_nrates; i++) { in iwx_fill_sf_command()
8213 for (i = 0; i < IWX_SF_NUM_SCENARIO; i++) { in iwx_fill_sf_command()
8214 for (j = 0; j < IWX_SF_NUM_TIMEOUT_TYPES; j++) { in iwx_fill_sf_command()
8239 int err = 0; in iwx_sf_config()
8270 return iwx_send_cmd_pdu(sc, IWX_BT_CONFIG, 0, sizeof(bt_cmd), in iwx_send_bt_init_conf()
8279 uint32_t cmd_id, flags = 0; in iwx_send_soc_conf()
8281 memset(&cmd, 0, sizeof(cmd)); in iwx_send_soc_conf()
8306 cmd_id = iwx_cmd_id(IWX_SOC_CONFIGURATION_CMD, IWX_SYSTEM_GROUP, 0); in iwx_send_soc_conf()
8307 err = iwx_send_cmd_pdu(sc, cmd_id, 0, sizeof(cmd), &cmd); in iwx_send_soc_conf()
8327 memset(&mcc_cmd, 0, sizeof(mcc_cmd)); in iwx_send_update_mcc_cmd()
8328 mcc_cmd.mcc = htole16(alpha2[0] << 8 | alpha2[1]); in iwx_send_update_mcc_cmd()
8335 hcmd.len[0] = sizeof(struct iwx_mcc_update_cmd); in iwx_send_update_mcc_cmd()
8356 resp->n_channels * sizeof(resp->channels[0])) { in iwx_send_update_mcc_cmd()
8361 …DPRINTF(("MCC status=0x%x mcc=0x%x cap=0x%x time=0x%x geo_info=0x%x source_id=0x%d n_channels=%u\n… in iwx_send_update_mcc_cmd()
8381 memset(&cmd, 0, sizeof(cmd)); in iwx_send_temp_report_ths_cmd()
8385 0, sizeof(cmd), &cmd); in iwx_send_temp_report_ths_cmd()
8397 int err = 0, i; in iwx_init_hw()
8399 err = iwx_run_init_mvm_ucode(sc, 0); in iwx_init_hw()
8445 for (i = 0; i < IWX_NUM_PHY_CTX; i++) { in iwx_init_hw()
8454 IWX_FW_CTXT_ACTION_ADD, 0, 0, 0); in iwx_init_hw()
8537 cmd->port_id = 0; in iwx_allow_mcast()
8538 cmd->count = 0; in iwx_allow_mcast()
8543 0, size, cmd); in iwx_allow_mcast()
8572 return 0; in iwx_init()
8583 while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { in iwx_start()
8585 if (iwx_tx(sc, m, ni) != 0) { in iwx_start()
8614 sc->sc_rx_ba_sessions = 0; in iwx_stop()
8615 sc->ba_rx.start_tidmask = 0; in iwx_stop()
8616 sc->ba_rx.stop_tidmask = 0; in iwx_stop()
8617 memset(sc->aggqid, 0, sizeof(sc->aggqid)); in iwx_stop()
8618 sc->ba_tx.start_tidmask = 0; in iwx_stop()
8619 sc->ba_tx.stop_tidmask = 0; in iwx_stop()
8634 for (i = 0; i < nitems(sc->sc_tx_timer); i++) { in iwx_watchdog()
8635 if (sc->sc_tx_timer[i] > 0) { in iwx_watchdog()
8636 if (--sc->sc_tx_timer[i] == 0) { in iwx_watchdog()
8656 uint32_t valid; /* (nonzero) valid, (0) log is empty */
8711 uint32_t valid; /* (nonzero) valid, (0) log is empty */
8739 if (base < 0x400000) { in iwx_nic_umac_error()
8740 printf("%s: Invalid error log pointer 0x%08x\n", in iwx_nic_umac_error()
8752 printf("%s: Status: 0x%x, count: %d\n", DEVNAME(sc), in iwx_nic_umac_error()
8756 printf("%s: 0x%08X | %s\n", DEVNAME(sc), table.error_id, in iwx_nic_umac_error()
8758 printf("%s: 0x%08X | umac branchlink1\n", DEVNAME(sc), table.blink1); in iwx_nic_umac_error()
8759 printf("%s: 0x%08X | umac branchlink2\n", DEVNAME(sc), table.blink2); in iwx_nic_umac_error()
8760 printf("%s: 0x%08X | umac interruptlink1\n", DEVNAME(sc), table.ilink1); in iwx_nic_umac_error()
8761 printf("%s: 0x%08X | umac interruptlink2\n", DEVNAME(sc), table.ilink2); in iwx_nic_umac_error()
8762 printf("%s: 0x%08X | umac data1\n", DEVNAME(sc), table.data1); in iwx_nic_umac_error()
8763 printf("%s: 0x%08X | umac data2\n", DEVNAME(sc), table.data2); in iwx_nic_umac_error()
8764 printf("%s: 0x%08X | umac data3\n", DEVNAME(sc), table.data3); in iwx_nic_umac_error()
8765 printf("%s: 0x%08X | umac major\n", DEVNAME(sc), table.umac_major); in iwx_nic_umac_error()
8766 printf("%s: 0x%08X | umac minor\n", DEVNAME(sc), table.umac_minor); in iwx_nic_umac_error()
8767 printf("%s: 0x%08X | frame pointer\n", DEVNAME(sc), in iwx_nic_umac_error()
8769 printf("%s: 0x%08X | stack pointer\n", DEVNAME(sc), in iwx_nic_umac_error()
8771 printf("%s: 0x%08X | last host cmd\n", DEVNAME(sc), table.cmd_header); in iwx_nic_umac_error()
8772 printf("%s: 0x%08X | isr status reg\n", DEVNAME(sc), in iwx_nic_umac_error()
8776 #define IWX_FW_SYSASSERT_CPU_MASK 0xf0000000
8781 { "NMI_INTERRUPT_WDG", 0x34 },
8782 { "SYSASSERT", 0x35 },
8783 { "UCODE_VERSION_MISMATCH", 0x37 },
8784 { "BAD_COMMAND", 0x38 },
8785 { "BAD_COMMAND", 0x39 },
8786 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
8787 { "FATAL_ERROR", 0x3D },
8788 { "NMI_TRM_HW_ERR", 0x46 },
8789 { "NMI_INTERRUPT_TRM", 0x4C },
8790 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
8791 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
8792 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
8793 { "NMI_INTERRUPT_HOST", 0x66 },
8794 { "NMI_INTERRUPT_LMAC_FATAL", 0x70 },
8795 { "NMI_INTERRUPT_UMAC_FATAL", 0x71 },
8796 { "NMI_INTERRUPT_OTHER_LMAC_FATAL", 0x73 },
8797 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
8798 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
8799 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
8800 { "ADVANCED_SYSASSERT", 0 },
8808 for (i = 0; i < nitems(advanced_lookup) - 1; i++) in iwx_desc_lookup()
8832 base = sc->sc_uc.uc_lmac_error_event_table[0]; in iwx_nic_error()
8834 if (base < 0x400000) { in iwx_nic_error()
8835 printf("%s: Invalid error log pointer 0x%08x\n", in iwx_nic_error()
8855 printf("%s: Status: 0x%x, count: %d\n", DEVNAME(sc), in iwx_nic_error()
8860 printf("%s: 0x%08X | %-28s\n", DEVNAME(sc), table.error_id, in iwx_nic_error()
8914 for (i = 0; i < nitems(sc->txq); i++) { in iwx_dump_driver_status()
8929 } while (/*CONSTCOND*/0)
8936 qid = pkt->hdr.qid & ~0x80; in iwx_rx_pkt_valid()
8940 return (!(qid == 0 && idx == 0 && code == 0) && in iwx_rx_pkt_valid()
8949 uint32_t offset = 0, nextoff = 0, nmpdu = 0, len; in iwx_rx_pkt()
8968 * in group 0, forcing us to use this hack. in iwx_rx_pkt()
9007 if (offset > 0) in iwx_rx_pkt()
9017 m = m_copym(m0, 0, M_COPYALL, M_NOWAIT); in iwx_rx_pkt()
9057 sc->sc_uc.uc_ok = 0; in iwx_rx_pkt()
9072 sc->sc_uc.uc_lmac_error_event_table[0] = le32toh( in iwx_rx_pkt()
9073 resp6->lmac_data[0].dbg_ptrs.error_event_table_ptr); in iwx_rx_pkt()
9077 resp6->lmac_data[0].dbg_ptrs.log_event_table_ptr); in iwx_rx_pkt()
9080 sc->sc_sku_id[0] = in iwx_rx_pkt()
9081 le32toh(resp6->sku_id.data[0]); in iwx_rx_pkt()
9098 sc->sc_uc.uc_lmac_error_event_table[0] = le32toh( in iwx_rx_pkt()
9099 resp5->lmac_data[0].dbg_ptrs.error_event_table_ptr); in iwx_rx_pkt()
9103 resp5->lmac_data[0].dbg_ptrs.log_event_table_ptr); in iwx_rx_pkt()
9106 sc->sc_sku_id[0] = in iwx_rx_pkt()
9107 le32toh(resp5->sku_id.data[0]); in iwx_rx_pkt()
9116 sc->sc_uc.uc_lmac_error_event_table[0] = le32toh( in iwx_rx_pkt()
9117 resp4->lmac_data[0].dbg_ptrs.error_event_table_ptr); in iwx_rx_pkt()
9121 resp4->lmac_data[0].dbg_ptrs.log_event_table_ptr); in iwx_rx_pkt()
9254 printf("%s: firmware error 0x%x, cmd 0x%x\n", in iwx_rx_pkt()
9284 if (status == 1 && start == 0 && in iwx_rx_pkt()
9337 case IWX_WIDE_ID(IWX_DATA_PATH_GROUP, 0xf8): in iwx_rx_pkt()
9348 handled = 0; in iwx_rx_pkt()
9350 if ((code == 0xc2 && pkt->len_n_flags == 0x0000000c) || in iwx_rx_pkt()
9351 (code == 0xce && pkt->len_n_flags == 0x2000002c)) in iwx_rx_pkt()
9353 printf("%s: unhandled firmware response 0x%x/0x%x " in iwx_rx_pkt()
9356 (qid & ~0x80), idx); in iwx_rx_pkt()
9361 * uCode sets bit 0x80 when it originates the notification, in iwx_rx_pkt()
9393 hw = le16toh(*status) & 0xfff; in iwx_notif_intr()
9395 hw = le16toh(sc->rxq.stat->closed_rb_num) & 0xfff; in iwx_notif_intr()
9411 hw = (hw == 0) ? IWX_RX_MQ_RING_COUNT - 1 : hw - 1; in iwx_notif_intr()
9415 #if 0
9422 int r1, r2, rv = 0;
9424 IWX_WRITE(sc, IWX_CSR_INT_MASK, 0);
9437 r1 = r2 = 0;
9440 ict[sc->ict_cur] = 0;
9446 if (r1 == 0xffffffff)
9447 r1 = 0;
9450 if (r1 & 0xc0000)
9451 r1 |= 0x8000;
9452 r1 = (0xff & r1) | ((0xff00 & r1) << 16);
9455 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
9459 if (r1 == 0 && r2 == 0) {
9466 #if 0
9469 for (i = 0; i < IWX_RX_MQ_RING_COUNT; i++)
9550 int vector = 0; in iwx_intr_msix()
9599 #if 0 in iwx_intr_msix()
9606 for (int i = 0; i < IWX_RX_MQ_RING_COUNT; i++) in iwx_intr_msix()
9690 IWX_DEV_INFO(0x2725, 0x0090, iwx_2ax_cfg_so_gf_a0),
9691 IWX_DEV_INFO(0x2725, 0x0020, iwx_2ax_cfg_ty_gf_a0),
9692 IWX_DEV_INFO(0x2725, 0x2020, iwx_2ax_cfg_ty_gf_a0),
9693 IWX_DEV_INFO(0x2725, 0x0024, iwx_2ax_cfg_ty_gf_a0),
9694 IWX_DEV_INFO(0x2725, 0x0310, iwx_2ax_cfg_ty_gf_a0),
9695 IWX_DEV_INFO(0x2725, 0x0510, iwx_2ax_cfg_ty_gf_a0),
9696 IWX_DEV_INFO(0x2725, 0x0A10, iwx_2ax_cfg_ty_gf_a0),
9697 IWX_DEV_INFO(0x2725, 0xE020, iwx_2ax_cfg_ty_gf_a0),
9698 IWX_DEV_INFO(0x2725, 0xE024, iwx_2ax_cfg_ty_gf_a0),
9699 IWX_DEV_INFO(0x2725, 0x4020, iwx_2ax_cfg_ty_gf_a0),
9700 IWX_DEV_INFO(0x2725, 0x6020, iwx_2ax_cfg_ty_gf_a0),
9701 IWX_DEV_INFO(0x2725, 0x6024, iwx_2ax_cfg_ty_gf_a0),
9702 IWX_DEV_INFO(0x2725, 0x1673, iwx_2ax_cfg_ty_gf_a0), /* killer_1675w */
9703 IWX_DEV_INFO(0x2725, 0x1674, iwx_2ax_cfg_ty_gf_a0), /* killer_1675x */
9704 IWX_DEV_INFO(0x51f0, 0x1691, iwx_2ax_cfg_so_gf4_a0), /* killer_1690s */
9705 IWX_DEV_INFO(0x51f0, 0x1692, iwx_2ax_cfg_so_gf4_a0), /* killer_1690i */
9706 IWX_DEV_INFO(0x51f1, 0x1691, iwx_2ax_cfg_so_gf4_a0),
9707 IWX_DEV_INFO(0x51f1, 0x1692, iwx_2ax_cfg_so_gf4_a0),
9708 IWX_DEV_INFO(0x54f0, 0x1691, iwx_2ax_cfg_so_gf4_a0), /* killer_1690s */
9709 IWX_DEV_INFO(0x54f0, 0x1692, iwx_2ax_cfg_so_gf4_a0), /* killer_1690i */
9710 IWX_DEV_INFO(0x7a70, 0x0090, iwx_2ax_cfg_so_gf_a0_long),
9711 IWX_DEV_INFO(0x7a70, 0x0098, iwx_2ax_cfg_so_gf_a0_long),
9712 IWX_DEV_INFO(0x7a70, 0x00b0, iwx_2ax_cfg_so_gf4_a0_long),
9713 IWX_DEV_INFO(0x7a70, 0x0310, iwx_2ax_cfg_so_gf_a0_long),
9714 IWX_DEV_INFO(0x7a70, 0x0510, iwx_2ax_cfg_so_gf_a0_long),
9715 IWX_DEV_INFO(0x7a70, 0x0a10, iwx_2ax_cfg_so_gf_a0_long),
9716 IWX_DEV_INFO(0x7af0, 0x0090, iwx_2ax_cfg_so_gf_a0),
9717 IWX_DEV_INFO(0x7af0, 0x0098, iwx_2ax_cfg_so_gf_a0),
9718 IWX_DEV_INFO(0x7af0, 0x00b0, iwx_2ax_cfg_so_gf4_a0),
9719 IWX_DEV_INFO(0x7a70, 0x1691, iwx_2ax_cfg_so_gf4_a0), /* killer_1690s */
9720 IWX_DEV_INFO(0x7a70, 0x1692, iwx_2ax_cfg_so_gf4_a0), /* killer_1690i */
9721 IWX_DEV_INFO(0x7af0, 0x0310, iwx_2ax_cfg_so_gf_a0),
9722 IWX_DEV_INFO(0x7af0, 0x0510, iwx_2ax_cfg_so_gf_a0),
9723 IWX_DEV_INFO(0x7af0, 0x0a10, iwx_2ax_cfg_so_gf_a0),
9724 IWX_DEV_INFO(0x7f70, 0x1691, iwx_2ax_cfg_so_gf4_a0), /* killer_1690s */
9725 IWX_DEV_INFO(0x7f70, 0x1692, iwx_2ax_cfg_so_gf4_a0), /* killer_1690i */
9728 IWX_DEV_INFO(0x2726, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9729 IWX_DEV_INFO(0x2726, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9730 IWX_DEV_INFO(0x51f0, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9731 IWX_DEV_INFO(0x51f0, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9732 IWX_DEV_INFO(0x54f0, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9733 IWX_DEV_INFO(0x54f0, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9734 IWX_DEV_INFO(0x7a70, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9735 IWX_DEV_INFO(0x7a70, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9736 IWX_DEV_INFO(0x7af0, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9737 IWX_DEV_INFO(0x7af0, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9738 IWX_DEV_INFO(0x7f70, 0x1671, iwx_2ax_cfg_so_gf_a0), /* killer_1675s */
9739 IWX_DEV_INFO(0x7f70, 0x1672, iwx_2ax_cfg_so_gf_a0), /* killer_1675i */
9772 _IWX_DEV_INFO(IWX_CFG_ANY, 0x1551,
9778 _IWX_DEV_INFO(IWX_CFG_ANY, 0x1552,
9806 _IWX_DEV_INFO(IWX_CFG_ANY, 0x1551,
9812 _IWX_DEV_INFO(IWX_CFG_ANY, 0x1552,
10000 return 0; in iwx_preinit()
10019 printf("%s: hw rev 0x%x, fw %s, pnvm %08x, " in iwx_preinit()
10025 printf("%s: hw rev 0x%x, fw %s, address %s\n", in iwx_preinit()
10032 memset(&ic->ic_sup_rates[IEEE80211_MODE_11A], 0, in iwx_preinit()
10035 return 0; in iwx_preinit()
10048 if (err != 0) in iwx_attach_hook()
10105 for (i = nitems(iwx_dev_info_table) - 1; i >= 0; i--) { in iwx_find_device_cfg()
10159 for (i = 0; i < nitems(iwx_devices); i++) { in iwx_probe()
10197 TASK_INIT(&sc->sc_es_task, 0, iwx_endscan_cb, sc); in iwx_attach()
10200 TASK_INIT(&sc->ba_rx_task, 0, iwx_ba_rx_task, sc); in iwx_attach()
10201 TASK_INIT(&sc->ba_tx_task, 0, iwx_ba_tx_task, sc); in iwx_attach()
10204 error = taskqueue_start_threads(&sc->sc_tq, 1, 0, "iwm_taskq"); in iwx_attach()
10205 if (error != 0) { in iwx_attach()
10212 if (sc->sc_cap_off == 0) { in iwx_attach()
10218 * We disable the RETRY_TIMEOUT register (0x41) to keep in iwx_attach()
10221 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); in iwx_attach()
10231 rid = PCIR_BAR(0); in iwx_attach()
10242 rid = 0; in iwx_attach()
10243 if (pci_alloc_msix(dev, &count) == 0) in iwx_attach()
10247 (rid != 0 ? 0 : RF_SHAREABLE)); in iwx_attach()
10254 if (error != 0) { in iwx_attach()
10260 IWX_WRITE(sc, IWX_CSR_INT_MASK, 0); in iwx_attach()
10261 IWX_WRITE(sc, IWX_CSR_INT, ~0); in iwx_attach()
10262 IWX_WRITE(sc, IWX_CSR_FH_INT_STATUS, ~0); in iwx_attach()
10271 * changed, and now the revision step also includes bit 0-1 (no more in iwx_attach()
10275 sc->sc_hw_rev = (sc->sc_hw_rev & 0xfff0) | in iwx_attach()
10282 sc->sc_integrated = 0; in iwx_attach()
10284 sc->sc_low_latency_xtal = 0; in iwx_attach()
10285 sc->sc_xtal_latency = 0; in iwx_attach()
10286 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10287 sc->sc_uhb_supported = 0; in iwx_attach()
10300 sc->sc_low_latency_xtal = 0; in iwx_attach()
10302 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10303 sc->sc_uhb_supported = 0; in iwx_attach()
10315 sc->sc_low_latency_xtal = 0; in iwx_attach()
10317 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10318 sc->sc_uhb_supported = 0; in iwx_attach()
10332 sc->sc_low_latency_xtal = 0; in iwx_attach()
10334 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10335 sc->sc_uhb_supported = 0; in iwx_attach()
10349 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10350 sc->sc_uhb_supported = 0; in iwx_attach()
10362 sc->sc_integrated = 0; in iwx_attach()
10364 sc->sc_low_latency_xtal = 0; in iwx_attach()
10365 sc->sc_xtal_latency = 0; in iwx_attach()
10366 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10378 sc->sc_tx_with_siso_diversity = 0; in iwx_attach()
10379 sc->sc_uhb_supported = 0; in iwx_attach()
10400 sc->mac_addr_from_csr = 0x380; /* differs on BZ hw generation */ in iwx_attach()
10403 sc->sc_umac_prph_offset = 0x300000; in iwx_attach()
10457 for (txq_i = 0; txq_i < nitems(sc->txq); txq_i++) { in iwx_attach()
10475 CTLFLAG_RWTUN, &sc->sc_debug, 0, "bitmask to control debugging"); in iwx_attach()
10479 CTLFLAG_RW, &iwx_himark, 0, "queues high watermark"); in iwx_attach()
10482 CTLFLAG_RW, &iwx_lomark, 0, "queues low watermark"); in iwx_attach()
10486 CTLFLAG_RD, &sc->qfullmsk, 0, "queue fullmask"); in iwx_attach()
10490 CTLFLAG_RD, &sc->txq[0].queued, 0, "queue 0"); in iwx_attach()
10493 CTLFLAG_RD, &sc->txq[1].queued, 0, "queue 1"); in iwx_attach()
10496 CTLFLAG_RD, &sc->txq[2].queued, 0, "queue 2"); in iwx_attach()
10499 CTLFLAG_RD, &sc->txq[3].queued, 0, "queue 3"); in iwx_attach()
10502 CTLFLAG_RD, &sc->txq[4].queued, 0, "queue 4"); in iwx_attach()
10505 CTLFLAG_RD, &sc->txq[5].queued, 0, "queue 5"); in iwx_attach()
10508 CTLFLAG_RD, &sc->txq[6].queued, 0, "queue 6"); in iwx_attach()
10511 CTLFLAG_RD, &sc->txq[7].queued, 0, "queue 7"); in iwx_attach()
10559 int mcsmap = IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 | in iwx_attach()
10570 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); in iwx_attach()
10571 for (i = 0; i < nitems(sc->sc_rxba_data); i++) { in iwx_attach()
10575 for (j = 0; j < nitems(rxba->entries); j++) in iwx_attach()
10581 if (config_intrhook_establish(&sc->sc_preinit_hook) != 0) { in iwx_attach()
10587 return (0); in iwx_attach()
10590 while (--txq_i >= 0) in iwx_attach()
10618 for (txq_i = 0; txq_i < nitems(sc->txq); txq_i++) in iwx_detach()
10644 return (0); in iwx_detach()
10751 return (0); in iwx_suspend()
10761 * We disable the RETRY_TIMEOUT register (0x41) to keep in iwx_resume()
10764 pci_write_config(dev, PCI_CFG_RETRY_TIMEOUT, 0x00, 1); in iwx_resume()
10778 return (0); in iwx_resume()
10789 if ((ic->ic_flags_ext & IEEE80211_FEXT_BGSCAN) == 0) in iwx_scan_start()
10824 #if 0 in iwx_set_channel()
10846 return 0; in iwx_wme_update()
10885 return (0); in iwx_transmit()
10924 return (0); in iwx_ampdu_rx_start()
10941 * If we return 0 here then the firmware will set up the state but net80211
10951 * @returns 0 so net80211 doesn't send the BA action frame to establish A-MPDU.
10976 return (0); in iwx_addba_request()
10984 return 0; in iwx_addba_response()
11009 *keyix = 0; /* NB: use key index 0 for ucast key */ in iwx_key_alloc()
11015 return (0); in iwx_key_alloc()
11041 memset(&cmd, 0, sizeof(cmd)); in iwx_key_set()
11050 id = 0; /* net80211 currently only supports unicast key 0 */ in iwx_key_set()
11066 cmd.common.key_offset = 0; in iwx_key_set()
11131 MODULE_PNP_INFO("U16:device;D:#;T:vendor=0x8086", pci, iwx_pci_driver,