Lines Matching +full:0 +full:x6e
58 #define IWN_HIADDR(paddr) (((paddr) >> 32) & 0xf)
61 #define IWN_HIADDR(paddr) (0)
67 #define IWN_HW_IF_CONFIG 0x000
68 #define IWN_INT_COALESCING 0x004
69 #define IWN_INT_PERIODIC 0x005 /* use IWN_WRITE_1 */
70 #define IWN_INT 0x008
71 #define IWN_INT_MASK 0x00c
72 #define IWN_FH_INT 0x010
73 #define IWN_GPIO_IN 0x018 /* read external chip pins */
74 #define IWN_RESET 0x020
75 #define IWN_GP_CNTRL 0x024
76 #define IWN_HW_REV 0x028
77 #define IWN_EEPROM 0x02c
78 #define IWN_EEPROM_GP 0x030
79 #define IWN_OTP_GP 0x034
80 #define IWN_GIO 0x03c
81 #define IWN_GP_UCODE 0x048
82 #define IWN_GP_DRIVER 0x050
83 #define IWN_UCODE_GP1 0x054
84 #define IWN_UCODE_GP1_SET 0x058
85 #define IWN_UCODE_GP1_CLR 0x05c
86 #define IWN_UCODE_GP2 0x060
87 #define IWN_LED 0x094
88 #define IWN_DRAM_INT_TBL 0x0a0
89 #define IWN_SHADOW_REG_CTRL 0x0a8
90 #define IWN_GIO_CHICKEN 0x100
91 #define IWN_ANA_PLL 0x20c
92 #define IWN_HW_REV_WA 0x22c
93 #define IWN_DBG_HPET_MEM 0x240
94 #define IWN_DBG_LINK_PWR_MGMT 0x250
96 #define IWN_MEM_RADDR 0x40c
97 #define IWN_MEM_WADDR 0x410
98 #define IWN_MEM_WDATA 0x418
99 #define IWN_MEM_RDATA 0x41c
100 #define IWN_TARG_MBX_C 0x430
101 #define IWN_PRPH_WADDR 0x444
102 #define IWN_PRPH_RADDR 0x448
103 #define IWN_PRPH_WDATA 0x44c
104 #define IWN_PRPH_RDATA 0x450
105 #define IWN_HBUS_TARG_WRPTR 0x460
110 #define IWN_FH_TFBD_CTRL0(qid) (0x1900 + (qid) * 8)
111 #define IWN_FH_TFBD_CTRL1(qid) (0x1904 + (qid) * 8)
112 #define IWN_FH_KW_ADDR 0x197c
113 #define IWN_FH_SRAM_ADDR(qid) (0x19a4 + (qid) * 4)
114 #define IWN_FH_CBBC_QUEUE(qid) (0x19d0 + (qid) * 4)
115 #define IWN_FH_STATUS_WPTR 0x1bc0
116 #define IWN_FH_RX_BASE 0x1bc4
117 #define IWN_FH_RX_WPTR 0x1bc8
118 #define IWN_FH_RX_CONFIG 0x1c00
119 #define IWN_FH_RX_STATUS 0x1c44
120 #define IWN_FH_TX_CONFIG(qid) (0x1d00 + (qid) * 32)
121 #define IWN_FH_TXBUF_STATUS(qid) (0x1d08 + (qid) * 32)
122 #define IWN_FH_TX_CHICKEN 0x1e98
123 #define IWN_FH_TX_STATUS 0x1eb0
128 #define IWN_SCHED_BASE 0xa02c00
129 #define IWN_SCHED_SRAM_ADDR (IWN_SCHED_BASE + 0x000)
130 #define IWN5000_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x008)
131 #define IWN4965_SCHED_DRAM_ADDR (IWN_SCHED_BASE + 0x010)
132 #define IWN5000_SCHED_TXFACT (IWN_SCHED_BASE + 0x010)
133 #define IWN4965_SCHED_TXFACT (IWN_SCHED_BASE + 0x01c)
134 #define IWN4965_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x064 + (qid) * 4)
135 #define IWN5000_SCHED_QUEUE_RDPTR(qid) (IWN_SCHED_BASE + 0x068 + (qid) * 4)
136 #define IWN4965_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0d0)
137 #define IWN4965_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x0e4)
138 #define IWN5000_SCHED_QCHAIN_SEL (IWN_SCHED_BASE + 0x0e8)
139 #define IWN4965_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x104 + (qid) * 4)
140 #define IWN5000_SCHED_INTR_MASK (IWN_SCHED_BASE + 0x108)
141 #define IWN5000_SCHED_QUEUE_STATUS(qid) (IWN_SCHED_BASE + 0x10c + (qid) * 4)
142 #define IWN5000_SCHED_AGGR_SEL (IWN_SCHED_BASE + 0x248)
147 #define IWN4965_SCHED_CTX_OFF 0x380
149 #define IWN4965_SCHED_QUEUE_OFFSET(qid) (0x380 + (qid) * 8)
150 #define IWN4965_SCHED_TRANS_TBL(qid) (0x500 + (qid) * 2)
151 #define IWN5000_SCHED_CTX_OFF 0x600
153 #define IWN5000_SCHED_QUEUE_OFFSET(qid) (0x600 + (qid) * 8)
154 #define IWN5000_SCHED_TRANS_TBL(qid) (0x7e0 + (qid) * 2)
159 #define IWN_APMG_CLK_CTRL 0x3000
160 #define IWN_APMG_CLK_EN 0x3004
161 #define IWN_APMG_CLK_DIS 0x3008
162 #define IWN_APMG_PS 0x300c
163 #define IWN_APMG_DIGITAL_SVR 0x3058
164 #define IWN_APMG_ANALOG_SVR 0x306c
165 #define IWN_APMG_PCI_STT 0x3010
166 #define IWN_BSM_WR_CTRL 0x3400
167 #define IWN_BSM_WR_MEM_SRC 0x3404
168 #define IWN_BSM_WR_MEM_DST 0x3408
169 #define IWN_BSM_WR_DWCOUNT 0x340c
170 #define IWN_BSM_DRAM_TEXT_ADDR 0x3490
171 #define IWN_BSM_DRAM_TEXT_SIZE 0x3494
172 #define IWN_BSM_DRAM_DATA_ADDR 0x3498
173 #define IWN_BSM_DRAM_DATA_SIZE 0x349c
174 #define IWN_BSM_SRAM_BASE 0x3800
187 #define IWN_INT_PERIODIC_DIS 0x00
188 #define IWN_INT_PERIODIC_ENA 0xff
194 #define IWN_FW_TEXT_BASE 0x00000000
195 #define IWN_FW_DATA_BASE 0x00800000
198 #define IWN_RESET_NEVO (1 << 0)
205 #define IWN_GP_CNTRL_MAC_ACCESS_ENA (1 << 0)
206 #define IWN_GP_CNTRL_MAC_CLOCK_READY (1 << 0)
220 #define IWN_GP_DRIVER_RADIO_3X3_HYB (0 << 0)
221 #define IWN_GP_DRIVER_RADIO_2X2_HYB (1 << 0)
222 #define IWN_GP_DRIVER_RADIO_2X2_IPA (2 << 0)
226 #define IWN_GP_DRIVER_NONE 0
236 #define IWN_LED_OFF 0x00000038
237 #define IWN_LED_ON 0x00000078
240 #define IWN_LED_STATIC_ON 0
244 #define IWN_LED_UNIT 0x1388 /* 5 ms */
261 {0, 33, 33},
270 #define IWN_ANA_PLL_INIT 0x00880300
280 #define IWN_INT_ALIVE (1 << 0)
304 (IWN_FH_INT_TX_CHNL(0) | IWN_FH_INT_TX_CHNL(1))
306 (IWN_FH_INT_RX_CHNL(0) | IWN_FH_INT_RX_CHNL(1) | IWN_FH_INT_HI_PRIOR)
309 #define IWN_FH_TX_CONFIG_DMA_PAUSE 0
338 #define IWN_EEPROM_READ_VALID (1 << 0)
342 #define IWN_EEPROM_GP_IF_OWNER 0x00000180
351 #define IWN4965_TXQ_STATUS_ACTIVE 0x0007fc01
352 #define IWN4965_TXQ_STATUS_INACTIVE 0x0007fc00
355 #define IWN5000_TXQ_STATUS_ACTIVE 0x00ff0018
356 #define IWN5000_TXQ_STATUS_INACTIVE 0x00ff0010
366 #define IWN_APMG_PS_PWR_SRC_VMAIN 0
372 #define IWN_APMG_DIGITAL_SVR_VOLTAGE(x) (((x) & 0xf) << 5)
374 IWN_APMG_DIGITAL_SVR_VOLTAGE(0xf)
441 uint8_t flags; /* 0:5 reserved, 6 abort, 7 internal */
444 /* 0:4 TX queue id - 5:6 reserved - 7 unsolicited RX
449 #define IWN_RX_DESC_QID_MSK 0x1F
450 #define IWN_UNSOLICITED_RX_NOTIF 0x80
453 #define IWN_STATE_CHANGE_HW_CARD_DISABLED 0x01
454 #define IWN_STATE_CHANGE_SW_CARD_DISABLED 0x02
455 #define IWN_STATE_CHANGE_CT_CARD_DISABLED 0x04
456 #define IWN_STATE_CHANGE_RXON_CARD_DISABLED 0x10
459 #define IWN_RX_NO_CRC_ERR (1 << 0)
501 #define IWN_CMD_WIPAN_PARAMS 0xb2
502 #define IWN_CMD_WIPAN_RXON 0xb3
503 #define IWN_CMD_WIPAN_RXON_TIMING 0xb4
504 #define IWN_CMD_WIPAN_RXON_ASSOC 0xb6
505 #define IWN_CMD_WIPAN_QOS_PARAM 0xb7
506 #define IWN_CMD_WIPAN_WEPKEY 0xb8
507 #define IWN_CMD_WIPAN_P2P_CHANNEL_SWITCH 0xb9
508 #define IWN_CMD_WIPAN_NOA_NOTIFICATION 0xbc
509 #define IWN_CMD_WIPAN_DEACTIVATION_COMPLETE 0xbd
518 * Structure for IWN_CMD_GET_STATISTICS = (0x9c) 156
522 * The response is in the same format as IWN_BEACON_STATISTICS (0x9d) 157.
530 * does not affect the response to the IWN_CMD_GET_STATISTICS 0x9c itself.
534 #define IWN_STATS_CONF_CLEAR_STATS htole32(0x1)
535 #define IWN_STATS_CONF_DISABLE_NOTIF htole32(0x2)
539 #define IWN_ANT_A (1 << 0)
566 #define IWN_RXCHAIN_DRIVER_FORCE (1 << 0)
578 #define IWN_RXON_24GHZ (1 << 0)
591 /* 0=legacy, 1=pure40, 2=mixed */
598 #define IWN_FILTER_PROMISC (1 << 0)
659 #define IWN_EDCA_UPDATE (1 << 0)
685 #define IWN_NODE_UPDATE (1 << 0)
692 #define IWN_ID_BSS 0
702 #define IWN_FLAG_SET_KEY (1 << 0)
768 #define IWN_RFLAG_RATE 0xff
769 #define IWN_RFLAG_RATE_MCS 0x1f
770 #define IWN_RFLAG_HT40_DUP 0x20
785 #define IWN_TX_NEED_PROTECTION (1 << 0) /* 5000 only */
814 #define IWN_LIFETIME_INFINITE 0xffffffff
859 #define IWN_WIMAX_COEX_STA_TABLE_VALID (1 << 0)
898 #define IWN_PS_ALLOW_SLEEP (1 << 0)
945 #define IWN_CHAN_PASSIVE (0 << 0)
946 #define IWN_CHAN_ACTIVE (1 << 0)
956 #define IWN_SCAN_CRC_TH_DISABLED 0
958 #define IWN_SCAN_CRC_TH_NEVER htole16(0xffff)
1007 #define IWN_GOOD_CRC_TH_DISABLED 0
1009 #define IWN_GOOD_CRC_TH_NEVER htole16(0xffff)
1027 #define IWN5000_TXPOWER_AUTO 0x7f
1040 #define IWN_BT_COEX_CHAN_ANN (1 << 0)
1060 #define IWN_BT_FLAG_COEX6000_MODE_DISABLED 0
1138 #define IWN_SENSITIVITY_DEFAULTTBL 0
1268 #define IWN_MEASUREMENT_BASIC (1 << 0)
1288 #define IWN_UCODE_RUNTIME 0
1315 #define IWN_TX_STATUS_MSK 0x000000ff
1316 #define IWN_TX_STATUS_DELAY_MSK 0x00000040
1317 #define IWN_TX_STATUS_ABORT_MSK 0x00000080
1318 #define IWN_TX_PACKET_MODE_MSK 0x0000ff00
1319 #define IWN_TX_FIFO_NUMBER_MSK 0x00070000
1320 #define IWN_TX_RESERVED 0x00780000
1321 #define IWN_TX_POWER_PA_DETECT_MSK 0x7f800000
1322 #define IWN_TX_ABORT_REQUIRED_MSK 0x80000000
1325 #define IWN_TX_STATUS_SUCCESS 0x01
1326 #define IWN_TX_STATUS_DIRECT_DONE 0x02
1329 #define IWN_TX_STATUS_POSTPONE_DELAY 0x40
1330 #define IWN_TX_STATUS_POSTPONE_FEW_BYTES 0x41
1331 #define IWN_TX_STATUS_POSTPONE_BT_PRIO 0x42
1332 #define IWN_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
1333 #define IWN_TX_STATUS_POSTPONE_CALC_TTAK 0x44
1336 #define IWN_TX_FAIL 0x80 /* all failures have 0x80 set */
1337 #define IWN_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
1338 #define IWN_TX_FAIL_SHORT_LIMIT 0x82 /* too many RTS retries */
1339 #define IWN_TX_FAIL_LONG_LIMIT 0x83 /* too many retries */
1340 #define IWN_TX_FAIL_FIFO_UNDERRRUN 0x84 /* tx fifo not kept running */
1341 #define IWN_TX_STATUS_FAIL_DRAIN_FLOW 0x85
1342 #define IWN_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
1343 #define IWN_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
1344 #define IWN_TX_FAIL_DEST_IN_PS 0x88 /* sta found in power save */
1345 #define IWN_TX_STATUS_FAIL_HOST_ABORTED 0x89
1346 #define IWN_TX_STATUS_FAIL_BT_RETRY 0x8a
1347 #define IWN_TX_FAIL_STA_INVALID 0x8b /* XXX STA invalid (???) */
1348 #define IWN_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
1349 #define IWN_TX_STATUS_FAIL_TID_DISABLE 0x8d
1350 #define IWN_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
1351 #define IWN_TX_STATUS_FAIL_INSUFFICIENT_CF_POLL 0x8f
1352 #define IWN_TX_FAIL_TX_LOCKED 0x90 /* waiting to see traffic */
1353 #define IWN_TX_STATUS_FAIL_NO_BEACON_ON_RADAR 0x91
1362 #define IWN_AGG_TX_STATE_TRANSMITTED 0x00
1363 #define IWN_AGG_TX_STATE_UNDERRUN_MSK 0x01
1364 #define IWN_AGG_TX_STATE_FEW_BYTES_MSK 0x04
1365 #define IWN_AGG_TX_STATE_ABORT_MSK 0x08
1367 #define IWN_AGG_TX_STATE_LAST_SENT_TTL_MSK 0x10
1368 #define IWN_AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK 0x20
1370 #define IWN_AGG_TX_STATE_SCD_QUERY_MSK 0x80
1372 #define IWN_AGG_TX_STATE_TEST_BAD_CRC32_MSK 0x100
1374 #define IWN_AGG_TX_STATE_RESPONSE_MSK 0x1ff
1375 #define IWN_AGG_TX_STATE_DUMP_TX_MSK 0x200
1376 #define IWN_AGG_TX_STATE_DELAY_TX_MSK 0x400
1378 #define IWN_AGG_TX_STATUS_MSK 0x00000fff
1379 #define IWN_AGG_TX_TRY_MSK 0x0000f000
1394 #define IWN_AGG_TX_STATE_TRY_CNT_MSK 0xf000
1398 #define IWN_AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1425 uint8_t ratid; /* tid (0:3), sta_id (4:7) */
1476 * High-throughput (HT) rate format for bits 7:0 (bit 8 must be "1"):
1477 * 2-0: 0) 6 Mbps
1486 * 4-3: 0) Single stream (SISO)
1490 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
1492 * Legacy OFDM rate format for bits 7:0 (bit 8 must be "0", bit 9 "0"):
1493 * 3-0: 0xD) 6 Mbps
1494 * 0xF) 9 Mbps
1495 * 0x5) 12 Mbps
1496 * 0x7) 18 Mbps
1497 * 0x9) 24 Mbps
1498 * 0xB) 36 Mbps
1499 * 0x1) 48 Mbps
1500 * 0x3) 54 Mbps
1502 * Legacy CCK rate format for bits 7:0 (bit 8 must be "0", bit 9 "1"):
1503 * 6-0: 10) 1 Mbps
1526 #if 0
1558 #define IWN_MEASUREMENT_START 0
1575 #define IWN_MEASUREMENT_OK 0
1762 uint32_t zero; /* Always 0, to differentiate from legacy. */
1764 #define IWN_FW_SIGNATURE 0x0a4c5749 /* "IWL\n" */
1768 #define IWN_FW_API(x) (((x) >> 8) & 0xff)
1841 IWN_UCODE_TLV_FLAGS_PAN = (1 << 0),
1865 #define IWN_EEPROM_MAC 0x015
1866 #define IWN_EEPROM_SKU_CAP 0x045
1867 #define IWN_EEPROM_RFCFG 0x048
1868 #define IWN4965_EEPROM_DOMAIN 0x060
1869 #define IWN4965_EEPROM_BAND1 0x063
1870 #define IWN5000_EEPROM_REG 0x066
1871 #define IWN5000_EEPROM_CAL 0x067
1872 #define IWN4965_EEPROM_BAND2 0x072
1873 #define IWN4965_EEPROM_BAND3 0x080
1874 #define IWN4965_EEPROM_BAND4 0x08d
1875 #define IWN4965_EEPROM_BAND5 0x099
1876 #define IWN4965_EEPROM_BAND6 0x0a0
1877 #define IWN4965_EEPROM_BAND7 0x0a8
1878 #define IWN4965_EEPROM_MAXPOW 0x0e8
1879 #define IWN4965_EEPROM_VOLTAGE 0x0e9
1880 #define IWN4965_EEPROM_BANDS 0x0ea
1882 #define IWN5000_EEPROM_NO_HT40 0x000
1883 #define IWN5000_EEPROM_DOMAIN 0x001
1884 #define IWN5000_EEPROM_BAND1 0x004
1885 #define IWN5000_EEPROM_BAND2 0x013
1886 #define IWN5000_EEPROM_BAND3 0x021
1887 #define IWN5000_EEPROM_BAND4 0x02e
1888 #define IWN5000_EEPROM_BAND5 0x03a
1889 #define IWN5000_EEPROM_BAND6 0x041
1890 #define IWN6000_EEPROM_BAND6 0x040
1891 #define IWN5000_EEPROM_BAND7 0x049
1892 #define IWN6000_EEPROM_ENHINFO 0x054
1893 #define IWN5000_EEPROM_CRYSTAL 0x128
1894 #define IWN5000_EEPROM_TEMP 0x12a
1895 #define IWN5000_EEPROM_VOLT 0x12b
1903 #define IWN_RFCFG_TYPE(x) (((x) >> 0) & 0x3)
1904 #define IWN_RFCFG_STEP(x) (((x) >> 2) & 0x3)
1905 #define IWN_RFCFG_DASH(x) (((x) >> 4) & 0x3)
1906 #define IWN_RFCFG_TXANTMSK(x) (((x) >> 8) & 0xf)
1907 #define IWN_RFCFG_RXANTMSK(x) (((x) >> 12) & 0xf)
1911 #define IWN_EEPROM_CHAN_VALID (1 << 0)
1921 #define IWN_ENHINFO_VALID 0x01
1922 #define IWN_ENHINFO_5GHZ 0x02
1923 #define IWN_ENHINFO_OFDM 0x04
1924 #define IWN_ENHINFO_HT40 0x08
1925 #define IWN_ENHINFO_HTAP 0x10
1926 #define IWN_ENHINFO_RES1 0x20
1927 #define IWN_ENHINFO_RES2 0x40
1928 #define IWN_ENHINFO_COMMON 0x80
2034 2, 3, 1, 0,
2045 #define IWN_RIDX_CCK1 0
2049 #define IWN_POWERSAVE_LVL_NONE 0
2063 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d, 0x3c, 0x3c,
2064 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39, 0x39, 0x38,
2065 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35, 0x35, 0x35,
2066 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32, 0x31, 0x31,
2067 0x31, 0x30, 0x30, 0x30, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x04,
2068 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01, 0x01, 0x01,
2069 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2071 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
2072 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2076 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3e, 0x3e, 0x3e, 0x3d, 0x3d, 0x3d,
2077 0x3c, 0x3c, 0x3c, 0x3b, 0x3b, 0x3b, 0x3a, 0x3a, 0x3a, 0x39, 0x39,
2078 0x39, 0x38, 0x38, 0x38, 0x37, 0x37, 0x37, 0x36, 0x36, 0x36, 0x35,
2079 0x35, 0x35, 0x34, 0x34, 0x34, 0x33, 0x33, 0x33, 0x32, 0x32, 0x32,
2080 0x31, 0x31, 0x31, 0x30, 0x30, 0x30, 0x25, 0x25, 0x25, 0x24, 0x24,
2081 0x24, 0x23, 0x23, 0x23, 0x22, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16,
2082 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x14, 0x13, 0x13, 0x13,
2083 0x12, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x05, 0x05,
2084 0x05, 0x04, 0x04, 0x04, 0x03, 0x03, 0x03, 0x02, 0x02, 0x02, 0x01,
2085 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
2093 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2094 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2095 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2096 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2097 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2098 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2099 0x6e, 0x68, 0x62, 0x61, 0x60, 0x5f, 0x5e, 0x5d, 0x5c, 0x5b, 0x5a,
2100 0x59, 0x58, 0x57, 0x56, 0x55, 0x54, 0x53, 0x52, 0x51, 0x50, 0x4f,
2101 0x4e, 0x4d, 0x4c, 0x4b, 0x4a, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44,
2102 0x43, 0x42, 0x41, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b
2106 0x7b, 0x75, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2107 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2108 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2109 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2110 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2111 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2112 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62,
2113 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68,
2114 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e, 0x68, 0x62, 0x6e,
2115 0x68, 0x62, 0x6e, 0x68, 0x62, 0x5d, 0x58, 0x53, 0x4e
2131 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2132 { 200, 500, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 1 */
2133 { 200, 300, { 1, 2, 2, 2, -1 }, 0 }, /* PS level 2 */
2134 { 50, 100, { 2, 2, 2, 2, -1 }, 0 }, /* PS level 3 */
2140 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2141 { 200, 500, { 1, 2, 3, 4, 4 }, 0 }, /* PS level 1 */
2142 { 200, 300, { 1, 2, 3, 4, 7 }, 0 }, /* PS level 2 */
2143 { 50, 100, { 2, 4, 6, 7, 9 }, 0 }, /* PS level 3 */
2149 { 0, 0, { 0, 0, 0, 0, 0 }, 0 }, /* CAM */
2150 { 200, 500, { 1, 2, 3, 4, -1 }, 0 }, /* PS level 1 */
2151 { 200, 300, { 2, 4, 6, 7, -1 }, 0 }, /* PS level 2 */
2152 { 50, 100, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 3 */
2153 { 50, 25, { 2, 7, 9, 9, -1 }, 0 }, /* PS level 4 */
2154 { 25, 25, { 4, 7, 10, 10, -1 }, 0 } /* PS level 5 */
2275 1, 0, 0, 1, 2, 2, 3, 3, 7, 7, 7, 7, 7, 7, 7, 7, 3
2280 { 0x04, 0x03, 0x00, 0x00 },
2281 { 0x04, 0x03, 0x00, 0x03 },
2282 { 0x04, 0x03, 0x00, 0x03 },
2283 { 0x04, 0x03, 0x00, 0x03 },
2284 { 0x04, 0x03, 0x00, 0x00 },
2285 { 0x04, 0x03, 0x00, 0x07 },
2286 { 0x04, 0x03, 0x00, 0x00 },
2287 { 0x04, 0x03, 0x00, 0x03 },
2288 { 0x04, 0x03, 0x00, 0x03 },
2289 { 0x04, 0x03, 0x00, 0x00 },
2290 { 0x06, 0x03, 0x00, 0x07 },
2291 { 0x04, 0x03, 0x00, 0x00 },
2292 { 0x06, 0x06, 0x00, 0x03 },
2293 { 0x04, 0x03, 0x00, 0x07 },
2294 { 0x04, 0x03, 0x00, 0x00 },
2295 { 0x04, 0x03, 0x00, 0x00 }
2350 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
2354 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \