Lines Matching +full:0 +full:x00000000 +full:- +full:0 +full:x0fffffff
10 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
73 * BEGIN iwl-csr.h
81 * low power states due to driver-invoked device resets
82 * (e.g. IWM_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
94 #define IWM_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
95 #define IWM_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
96 #define IWM_CSR_INT (0x008) /* host interrupt status/ack */
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
98 #define IWM_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
99 #define IWM_CSR_GPIO_IN (0x018) /* read external chip pins */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
101 #define IWM_CSR_GP_CNTRL (0x024)
104 #define IWM_CSR_INT_PERIODIC_REG (0x005)
109 * 31-16: Reserved
110 * 15-4: Type of device: see IWM_CSR_HW_REV_TYPE_xxx definitions
111 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
112 * 1-0: "Dash" (-) value, as in A-1, etc.
114 #define IWM_CSR_HW_REV (0x028)
117 * EEPROM and OTP (one-time-programmable) memory reads
122 #define IWM_CSR_EEPROM_REG (0x02c)
123 #define IWM_CSR_EEPROM_GP (0x030)
124 #define IWM_CSR_OTP_GP_REG (0x034)
126 #define IWM_CSR_GIO_REG (0x03C)
127 #define IWM_CSR_GP_UCODE_REG (0x048)
128 #define IWM_CSR_GP_DRIVER_REG (0x050)
131 * UCODE-DRIVER GP (general purpose) mailbox registers.
134 #define IWM_CSR_UCODE_DRV_GP1 (0x054)
135 #define IWM_CSR_UCODE_DRV_GP1_SET (0x058)
136 #define IWM_CSR_UCODE_DRV_GP1_CLR (0x05c)
137 #define IWM_CSR_UCODE_DRV_GP2 (0x060)
139 #define IWM_CSR_MBOX_SET_REG (0x088)
140 #define IWM_CSR_MBOX_SET_REG_OS_ALIVE 0x20
142 #define IWM_CSR_LED_REG (0x094)
143 #define IWM_CSR_DRAM_INT_TBL_REG (0x0A0)
144 #define IWM_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
148 #define IWM_CSR_GIO_CHICKEN_BITS (0x100)
150 /* Analog phase-lock-loop configuration */
151 #define IWM_CSR_ANA_PLL_CFG (0x20c)
158 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
159 * 1-0: "Dash" (-) value, as in C-1, etc.
161 #define IWM_CSR_HW_REV_WA_REG (0x22C)
163 #define IWM_CSR_DBG_HPET_MEM_REG (0x240)
164 #define IWM_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
167 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
168 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
169 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
170 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
171 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
172 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
173 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
174 #define IWM_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
176 #define IWM_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
183 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
184 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
185 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
186 #define IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
187 #define IWM_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
188 #define IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
189 #define IWM_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
191 #define IWM_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
192 #define IWM_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
199 #define IWM_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
206 #define IWM_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
222 #define IWM_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
224 #define IWM_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
234 #define IWM_CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
235 #define IWM_CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
236 #define IWM_CSR_GPIO_IN_VAL_VMAIN_PWR_SRC (0x00000200)
239 #define IWM_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
240 #define IWM_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
241 #define IWM_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
242 #define IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
243 #define IWM_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
244 #define IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
250 * Indicates state of (platform's) hardware RF-Kill switch
251 * 26-24: POWER_SAVE_TYPE
252 * Indicates current power-saving mode:
253 * 000 -- No power saving
254 * 001 -- MAC power-down
255 * 010 -- PHY (radio) power-down
256 * 011 -- Error
257 * 9-6: SYS_CONFIG
261 * Indicates MAC is entering a power-saving sleep power-down.
262 * Not a good time to access device-internal resources.
265 * access to device-internal resources. Host must wait for
266 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
271 * 0: MAC_CLOCK_READY
276 * init or post-power-down restore of internal SRAM memory.
279 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
281 * NOTE: After device reset, this bit remains "0" until host sets
284 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
285 #define IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
286 #define IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
287 #define IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
289 #define IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
291 #define IWM_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
292 #define IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
293 #define IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
297 #define IWM_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
298 #define IWM_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
304 IWM_SILICON_A_STEP = 0,
309 #define IWM_CSR_HW_REV_TYPE_MSK (0x000FFF0)
310 #define IWM_CSR_HW_REV_TYPE_5300 (0x0000020)
311 #define IWM_CSR_HW_REV_TYPE_5350 (0x0000030)
312 #define IWM_CSR_HW_REV_TYPE_5100 (0x0000050)
313 #define IWM_CSR_HW_REV_TYPE_5150 (0x0000040)
314 #define IWM_CSR_HW_REV_TYPE_1000 (0x0000060)
315 #define IWM_CSR_HW_REV_TYPE_6x00 (0x0000070)
316 #define IWM_CSR_HW_REV_TYPE_6x50 (0x0000080)
317 #define IWM_CSR_HW_REV_TYPE_6150 (0x0000084)
318 #define IWM_CSR_HW_REV_TYPE_6x05 (0x00000B0)
321 #define IWM_CSR_HW_REV_TYPE_2x30 (0x00000C0)
322 #define IWM_CSR_HW_REV_TYPE_2x00 (0x0000100)
323 #define IWM_CSR_HW_REV_TYPE_105 (0x0000110)
324 #define IWM_CSR_HW_REV_TYPE_135 (0x0000120)
325 #define IWM_CSR_HW_REV_TYPE_7265D (0x0000210)
326 #define IWM_CSR_HW_REV_TYPE_NONE (0x00001F0)
329 #define IWM_CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
330 #define IWM_CSR_EEPROM_REG_BIT_CMD (0x00000002)
331 #define IWM_CSR_EEPROM_REG_MSK_ADDR (0x0000FFFC)
332 #define IWM_CSR_EEPROM_REG_MSK_DATA (0xFFFF0000)
335 #define IWM_CSR_EEPROM_GP_VALID_MSK (0x00000007) /* signature */
336 #define IWM_CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
337 #define IWM_CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP (0x00000000)
338 #define IWM_CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP (0x00000001)
339 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K (0x00000002)
340 #define IWM_CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K (0x00000004)
342 /* One-time-programmable memory general purpose reg */
343 #define IWM_CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
344 #define IWM_CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
345 #define IWM_CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK (0x00100000) /* bit 20 */
346 #define IWM_CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK (0x00200000) /* bit 21 */
349 #define IWM_CSR_GP_REG_POWER_SAVE_STATUS_MSK (0x03000000) /* bit 24/25 */
350 #define IWM_CSR_GP_REG_NO_POWER_SAVE (0x00000000)
351 #define IWM_CSR_GP_REG_MAC_POWER_SAVE (0x01000000)
352 #define IWM_CSR_GP_REG_PHY_POWER_SAVE (0x02000000)
353 #define IWM_CSR_GP_REG_POWER_SAVE_ERROR (0x03000000)
357 #define IWM_CSR_GIO_REG_VAL_L0S_ENABLED (0x00000002)
360 * UCODE-DRIVER GP (general purpose) mailbox register 1
371 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
378 * 0: MAC_SLEEP
379 * uCode sets this when preparing a power-saving power-down.
380 * uCode resets this when power-up is complete and SRAM is sane.
384 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
387 #define IWM_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
388 #define IWM_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
389 #define IWM_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
390 #define IWM_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
391 #define IWM_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
394 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK (0x00000003)
395 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB (0x00000000)
396 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB (0x00000001)
397 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA (0x00000002)
398 #define IWM_CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6 (0x00000004)
399 #define IWM_CSR_GP_DRIVER_REG_BIT_6050_1x2 (0x00000008)
401 #define IWM_CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER (0x00000080)
404 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
405 #define IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
408 #define IWM_CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
409 #define IWM_CSR_LED_REG_TURN_ON (0x60)
410 #define IWM_CSR_LED_REG_TURN_OFF (0x20)
413 #define IWM_CSR50_ANA_PLL_CFG_VAL (0x00880300)
416 #define IWM_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
424 #define IWM_CSR_SECURE_BOOT_CONFIG_ADDR (0x100)
425 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_BURNED_IN_OTP 0x00000001
426 #define IWM_CSR_SECURE_BOOT_CONFIG_INSPECTOR_NOT_REQ 0x00000002
427 #define IWM_CSR_SECURE_BOOT_CPU1_STATUS_ADDR (0x100)
428 #define IWM_CSR_SECURE_BOOT_CPU2_STATUS_ADDR (0x100)
429 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS 0x00000003
430 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED 0x00000002
431 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_SUCCESS 0x00000004
432 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_VERF_FAIL 0x00000008
433 #define IWM_CSR_SECURE_BOOT_CPU_STATUS_SIGN_VERF_FAIL 0x00000010
435 #define IWM_FH_UCODE_LOAD_STATUS 0x1af0
437 #define IWM_FH_MEM_TB_MAX_LENGTH 0x20000
441 #define IWM_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
444 #define IWM_RFH_Q0_FRBDCB_WIDX 0xA08080
446 /* Write index table - shadow registers */
447 #define IWM_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
450 #define IWM_RFH_Q0_FRBDCB_RIDX 0xA080C0
453 #define IWM_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
456 #define IWM_RFH_Q0_URBDCB_WIDX 0xA08180
458 #define IWM_RFH_Q0_URBDCB_VAID 0xA081C0
461 #define IWM_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
464 #define IWM_RFH_Q0_ORB_WPTR_LSB 0xA08280
466 #define IWM_RFH_RBDBUF_RBD0_LSB 0xA08300
488 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
490 #define IWM_RFH_GEN_STATUS 0xA09808
491 #define IWM_RFH_GEN_STATUS_GEN3 0xA07824
497 #define IWM_RFH_RXF_DMA_CFG 0xA09820
498 #define IWM_RFH_RXF_DMA_CFG_GEN3 0xA07880
500 #define IWM_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
502 #define IWM_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
503 #define IWM_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
504 #define IWM_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
505 #define IWM_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
506 #define IWM_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWM_RFH_RXF_DMA_RB_SIZE_POS)
507 #define IWM_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWM_RFH_RXF_DMA_RB_SIZE_POS)
508 #define IWM_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWM_RFH_RXF_DMA_RB_SIZE_POS)
509 #define IWM_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWM_RFH_RXF_DMA_RB_SIZE_POS)
510 #define IWM_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWM_RFH_RXF_DMA_RB_SIZE_POS)
511 #define IWM_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWM_RFH_RXF_DMA_RB_SIZE_POS)
513 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
515 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
516 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
517 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
518 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
519 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
520 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
521 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
522 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
523 #define IWM_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWM_RFH_RXF_DMA_RBDCB_SIZE_POS)
524 #define IWM_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
527 #define IWM_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
528 #define IWM_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
529 #define IWM_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
532 #define IWM_RFH_RXF_RXQ_ACTIVE 0xA0980C
534 #define IWM_RFH_GEN_CFG 0xA09800
535 #define IWM_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)
537 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
538 #define IWM_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
539 /* the driver assumes everywhere that the default RXQ is 0 */
540 #define IWM_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
544 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR 0x1e78
545 #define IWM_LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR 0x1e7c
547 #define IWM_LMPM_SECURE_CPU1_HDR_MEM_SPACE 0x420000
548 #define IWM_LMPM_SECURE_CPU2_HDR_MEM_SPACE 0x420400
553 #define IWM_FW_MEM_EXTENDED_START 0x40000
554 #define IWM_FW_MEM_EXTENDED_END 0x57FFF
557 #define IWM_LMPM_CHICK 0xa01ff8
558 #define IWM_LMPM_CHICK_EXTENDED_ADDR_SPACE 0x01
560 #define IWM_FH_TCSR_0_REG0 (0x1D00)
563 * HBUS (Host-side Bus)
567 * may be powered-down.
577 #define IWM_HBUS_BASE (0x400)
584 * data registers auto-increment the address by one dword.
586 * 0-31: memory address within device
588 #define IWM_HBUS_TARG_MEM_RADDR (IWM_HBUS_BASE+0x00c)
589 #define IWM_HBUS_TARG_MEM_WADDR (IWM_HBUS_BASE+0x010)
590 #define IWM_HBUS_TARG_MEM_WDAT (IWM_HBUS_BASE+0x018)
591 #define IWM_HBUS_TARG_MEM_RDAT (IWM_HBUS_BASE+0x01c)
594 #define IWM_HBUS_TARG_MBX_C (IWM_HBUS_BASE+0x030)
595 #define IWM_HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
602 * 0-15: register address (offset) within device
603 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
605 #define IWM_HBUS_TARG_PRPH_WADDR (IWM_HBUS_BASE+0x044)
606 #define IWM_HBUS_TARG_PRPH_RADDR (IWM_HBUS_BASE+0x048)
607 #define IWM_HBUS_TARG_PRPH_WDAT (IWM_HBUS_BASE+0x04c)
608 #define IWM_HBUS_TARG_PRPH_RDAT (IWM_HBUS_BASE+0x050)
611 #define IWM_WFPM_PS_CTL_CLR 0xa0300c
612 #define IWM_WFMP_MAC_ADDR_0 0xa03080
613 #define IWM_WFMP_MAC_ADDR_1 0xa03084
614 #define IWM_LMPM_PMG_EN 0xa01cec
615 #define IWM_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
616 #define IWM_RFIC_REG_RD 0xad0470
617 #define IWM_WFPM_CTRL_REG 0xa03030
618 #define IWM_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
619 #define IWM_ENABLE_WFPM 0x80000000
621 #define IWM_AUX_MISC_REG 0xa200b0
624 #define IWM_AUX_MISC_MASTER1_EN 0xa20818
625 #define IWM_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
626 #define IWM_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
627 #define IWM_RSA_ENABLE 0xa24b08
628 #define IWM_PREG_AUX_BUS_WPROT_0 0xa04cc0
629 #define IWM_PREG_PRPH_WPROT_9000 0xa04ce0
630 #define IWM_PREG_PRPH_WPROT_22000 0xa04d00
631 #define IWM_SB_CFG_OVERRIDE_ADDR 0xa26c78
632 #define IWM_SB_CFG_OVERRIDE_ENABLE 0x8000
633 #define IWM_SB_CFG_BASE_OVERRIDE 0xa20000
634 #define IWM_SB_MODIFY_CFG_FLAG 0xa03088
635 #define IWM_SB_CPU_1_STATUS 0xa01e30
636 #define IWM_SB_CPU_2_STATUS 0Xa01e34
638 #define IWM_UREG_CHICK 0xa05c00
642 #define IWM_HPM_DEBUG 0xa03440
647 #define IWM_HBUS_TARG_TEST_REG (IWM_HBUS_BASE+0x05c)
650 * Per-Tx-queue write pointer (index, really!)
653 * 0-7: queue write index
654 * 11-8: queue selector
656 #define IWM_HBUS_TARG_WRPTR (IWM_HBUS_BASE+0x060)
664 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
668 #define IWM_HOST_INT_TIMEOUT_MAX (0xFF)
669 #define IWM_HOST_INT_TIMEOUT_DEF (0x40)
670 #define IWM_HOST_INT_TIMEOUT_MIN (0x0)
678 #define IWM_DTS_DIODE_REG_DIG_VAL 0x000000FF /* bits [7:0] */
679 #define IWM_DTS_DIODE_REG_VREF_LOW 0x0000FF00 /* bits [15:8] */
680 #define IWM_DTS_DIODE_REG_VREF_HIGH 0x00FF0000 /* bits [23:16] */
681 #define IWM_DTS_DIODE_REG_VREF_ID 0x03000000 /* bits [25:24] */
682 #define IWM_DTS_DIODE_REG_PASS_ONCE 0x80000000 /* bits [31:31] */
683 #define IWM_DTS_DIODE_REG_FLAGS_MSK 0xFF000000 /* bits [31:24] */
684 /* Those are the masks INSIDE the flags bit-field: */
685 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID_POS 0
686 #define IWM_DTS_DIODE_REG_FLAGS_VREFS_ID 0x00000003 /* bits [1:0] */
688 #define IWM_DTS_DIODE_REG_FLAGS_PASS_ONCE 0x00000080 /* bits [7:7] */
694 #define IWM_CSR_MSIX_BASE (0x2000)
695 #define IWM_CSR_MSIX_FH_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x800)
696 #define IWM_CSR_MSIX_FH_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x804)
697 #define IWM_CSR_MSIX_HW_INT_CAUSES_AD (IWM_CSR_MSIX_BASE + 0x808)
698 #define IWM_CSR_MSIX_HW_INT_MASK_AD (IWM_CSR_MSIX_BASE + 0x80C)
699 #define IWM_CSR_MSIX_AUTOMASK_ST_AD (IWM_CSR_MSIX_BASE + 0x810)
700 #define IWM_CSR_MSIX_RX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x880)
701 #define IWM_CSR_MSIX_IVAR_AD_REG (IWM_CSR_MSIX_BASE + 0x890)
702 #define IWM_CSR_MSIX_PENDING_PBA_AD (IWM_CSR_MSIX_BASE + 0x1000)
710 IWM_MSIX_FH_INT_CAUSES_Q0 = (1 << 0),
719 * END iwl-csr.h
723 * BEGIN iwl-fw.h
730 IWM_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0),
749 IWM_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0,
750 IWM_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1,
751 IWM_MSIX_IVAR_CAUSE_S2D = 0x3,
752 IWM_MSIX_IVAR_CAUSE_FH_ERR = 0x5,
753 IWM_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10,
754 IWM_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11,
755 IWM_MSIX_IVAR_CAUSE_REG_IML = 0x12,
756 IWM_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16,
757 IWM_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17,
758 IWM_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18,
759 IWM_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29,
760 IWM_MSIX_IVAR_CAUSE_REG_SCD = 0x2a,
761 IWM_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b,
762 IWM_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d,
763 IWM_MSIX_IVAR_CAUSE_REG_HAP = 0x2e,
766 #define IWM_MSIX_AUTO_CLEAR_CAUSE (0 << 7)
796 #define IWM_UCODE_TLV_FLAGS_PAN (1 << 0)
828 * (command version 3) that supports per-chain limits
836 * @IWM_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
882 * @IWM_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
888 * @IWM_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
889 * @IWM_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
892 * IWM_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
898 * 0=no support)
901 * @IWM_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
907 * @IWM_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
917 * 0=no support)
921 #define IWM_UCODE_TLV_CAPA_D0I3_SUPPORT 0
980 #define IWM_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
981 #define IWM_PAGING_SEPARATOR_SECTION 0xAAAABBBB
984 #define IWM_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
985 #define IWM_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
986 #define IWM_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
987 #define IWM_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
1002 #define IWM_FW_PHY_CFG_RADIO_TYPE_POS 0
1003 #define IWM_FW_PHY_CFG_RADIO_TYPE (0x3 << IWM_FW_PHY_CFG_RADIO_TYPE_POS)
1005 #define IWM_FW_PHY_CFG_RADIO_STEP (0x3 << IWM_FW_PHY_CFG_RADIO_STEP_POS)
1007 #define IWM_FW_PHY_CFG_RADIO_DASH (0x3 << IWM_FW_PHY_CFG_RADIO_DASH_POS)
1009 #define IWM_FW_PHY_CFG_TX_CHAIN (0xf << IWM_FW_PHY_CFG_TX_CHAIN_POS)
1011 #define IWM_FW_PHY_CFG_RX_CHAIN (0xf << IWM_FW_PHY_CFG_RX_CHAIN_POS)
1016 * struct iwm_fw_cipher_scheme - a cipher scheme supported by FW.
1042 * struct iwm_fw_cscheme_list - a cipher scheme list
1052 * END iwl-fw.h
1056 * BEGIN iwl-fw-file.h
1069 uint8_t data[0]; /* in same order as sizes */
1078 uint8_t data[0]; /* in same order as sizes */
1091 IWM_UCODE_TLV_INVALID = 0, /* unused */
1142 #define IWM_UCODE_TLV_DEBUG_BASE 0x1000005
1143 #define IWM_UCODE_TLV_TYPE_DEBUG_INFO (IWM_UCODE_TLV_DEBUG_BASE + 0)
1153 uint8_t data[0];
1166 #define IWM_TLV_UCODE_MAGIC 0x0a4c5749
1187 uint8_t data[0];
1191 * END iwl-fw-file.h
1195 * BEGIN iwl-prph.h
1202 #define IWM_PRPH_BASE (0x00000)
1203 #define IWM_PRPH_END (0xFFFFF)
1206 #define IWM_APMG_BASE (IWM_PRPH_BASE + 0x3000)
1207 #define IWM_APMG_CLK_CTRL_REG (IWM_APMG_BASE + 0x0000)
1208 #define IWM_APMG_CLK_EN_REG (IWM_APMG_BASE + 0x0004)
1209 #define IWM_APMG_CLK_DIS_REG (IWM_APMG_BASE + 0x0008)
1210 #define IWM_APMG_PS_CTRL_REG (IWM_APMG_BASE + 0x000c)
1211 #define IWM_APMG_PCIDEV_STT_REG (IWM_APMG_BASE + 0x0010)
1212 #define IWM_APMG_RFKILL_REG (IWM_APMG_BASE + 0x0014)
1213 #define IWM_APMG_RTC_INT_STT_REG (IWM_APMG_BASE + 0x001c)
1214 #define IWM_APMG_RTC_INT_MSK_REG (IWM_APMG_BASE + 0x0020)
1215 #define IWM_APMG_DIGITAL_SVR_REG (IWM_APMG_BASE + 0x0058)
1216 #define IWM_APMG_ANALOG_SVR_REG (IWM_APMG_BASE + 0x006C)
1218 #define IWM_APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
1219 #define IWM_APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
1220 #define IWM_APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
1222 #define IWM_APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
1223 #define IWM_APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
1224 #define IWM_APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
1225 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
1226 #define IWM_APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
1227 #define IWM_APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */
1228 #define IWM_APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
1230 #define IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
1232 #define IWM_APMG_RTC_INT_STT_RFKILL (0x10000000)
1235 #define IWM_DEVICE_SYSTEM_TIME_REG 0xA0206C
1238 #define IWM_DEVICE_SET_NMI_REG 0x00a01c30
1239 #define IWM_DEVICE_SET_NMI_VAL_HW 0x01
1240 #define IWM_DEVICE_SET_NMI_VAL_DRV 0x80
1241 #define IWM_DEVICE_SET_NMI_8000_REG 0x00a01c24
1242 #define IWM_DEVICE_SET_NMI_8000_VAL 0x1000000
1248 #define IWM_RELEASE_CPU_RESET 0x300c
1249 #define IWM_RELEASE_CPU_RESET_BIT 0x1000000
1256 #define IWM_SHR_MISC_WFM_DTS_EN (0x00a10024)
1257 #define IWM_DTSC_CFG_MODE (0x00a10604)
1258 #define IWM_DTSC_VREF_AVG (0x00a10648)
1259 #define IWM_DTSC_VREF5_AVG (0x00a1064c)
1260 #define IWM_DTSC_CFG_MODE_PERIODIC (0x2)
1261 #define IWM_DTSC_PTAT_AVG (0x00a10650)
1277 * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c):
1279 * 0 -- EDCA BK (background) frames, lowest priority
1280 * 1 -- EDCA BE (best effort) frames, normal priority
1281 * 2 -- EDCA VI (video) frames, higher priority
1282 * 3 -- EDCA VO (voice) and management frames, highest priority
1283 * 4 -- unused
1284 * 5 -- unused
1285 * 6 -- unused
1286 * 7 -- Commands
1288 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1290 * channels 0-3 to support 11n aggregation via EDCA DMA channels.
1294 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1295 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1298 * Quality-Of-Service (QOS) priority, destined for a single station.
1300 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1303 * automatically processes block-acks received from the receiving STA,
1304 * and reschedules un-acked frames to be retransmitted (successful
1305 * Tx completion may end up being out-of-order).
1311 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1335 #define IWM_SCD_MEM_LOWER_BOUND (0x0000)
1339 * can keep track of at one time when creating block-ack chains of frames.
1340 * Note that "64" matches the number of ack bits in a block-ack packet.
1345 #define IWM_SCD_TXFIFO_POS_TID (0)
1347 #define IWM_SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1350 #define IWM_SCD_QUEUE_STTS_REG_POS_TXF (0)
1354 #define IWM_SCD_QUEUE_STTS_REG_MSK (0x017F0000)
1357 #define IWM_SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1359 #define IWM_SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1360 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS (0)
1361 #define IWM_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK (0x0000007F)
1363 #define IWM_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1364 #define IWM_SCD_GP_CTRL_ENABLE_31_QUEUES (1 << 0)
1368 #define IWM_SCD_CONTEXT_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x600)
1369 #define IWM_SCD_CONTEXT_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1372 #define IWM_SCD_TX_STTS_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x6A0)
1373 #define IWM_SCD_TX_STTS_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1376 #define IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x7E0)
1377 #define IWM_SCD_TRANS_TBL_MEM_UPPER_BOUND (IWM_SCD_MEM_LOWER_BOUND + 0x808)
1386 ((IWM_SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
1388 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00)
1390 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1391 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1392 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1393 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1394 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1395 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1396 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1397 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1398 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1399 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1400 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1405 return IWM_SCD_BASE + 0x18 + chnl * 4;
1406 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4;
1412 return IWM_SCD_BASE + 0x68 + chnl * 4;
1413 return IWM_SCD_BASE + 0x2B4 + chnl * 4;
1419 return IWM_SCD_BASE + 0x10c + chnl * 4;
1420 return IWM_SCD_BASE + 0x334 + chnl * 4;
1426 #define IWM_OSC_CLK (0xa04068)
1427 #define IWM_OSC_CLK_FORCE_CONTROL (0x8)
1430 * END iwl-prph.h
1434 * BEGIN iwl-fh.h
1445 #define IWM_FH_MEM_LOWER_BOUND (0x1000)
1446 #define IWM_FH_MEM_UPPER_BOUND (0x2000)
1449 * Keep-Warm (KW) buffer base address.
1452 * host DRAM powered on (via dummy accesses to DRAM) to maintain low-latency
1454 * from going into a power-savings mode that would cause higher DRAM latency,
1455 * and possible data over/under-runs, before all Tx/Rx is complete.
1459 * automatically invokes keep-warm accesses when normal accesses might not
1463 * 31-0: Keep-warm buffer physical base address [35:4], must be 4K aligned
1465 #define IWM_FH_KW_MEM_ADDR_REG (IWM_FH_MEM_LOWER_BOUND + 0x97C)
1471 * Device has 16 base pointer registers, one for each of 16 host-DRAM-resident
1473 * (see struct iwm_tfd_frame). These 16 pointer registers are offset by 0x04
1474 * bytes from one another. Each TFD circular buffer in DRAM must be 256-byte
1475 * aligned (address bits 0-7 must be 0).
1480 * 27-0: TFD CB physical base address [35:8], must be 256-byte aligned
1482 #define IWM_FH_MEM_CBBC_0_15_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1483 #define IWM_FH_MEM_CBBC_0_15_UPPER_BOUN (IWM_FH_MEM_LOWER_BOUND + 0xA10)
1484 #define IWM_FH_MEM_CBBC_16_19_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBF0)
1485 #define IWM_FH_MEM_CBBC_16_19_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1486 #define IWM_FH_MEM_CBBC_20_31_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB20)
1487 #define IWM_FH_MEM_CBBC_20_31_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xB80)
1495 return IWM_FH_MEM_CBBC_16_19_LOWER_BOUND + 4 * (chnl - 16);
1496 return IWM_FH_MEM_CBBC_20_31_LOWER_BOUND + 4 * (chnl - 20);
1522 * 27-0: Receive Buffer physical address bits [35:8], 256-byte aligned
1525 * into IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG [27:0].
1530 * physical address [35:4] into IWM_FH_RSCSR_CHNL0_STTS_WPTR_REG [31:0].
1534 * 31-12: Not used by driver
1535 * 11- 0: Index of last filled Rx buffer descriptor
1544 * available, i.e. one RBD past the tail of the ready-to-fill RBDs within
1545 * the circular buffer. This value should initially be 0 (before preparing any
1547 * wrap back to 0 at the end of the circular buffer (but don't wrap before
1560 * driver may process the RB pointed to by RBD 0. Depending on volume of
1569 #define IWM_FH_MEM_RSCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xBC0)
1570 #define IWM_FH_MEM_RSCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1574 * Physical base address of 8-byte Rx Status buffer.
1576 * 31-0: Rx status buffer physical base address [35:4], must 16-byte aligned.
1583 * 27-0: RBD CD physical base address [35:8], must be 256-byte aligned.
1585 #define IWM_FH_RSCSR_CHNL0_RBDCB_BASE_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x004)
1590 * 11-0: Index of driver's most recent prepared-to-be-filled RBD, + 1.
1591 * NOTE: For 256-entry circular buffer, use only bits [7:0].
1593 #define IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x008)
1596 #define IWM_FW_RSCSR_CHNL0_RXDCB_RDPTR_REG (IWM_FH_MEM_RSCSR_CHNL0 + 0x00c)
1601 * Rx Config Reg for channel 0 (only channel used)
1606 * Clearing IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG to 0 turns off Rx DMA.
1611 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1613 * 29-24: reserved
1614 * 23-20: # RBDs in circular buffer = 2^value; use "8" for 256 RBDs (normal),
1616 * 19-18: reserved
1617 * 17-16: size of each receive buffer; '00' 4K (normal), '01' 8K,
1619 * 15-14: reserved
1620 * 13-12: IRQ destination; '00' none, '01' host driver (normal operation)
1621 * 11- 4: timeout for closing Rx buffer and interrupting host (units 32 usec)
1622 * typical value 0x10 (about 1/2 msec)
1623 * 3- 0: reserved
1625 #define IWM_FH_MEM_RCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC00)
1626 #define IWM_FH_MEM_RCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xCC0)
1630 #define IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR (IWM_FH_MEM_RCSR_CHNL0 + 0x8)
1631 #define IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ (IWM_FH_MEM_RCSR_CHNL0 + 0x10)
1633 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1634 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1635 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1636 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1637 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1638 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31*/
1642 #define IWM_RX_RB_TIMEOUT (0x11)
1644 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1645 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1646 #define IWM_FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1648 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1649 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1650 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1651 #define IWM_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1653 #define IWM_FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1654 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1655 #define IWM_FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1660 * After stopping Rx DMA channel (writing 0 to
1665 * 24: 1 = Channel 0 is idle
1670 #define IWM_FH_MEM_RSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xC40)
1671 #define IWM_FH_MEM_RSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1674 #define IWM_FH_MEM_RSSR_RX_STATUS_REG (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x004)
1676 (IWM_FH_MEM_RSSR_LOWER_BOUND + 0x008)
1678 #define IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1682 /* TFDB Area - TFDs buffer table */
1683 #define IWM_FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1684 #define IWM_FH_TFDIB_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x900)
1685 #define IWM_FH_TFDIB_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x958)
1686 #define IWM_FH_TFDIB_CTRL0_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1687 #define IWM_FH_TFDIB_CTRL1_REG(_chnl) (IWM_FH_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1694 * which feed the DMA/FIFO channels); config regs are separated by 0x20 bytes.
1702 * All other bits should be 0.
1705 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1707 * 29- 4: Reserved, set to "0"
1708 * 3: Enable internal DMA requests (1, normal operation), disable (0)
1709 * 2- 0: Reserved, set to "0"
1711 #define IWM_FH_TCSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xD00)
1712 #define IWM_FH_TCSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xE60)
1719 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1721 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1723 (IWM_FH_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1725 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1726 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1728 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1729 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1731 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1732 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1733 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1735 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1736 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1737 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1739 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1740 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1741 #define IWM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1743 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1744 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1745 #define IWM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1753 * After stopping Tx DMA channel (writing 0 to
1759 * 31-24: 1 = Channel buffers empty (channel 7:0)
1760 * 23-16: 1 = No pending requests (channel 7:0)
1762 #define IWM_FH_TSSR_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEA0)
1763 #define IWM_FH_TSSR_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0xEC0)
1765 #define IWM_FH_TSSR_TX_STATUS_REG (IWM_FH_TSSR_LOWER_BOUND + 0x010)
1773 * 16-9:Each status bit is for one channel. Indicates that an (Error) ActDMA
1777 * 7-0: Each status bit indicates a channel's TxCredit error. When an error
1784 #define IWM_FH_TSSR_TX_ERROR_REG (IWM_FH_TSSR_LOWER_BOUND + 0x018)
1785 #define IWM_FH_TSSR_TX_MSG_CONFIG_REG (IWM_FH_TSSR_LOWER_BOUND + 0x008)
1791 #define IWM_FH_SRVC_LOWER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9C8)
1792 #define IWM_FH_SRVC_UPPER_BOUND (IWM_FH_MEM_LOWER_BOUND + 0x9D0)
1794 (IWM_FH_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1796 #define IWM_FH_TX_CHICKEN_BITS_REG (IWM_FH_MEM_LOWER_BOUND + 0xE98)
1797 #define IWM_FH_TX_TRB_REG(_chan) (IWM_FH_MEM_LOWER_BOUND + 0x958 + \
1801 * it is brought from the memory to TX-FIFO
1803 #define IWM_FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1816 * struct iwm_rb_status - reseve buffer status
1818 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1819 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1820 * @finished_rb_num [0:11] - Indicates the index of the current RB
1822 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1843 return (sizeof(addr) > sizeof(uint32_t) ? (addr >> 16) >> 16 : 0) & 0xF;
1850 * @lo: low [31:0] portion of the dma address of TX buffer
1852 * @hi_n_len 0-3 [35:32] portion of dma
1853 * 4-15 length of the tx buffer
1866 * @ num_tbs 0-4 number of active tbs
1868 * 6-7 padding (not used)
1874 * contiguous 256 TFDs x 128 bytes-per-TFD = 32 KBytes
1883 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1896 #define IWM_KW_SIZE 0x1000 /* 4k */
1898 /* Fixed (non-configurable) rx data from phy */
1903 * @tfd_offset 0-12 - tx command byte count
1904 * 12-16 - station index
1912 * END iwl-fh.h
1916 * BEGIN mvm/fw-api.h
1926 * DQA - Dynamic Queue Allocation -introduction
1929 * to allow dynamic allocation of queues on-demand, rather than allocate them
1931 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2
1937 * TXQ #0 - command queue
1938 * TXQ #1 - aux frames
1939 * TXQ #2 - P2P device frames
1940 * TXQ #3 - P2P GO/SoftAP GCAST/BCAST frames
1941 * TXQ #4 - BSS DATA frames queue
1942 * TXQ #5-8 - non-QoS data, QoS no-data, and MGMT frames queue pool
1943 * TXQ #9 - P2P GO/SoftAP probe responses
1944 * TXQ #10-31 - QoS DATA frames queue pool (for Tx aggregation)
1948 #define IWM_DQA_CMD_QUEUE 0
1960 /* Reserve 8 DQA Tx queues, from 10 up to 17, for A-MPDU aggregation. */
1963 #define IWM_LAST_AGG_TX_QUEUE (IWM_FIRST_AGG_TX_QUEUE + IWM_MAX_TID_COUNT - 1)
1965 /* legacy non-DQA queues; the legacy command queue uses a different number! */
1970 #define IWM_TX_FIFO_BK 0
1982 #define IWM_ALIVE 0x1
1983 #define IWM_REPLY_ERROR 0x2
1984 #define IWM_INIT_COMPLETE_NOTIF 0x4
1987 #define IWM_PHY_CONTEXT_CMD 0x8
1988 #define IWM_DBG_CFG 0x9
1991 #define IWM_SCAN_ITERATION_COMPLETE_UMAC 0xb5
1992 #define IWM_SCAN_CFG_CMD 0xc
1993 #define IWM_SCAN_REQ_UMAC 0xd
1994 #define IWM_SCAN_ABORT_UMAC 0xe
1995 #define IWM_SCAN_COMPLETE_UMAC 0xf
1998 #define IWM_ADD_STA_KEY 0x17
1999 #define IWM_ADD_STA 0x18
2000 #define IWM_REMOVE_STA 0x19
2003 #define IWM_TX_CMD 0x1c
2004 #define IWM_TXPATH_FLUSH 0x1e
2005 #define IWM_MGMT_MCAST_KEY 0x1f
2008 #define IWM_SCD_QUEUE_CFG 0x1d
2011 #define IWM_WEP_KEY 0x20
2014 #define IWM_MAC_CONTEXT_CMD 0x28
2015 #define IWM_TIME_EVENT_CMD 0x29 /* both CMD and response */
2016 #define IWM_TIME_EVENT_NOTIFICATION 0x2a
2017 #define IWM_BINDING_CONTEXT_CMD 0x2b
2018 #define IWM_TIME_QUOTA_CMD 0x2c
2019 #define IWM_NON_QOS_TX_COUNTER_CMD 0x2d
2021 #define IWM_LQ_CMD 0x4e
2024 #define IWM_TEMPERATURE_NOTIFICATION 0x62
2025 #define IWM_CALIBRATION_CFG_CMD 0x65
2026 #define IWM_CALIBRATION_RES_NOTIFICATION 0x66
2027 #define IWM_CALIBRATION_COMPLETE_NOTIFICATION 0x67
2028 #define IWM_RADIO_VERSION_NOTIFICATION 0x68
2031 #define IWM_FW_PAGING_BLOCK_CMD 0x4f
2034 #define IWM_SCAN_OFFLOAD_REQUEST_CMD 0x51
2035 #define IWM_SCAN_OFFLOAD_ABORT_CMD 0x52
2036 #define IWM_HOT_SPOT_CMD 0x53
2037 #define IWM_SCAN_OFFLOAD_COMPLETE 0x6d
2038 #define IWM_SCAN_OFFLOAD_UPDATE_PROFILES_CMD 0x6e
2039 #define IWM_SCAN_OFFLOAD_CONFIG_CMD 0x6f
2040 #define IWM_MATCH_FOUND_NOTIFICATION 0xd9
2041 #define IWM_SCAN_ITERATION_COMPLETE 0xe7
2044 #define IWM_PHY_CONFIGURATION_CMD 0x6a
2045 #define IWM_CALIB_RES_NOTIF_PHY_DB 0x6b
2046 #define IWM_PHY_DB_CMD 0x6c
2048 /* Power - legacy power table command */
2049 #define IWM_POWER_TABLE_CMD 0x77
2050 #define IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78
2051 #define IWM_LTR_CONFIG 0xee
2054 #define IWM_REPLY_THERMAL_MNG_BACKOFF 0x7e
2057 #define IWM_NVM_ACCESS_CMD 0x88
2059 #define IWM_SET_CALIB_DEFAULT_CMD 0x8e
2061 #define IWM_BEACON_NOTIFICATION 0x90
2062 #define IWM_BEACON_TEMPLATE_CMD 0x91
2063 #define IWM_TX_ANT_CONFIGURATION_CMD 0x98
2064 #define IWM_BT_CONFIG 0x9b
2065 #define IWM_STATISTICS_NOTIFICATION 0x9d
2066 #define IWM_REDUCE_TX_POWER_CMD 0x9f
2068 /* RF-KILL commands and notifications */
2069 #define IWM_CARD_STATE_CMD 0xa0
2070 #define IWM_CARD_STATE_NOTIFICATION 0xa1
2072 #define IWM_MISSED_BEACONS_NOTIFICATION 0xa2
2074 #define IWM_MFUART_LOAD_NOTIFICATION 0xb1
2076 /* Power - new power table command */
2077 #define IWM_MAC_PM_POWER_TABLE 0xa9
2079 #define IWM_REPLY_RX_PHY_CMD 0xc0
2080 #define IWM_REPLY_RX_MPDU_CMD 0xc1
2081 #define IWM_BA_NOTIF 0xc5
2084 #define IWM_MCC_UPDATE_CMD 0xc8
2085 #define IWM_MCC_CHUB_UPDATE_CMD 0xc9
2088 #define IWM_BT_COEX_PRIO_TABLE 0xcc
2089 #define IWM_BT_COEX_PROT_ENV 0xcd
2090 #define IWM_BT_PROFILE_NOTIFICATION 0xce
2091 #define IWM_BT_COEX_CI 0x5d
2093 #define IWM_REPLY_SF_CFG_CMD 0xd1
2094 #define IWM_REPLY_BEACON_FILTERING_CMD 0xd2
2097 #define IWM_CMD_DTS_MEASUREMENT_TRIGGER 0xdc
2098 #define IWM_DTS_MEASUREMENT_NOTIFICATION 0xdd
2100 #define IWM_REPLY_DEBUG_CMD 0xf0
2101 #define IWM_DEBUG_LOG_MSG 0xf7
2103 #define IWM_MCAST_FILTER_CMD 0xd0
2106 #define IWM_D3_CONFIG_CMD 0xd3
2107 #define IWM_PROT_OFFLOAD_CONFIG_CMD 0xd4
2108 #define IWM_OFFLOADS_QUERY_CMD 0xd5
2109 #define IWM_REMOTE_WAKE_CONFIG_CMD 0xd6
2112 #define IWM_WOWLAN_PATTERNS 0xe0
2113 #define IWM_WOWLAN_CONFIGURATION 0xe1
2114 #define IWM_WOWLAN_TSC_RSC_PARAM 0xe2
2115 #define IWM_WOWLAN_TKIP_PARAM 0xe3
2116 #define IWM_WOWLAN_KEK_KCK_MATERIAL 0xe4
2117 #define IWM_WOWLAN_GET_STATUSES 0xe5
2118 #define IWM_WOWLAN_TX_POWER_PER_DB 0xe6
2121 #define IWM_NET_DETECT_CONFIG_CMD 0x54
2122 #define IWM_NET_DETECT_PROFILES_QUERY_CMD 0x56
2123 #define IWM_NET_DETECT_PROFILES_CMD 0x57
2124 #define IWM_NET_DETECT_HOTSPOTS_CMD 0x58
2125 #define IWM_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59
2128 #define IWM_FSEQ_VER_MISMATCH_NOTIFICATION 0xff
2130 #define IWM_REPLY_MAX 0xff
2133 #define IWM_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0
2134 #define IWM_CTDP_CONFIG_CMD 0x03
2135 #define IWM_TEMP_REPORTING_THRESHOLDS_CMD 0x04
2136 #define IWM_CT_KILL_NOTIFICATION 0xFE
2137 #define IWM_DTS_MEASUREMENT_NOTIF_WIDE 0xFF
2140 #define IWM_LEGACY_GROUP 0x0
2141 #define IWM_LONG_GROUP 0x1
2142 #define IWM_SYSTEM_GROUP 0x2
2143 #define IWM_MAC_CONF_GROUP 0x3
2144 #define IWM_PHY_OPS_GROUP 0x4
2145 #define IWM_DATA_PATH_GROUP 0x5
2146 #define IWM_PROT_OFFLOAD_GROUP 0xb
2150 #define IWM_SHARED_MEM_CFG_CMD 0x00
2151 #define IWM_SOC_CONFIGURATION_CMD 0x01
2152 #define IWM_INIT_EXTENDED_CFG_CMD 0x03
2153 #define IWM_FW_ERROR_RECOVERY_CMD 0x07
2156 #define IWM_DQA_ENABLE_CMD 0x00
2167 * struct iwm_cmd_response - generic response struct for most commands
2183 * struct iwm_reduce_tx_power_cmd - TX power reduction command
2184 * IWM_REDUCE_TX_POWER_CMD = 0x9f
2211 #define IWM_CALIB_CFG_XTAL_IDX (1 << 0)
2239 #define IWM_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
2253 * struct iwm_ct_kill_notif - CT-kill entry notification
2264 * struct iwm_temp_report_ths_cmd - set temperature thresholds
2289 * phy db - configure operational ucode
2304 * phy db - Receive phy db chunk after calibrations
2312 /* 7k family NVM HW-Section offset (in words) definitions */
2313 #define IWM_HW_ADDR 0x15
2314 /* 7k family NVM SW-Section offset (in words) definitions */
2315 #define IWM_NVM_SW_SECTION 0x1C0
2316 #define IWM_NVM_VERSION 0
2320 #define IWM_NVM_CHANNELS 0x1E0 - IWM_NVM_SW_SECTION
2322 #define IWM_NVM_CALIB_SECTION 0x2B8
2323 #define IWM_XTAL_CALIB (0x316 - IWM_NVM_CALIB_SECTION)
2325 /* 8k family NVM HW-Section offset (in words) definitions */
2326 #define IWM_HW_ADDR0_WFPM_8000 0x12
2327 #define IWM_HW_ADDR1_WFPM_8000 0x16
2328 #define IWM_HW_ADDR0_PCIE_8000 0x8A
2329 #define IWM_HW_ADDR1_PCIE_8000 0x8E
2332 /* 8k family NVM SW-Section offset (in words) definitions */
2333 #define IWM_NVM_SW_SECTION_8000 0x1C0
2334 #define IWM_NVM_VERSION_8000 0
2335 #define IWM_RADIO_CFG_8000 0
2339 /* 8k family NVM REGULATORY -Section offset (in words) definitions */
2340 #define IWM_NVM_CHANNELS_8000 0
2341 #define IWM_NVM_LAR_OFFSET_8000_OLD 0x4C7
2342 #define IWM_NVM_LAR_OFFSET_8000 0x507
2343 #define IWM_NVM_LAR_ENABLED_8000 0x7
2346 #define IWM_NVM_CALIB_SECTION_8000 0x2B8
2347 #define IWM_XTAL_CALIB_8000 (0x316 - IWM_NVM_CALIB_SECTION_8000)
2350 #define IWM_NVM_SKU_CAP_BAND_24GHZ (1 << 0)
2357 #define IWM_NVM_RF_CFG_DASH_MSK(x) (x & 0x3) /* bits 0-1 */
2358 #define IWM_NVM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
2359 #define IWM_NVM_RF_CFG_TYPE_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
2360 #define IWM_NVM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
2361 #define IWM_NVM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
2362 #define IWM_NVM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
2364 #define IWM_NVM_RF_CFG_PNUM_MSK_8000(x) (x & 0xF)
2365 #define IWM_NVM_RF_CFG_DASH_MSK_8000(x) ((x >> 4) & 0xF)
2366 #define IWM_NVM_RF_CFG_STEP_MSK_8000(x) ((x >> 8) & 0xF)
2367 #define IWM_NVM_RF_CFG_TYPE_MSK_8000(x) ((x >> 12) & 0xFFF)
2368 #define IWM_NVM_RF_CFG_TX_ANT_MSK_8000(x) ((x >> 24) & 0xF)
2369 #define IWM_NVM_RF_CFG_RX_ANT_MSK_8000(x) ((x >> 28) & 0xF)
2383 #define IWM_NVM_CHANNEL_VALID (1 << 0)
2394 #define IWM_NVM_ACCESS_TARGET_CACHE 0
2399 #define IWM_NVM_SECTION_TYPE_HW 0
2415 * struct iwm_nvm_access_cmd_ver2 - Request the device to send an NVM section
2416 * @op_code: 0 - read, 1 - write
2455 #define IWM_PAGING_ADDR_SIG 0xAA000000
2459 #define IWM_PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS 0
2465 * struct iwm_fw_paging_cmd - paging layout
2467 * (IWM_FW_PAGING_BLOCK_CMD = 0x4f)
2484 * struct iwm_nvm_access_resp_ver2 - response to IWM_NVM_ACCESS_CMD
2488 * @status: 0 for success, fail otherwise
2499 /* IWM_ALIVE 0x1 */
2502 #define IWM_ALIVE_RESP_UCODE_OK (1 << 0)
2506 #define IWM_FW_TYPE_HW 0
2514 #define IWM_FW_SUBTYPE_FULL_FEATURE 0
2523 #define IWM_ALIVE_STATUS_ERR 0xDEAD
2524 #define IWM_ALIVE_STATUS_OK 0xCAFE
2526 #define IWM_ALIVE_FLG_RFKILL (1 << 0)
2568 #define IWM_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)
2571 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc
2572 #define IWM_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0
2578 * struct iwm_soc_configuration_cmd - Set device stabilization latency
2595 #define IWM_FW_ERR_UNKNOWN_CMD 0x0
2596 #define IWM_FW_ERR_INVALID_CMD_PARAM 0x1
2597 #define IWM_FW_ERR_SERVICE 0x2
2598 #define IWM_FW_ERR_ARC_MEMORY 0x3
2599 #define IWM_FW_ERR_ARC_CODE 0x4
2600 #define IWM_FW_ERR_WATCH_DOG 0x5
2601 #define IWM_FW_ERR_WEP_GRP_KEY_INDX 0x10
2602 #define IWM_FW_ERR_WEP_KEY_SIZE 0x11
2603 #define IWM_FW_ERR_OBSOLETE_FUNC 0x12
2604 #define IWM_FW_ERR_UNEXPECTED 0xFE
2605 #define IWM_FW_ERR_FATAL 0xFF
2608 * struct iwm_error_resp - FW error indication
2609 * ( IWM_REPLY_ERROR = 0x2 )
2614 * error_type = 2, otherwise 0
2629 * struct iwm_fw_cmd_version - firmware command version entry
2651 #define IWM_FW_CTXT_ID_POS (0)
2652 #define IWM_FW_CTXT_ID_MSK (0xff << IWM_FW_CTXT_ID_POS)
2654 #define IWM_FW_CTXT_COLOR_MSK (0xff << IWM_FW_CTXT_COLOR_POS)
2655 #define IWM_FW_CTXT_INVALID (0xffffffff)
2661 #define IWM_FW_CTXT_ACTION_STUB 0
2673 #define IWM_TE_BSS_STA_AGGRESSIVE_ASSOC 0
2702 /* Time event - defines for command API v1 */
2717 #define IWM_TE_V1_FRAG_NONE 0
2720 #define IWM_TE_V1_FRAG_ENDLESS 0xffffffff
2723 #define IWM_TE_V1_FRAG_MAX_MSK 0x0fffffff
2725 #define IWM_TE_V1_REPEAT_ENDLESS 0xffffffff
2727 #define IWM_TE_V1_REPEAT_MAX_MSK_V1 0x0fffffff
2730 #define IWM_TE_V1_INDEPENDENT 0
2731 #define IWM_TE_V1_DEP_OTHER (1 << 0)
2753 #define IWM_TE_V1_NOTIF_NONE 0
2754 #define IWM_TE_V1_NOTIF_HOST_EVENT_START (1 << 0)
2765 /* Time event - defines for command API */
2768 * DOC: Time Events - what is it?
2797 * Is there an end-time for the event?
2817 #define IWM_TE_V2_FRAG_NONE 0
2820 #define IWM_TE_V2_FRAG_MAX 0xfe
2821 #define IWM_TE_V2_FRAG_ENDLESS 0xff
2824 #define IWM_TE_V2_REPEAT_ENDLESS 0xff
2826 #define IWM_TE_V2_REPEAT_MAX 0xfe
2848 * @IWM_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of tha same MAC
2851 #define IWM_TE_V2_DEFAULT_POLICY 0x0
2854 #define IWM_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)
2865 #define IWM_TE_V2_NOTIF_MSK 0xff
2876 * struct iwm_time_event_cmd_api - configuring Time Events
2879 * ( IWM_TIME_EVENT_CMD = 0x29 )
2916 * struct iwm_time_event_resp - response structure to iwm_time_event_cmd
2917 * @status: bit 0 indicates success, all others specify errors
2930 * struct iwm_time_event_notif - notifications of time event start/stop
2931 * ( IWM_TIME_EVENT_NOTIFICATION = 0x2a )
2952 * struct iwm_binding_cmd_v1 - configuring bindings
2953 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2970 * struct iwm_binding_cmd - configuring bindings
2971 * ( IWM_BINDING_CONTEXT_CMD = 0x2b )
2988 #define IWM_LMAC_24G_INDEX 0
2995 * struct iwm_time_quota_data - configuration of time quota per binding
3008 * struct iwm_time_quota_cmd - configuration of time quota between bindings
3009 * ( IWM_TIME_QUOTA_CMD = 0x2c )
3016 #define IWM_QUOTA_LOW_LATENCY_NONE 0
3017 #define IWM_QUOTA_LOW_LATENCY_TX (1 << 0)
3021 * struct iwm_time_quota_data - configuration of time quota per binding
3036 * struct iwm_time_quota_cmd - configuration of time quota between bindings
3037 * ( TIME_QUOTA_CMD = 0x2c )
3038 * Note: on non-CDB the fourth one is the auxilary mac and is essentially zero.
3051 #define IWM_PHY_BAND_5 (0)
3055 #define IWM_PHY_VHT_CHANNEL_MODE20 (0x0)
3056 #define IWM_PHY_VHT_CHANNEL_MODE40 (0x1)
3057 #define IWM_PHY_VHT_CHANNEL_MODE80 (0x2)
3058 #define IWM_PHY_VHT_CHANNEL_MODE160 (0x3)
3063 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
3064 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
3072 #define IWM_PHY_VHT_CTRL_POS_1_BELOW (0x0)
3073 #define IWM_PHY_VHT_CTRL_POS_2_BELOW (0x1)
3074 #define IWM_PHY_VHT_CTRL_POS_3_BELOW (0x2)
3075 #define IWM_PHY_VHT_CTRL_POS_4_BELOW (0x3)
3076 #define IWM_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
3077 #define IWM_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
3078 #define IWM_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
3079 #define IWM_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
3095 * struct iwm_fw_channel_info - channel information
3111 #define IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
3113 (0x1 << IWM_PHY_RX_CHAIN_DRIVER_FORCE_POS)
3116 (0x7 << IWM_PHY_RX_CHAIN_VALID_POS)
3119 (0x7 << IWM_PHY_RX_CHAIN_FORCE_SEL_POS)
3122 (0x7 << IWM_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
3125 (0x3 << IWM_PHY_RX_CHAIN_CNT_POS)
3128 (0x3 << IWM_PHY_RX_CHAIN_MIMO_CNT_POS)
3131 (0x1 << IWM_PHY_RX_CHAIN_MIMO_FORCE_POS)
3138 * struct iwm_phy_context_cmd - config of the PHY context
3139 * ( IWM_PHY_CONTEXT_CMD = 0x8 )
3142 * @apply_time: 0 means immediate apply and context switch.
3149 * @dsp_cfg_flags: set to 0
3189 #define IWM_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
3190 #define IWM_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
3191 #define IWM_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
3192 #define IWM_RX_INFO_ENERGY_ANT_A_POS 0
3198 #define IWM_OFDM_AGC_A_MSK 0x0000007f
3199 #define IWM_OFDM_AGC_A_POS 0
3200 #define IWM_OFDM_AGC_B_MSK 0x00003f80
3202 #define IWM_OFDM_AGC_CODE_MSK 0x3fe00000
3204 #define IWM_OFDM_RSSI_INBAND_A_MSK 0x00ff
3205 #define IWM_OFDM_RSSI_A_POS 0
3206 #define IWM_OFDM_RSSI_ALLBAND_A_MSK 0xff00
3208 #define IWM_OFDM_RSSI_INBAND_B_MSK 0xff0000
3210 #define IWM_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
3214 * struct iwm_rx_phy_info - phy info
3215 * (IWM_REPLY_RX_PHY_CMD = 0xc0)
3222 * @beacon_time_stamp: beacon at on-air rise
3227 * @byte_count: frame's byte-count
3247 #if 0
3272 * @IWM_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
3277 #define IWM_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)
3281 #define IWM_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)
3320 #define IWM_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)
3329 #define IWM_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)
3342 #define IWM_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)
3343 #define IWM_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)
3345 #define IWM_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)
3346 #define IWM_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)
3348 #define IWM_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03
3349 #define IWM_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0
3352 #define IWM_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f
3353 #define IWM_RX_MPDU_MFLG2_PAD 0x20
3354 #define IWM_RX_MPDU_MFLG2_AMSDU 0x40
3356 #define IWM_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f
3357 #define IWM_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80
3389 #define IWM_RX_REORDER_DATA_INVALID_BAID 0x7f
3391 #define IWM_RX_MPDU_REORDER_NSSN_MASK 0x00000fff
3392 #define IWM_RX_MPDU_REORDER_SN_MASK 0x00fff000
3394 #define IWM_RX_MPDU_REORDER_BAID_MASK 0x7f000000
3396 #define IWM_RX_MPDU_REORDER_BA_OLD_SN 0x80000000
3418 * struct iwm_radio_version_notif - information on the radio version
3419 * ( IWM_RADIO_VERSION_NOTIFICATION = 0x68 )
3430 #define IWM_CARD_ENABLED 0x00
3431 #define IWM_HW_CARD_DISABLED 0x01
3432 #define IWM_SW_CARD_DISABLED 0x02
3433 #define IWM_CT_KILL_CARD_DISABLED 0x04
3434 #define IWM_HALT_CARD_DISABLED 0x08
3435 #define IWM_CARD_DISABLED_MSK 0x0f
3436 #define IWM_CARD_IS_RX_ON 0x10
3439 * struct iwm_radio_version_notif - information on the radio version
3440 * (IWM_CARD_STATE_NOTIFICATION = 0xa1 )
3448 * struct iwm_missed_beacons_notif - information on missed beacons
3449 * ( IWM_MISSED_BEACONS_NOTIFICATION = 0xa2 )
3466 * struct iwm_mfuart_load_notif - mfuart image version & status
3467 * ( IWM_MFUART_LOAD_NOTIFICATION = 0xb1 )
3481 * struct iwm_set_calib_default_cmd - set default value for calibration.
3482 * ( IWM_SET_CALIB_DEFAULT_CMD = 0x8e )
3490 uint8_t data[0];
3497 * struct iwm_mcast_filter_cmd - configure multicast filter.
3500 * to identify network interface adopted in host-device IF.
3516 uint8_t addr_list[0];
3547 * count the number of times we have to re-tune
3703 * IWM_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
3707 * IWM_REPLY_STATISTICS_CMD 0x9c, above.
3711 * 0x9c with CLEAR_STATS bit set (see above).
3731 IWM_SF_LONG_DELAY_ON = 0, /* should never be called by driver */
3802 * END mvm/fw-api.h
3806 * BEGIN mvm/fw-api-mac.h
3810 * The first MAC indices (starting from 0)
3814 #define IWM_MAC_INDEX_MIN_DRIVER 0
3817 #define IWM_AC_BK 0
3845 * @IWM_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
3875 #define IWM_TSF_ID_A 0
3883 * struct iwm_mac_data_ap - configuration data for AP MAC context
3906 * struct iwm_mac_data_ibss - configuration data for IBSS MAC context
3922 * struct iwm_mac_data_sta - configuration data for station MAC context
3923 * @is_assoc: 1 for associated state, 0 otherwise
3947 * struct iwm_mac_data_go - configuration data for P2P GO MAC context
3950 * 0 indicates that there is no CT window.
3960 * struct iwm_mac_data_p2p_sta - configuration data for P2P client MAC context
3963 * 0 indicates that there is no CT window.
3971 * struct iwm_mac_data_pibss - Pseudo IBSS config data
3979 * struct iwm_mac_data_p2p_dev - configuration data for the P2P Device MAC
4006 #define IWM_MAC_FILTER_IN_PROMISC (1 << 0)
4023 #define IWM_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)
4028 * struct iwm_ac_qos - QOS timing params for IWM_MAC_CONTEXT_CMD
4030 * Should be a power-of-2, minus 1. Device's default is 0x0f.
4032 * Should be a power-of-2, minus 1. Device's default is 0x3f.
4036 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
4054 * struct iwm_mac_ctx_cmd - command structure to configure MAC contexts
4055 * ( IWM_MAC_CONTEXT_CMD = 0x28 )
4065 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
4066 * @short_slot: 0x10 for enabling short slots, 0 otherwise
4107 return 0;
4108 return 0xFFFFFFFF / v;
4111 #define IWM_NONQOS_SEQ_GET 0x1
4112 #define IWM_NONQOS_SEQ_SET 0x2
4121 * END mvm/fw-api-mac.h
4125 * BEGIN mvm/fw-api-power.h
4143 #define IWM_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001
4144 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002
4145 #define IWM_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004
4146 #define IWM_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008
4147 #define IWM_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010
4148 #define IWM_LTR_CFG_FLAG_SW_SET_LONG 0x00000020
4149 #define IWM_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040
4152 * struct iwm_ltr_config_cmd_v1 - configures the LTR
4164 * struct iwm_ltr_config_cmd - configures the LTR
4187 * receiver and transmitter. '0' - does not allow.
4188 * @IWM_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
4190 * @IWM_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
4201 #define IWM_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4216 * '0' Do not allow. This flag should be always set to '1' unless
4220 * '0' Power management is enabled, one of the power schemes is applied.
4222 #define IWM_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4226 * struct iwm_device_power_cmd - device wide power command.
4227 * IWM_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
4238 * struct iwm_mac_power_cmd - New power command containing uAPSD support
4239 * IWM_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
4242 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
4243 * Minimum allowed:- 3 * DTIM. Keep alive period must be
4247 * PSM transition - legacy PM
4249 * PSM transition - legacy PM
4255 * PSM transition - uAPSD
4257 * PSM transition - uAPSD
4269 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
4311 * struct iwm_uapsd_misbehaving_ap_notif - FW sends this notification when
4313 * IWM_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
4314 * @sta_id: index of station in uCode's station table - associated AP ID in
4325 * IWM_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
4341 * Threshold. Typical energy threshold is -72dBm.
4344 * If the current temperature is above this threshold - Fast filter
4345 * will be used, If the current temperature is below this threshold -
4357 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
4361 * for a longer period of time then this escape-timeout. Units: Beacons.
4362 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
4381 #define IWM_BF_ENERGY_DELTA_MIN 0
4385 #define IWM_BF_ROAMING_ENERGY_DELTA_MIN 0
4389 #define IWM_BF_ROAMING_STATE_MIN 0
4393 #define IWM_BF_TEMP_THRESHOLD_MIN 0
4397 #define IWM_BF_TEMP_FAST_FILTER_MIN 0
4401 #define IWM_BF_TEMP_SLOW_FILTER_MIN 0
4405 #define IWM_BF_DEBUG_FLAG_DEFAULT 0
4409 #define IWM_BF_ESCAPE_TIMER_MIN 0
4414 #define IWM_BA_ESCAPE_TIMER_MIN 0
4431 * END mvm/fw-api-power.h
4435 * BEGIN mvm/fw-api-rs.h
4440 #define IWM_RATE_HT_SISO_MCS_0_PLCP 0
4448 #define IWM_RATE_HT_MIMO2_MCS_8_PLCP 0x8
4449 #define IWM_RATE_HT_MIMO2_MCS_9_PLCP 0x9
4450 #define IWM_RATE_HT_MIMO2_MCS_10_PLCP 0xA
4451 #define IWM_RATE_HT_MIMO2_MCS_11_PLCP 0xB
4452 #define IWM_RATE_HT_MIMO2_MCS_12_PLCP 0xC
4453 #define IWM_RATE_HT_MIMO2_MCS_13_PLCP 0xD
4454 #define IWM_RATE_HT_MIMO2_MCS_14_PLCP 0xE
4455 #define IWM_RATE_HT_MIMO2_MCS_15_PLCP 0xF
4456 #define IWM_RATE_VHT_SISO_MCS_0_PLCP 0
4466 #define IWM_RATE_VHT_MIMO2_MCS_0_PLCP 0x10
4467 #define IWM_RATE_VHT_MIMO2_MCS_1_PLCP 0x11
4468 #define IWM_RATE_VHT_MIMO2_MCS_2_PLCP 0x12
4469 #define IWM_RATE_VHT_MIMO2_MCS_3_PLCP 0x13
4470 #define IWM_RATE_VHT_MIMO2_MCS_4_PLCP 0x14
4471 #define IWM_RATE_VHT_MIMO2_MCS_5_PLCP 0x15
4472 #define IWM_RATE_VHT_MIMO2_MCS_6_PLCP 0x16
4473 #define IWM_RATE_VHT_MIMO2_MCS_7_PLCP 0x17
4474 #define IWM_RATE_VHT_MIMO2_MCS_8_PLCP 0x18
4475 #define IWM_RATE_VHT_MIMO2_MCS_9_PLCP 0x19
4476 #define IWM_RATE_HT_SISO_MCS_INV_PLCP 0x20
4487 IWM_RATE_1M_INDEX = 0,
4544 #define IWM_RATE_INVM_PLCP 0xff
4549 * The 32-bit value has different layouts in the low 8 bites depending on the
4553 * High-throughput (HT) rate format
4554 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
4555 * Very High-throughput (VHT) rate format
4556 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
4557 * Legacy OFDM rate format for bits 7:0
4558 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
4559 * Legacy CCK rate format for bits 7:0:
4560 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
4563 /* Bit 8: (1) HT format, (0) legacy or VHT format */
4567 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
4571 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
4580 * High-throughput (HT) rate format for bits 7:0
4582 * 2-0: MCS rate base
4583 * 0) 6 Mbps
4591 * 4-3: 0) Single stream (SISO)
4594 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
4595 * (bits 7-6 are zero)
4598 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
4599 * streams and 16-23 have three streams. We could also support MCS 32
4602 #define IWM_RATE_HT_MCS_RATE_CODE_MSK 0x7
4610 #define IWM_RATE_HT_MCS_INDEX_MSK 0x3f
4613 * Very High-throughput (VHT) rate format for bits 7:0
4615 * 3-0: VHT MCS (0-9)
4616 * 5-4: number of streams - 1:
4617 * 0) Single stream (SISO)
4622 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
4623 #define IWM_RATE_VHT_MCS_RATE_CODE_MSK 0xf
4628 * Legacy OFDM rate format for bits 7:0
4630 * 3-0: 0xD) 6 Mbps
4631 * 0xF) 9 Mbps
4632 * 0x5) 12 Mbps
4633 * 0x7) 18 Mbps
4634 * 0x9) 24 Mbps
4635 * 0xB) 36 Mbps
4636 * 0x1) 48 Mbps
4637 * 0x3) 54 Mbps
4638 * (bits 7-4 are 0)
4640 * Legacy CCK rate format for bits 7:0:
4641 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
4643 * 6-0: 10) 1 Mbps
4647 * (bit 7 is 0)
4649 #define IWM_RATE_LEGACY_RATE_MSK 0xff
4653 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
4654 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
4658 #define IWM_RATE_MCS_CHAN_WIDTH_20 (0 << IWM_RATE_MCS_CHAN_WIDTH_POS)
4663 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
4667 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
4679 /* Bit 17-18: (0) SS, (1) SS*2 */
4683 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
4687 /* Bit 20: (0) ZLF is off, (1) ZLF is on */
4691 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
4695 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
4707 /* Bit 0: (0) Don't use RTS (1) Use RTS */
4708 #define IWM_LQ_FLAG_USE_RTS_POS 0
4711 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
4715 /* Bit 4-5: Tx RTS BW Signalling
4716 * (0) No RTS BW signalling
4721 #define IWM_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWM_LQ_FLAG_RTS_BW_SIG_POS)
4725 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
4732 #define IWM_ANT_A (1 << 0)
4741 * struct iwm_lq_cmd - link quality command
4753 * @agg_disable_start_th: try-count threshold for starting aggregation.
4754 * If a frame has higher try-count, it should not be selected for
4757 * 0: no limit
4759 * 2 - 0x3f: maximal number of frames (up to 3f == 63)
4784 * END mvm/fw-api-rs.h
4788 * BEGIN mvm/fw-api-tx.h
4793 * @IWM_TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
4806 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
4807 * @IWM_TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
4819 * @IWM_TX_CMD_FLG_DUR: disable duration overwriting used in PS-Poll Assoc-id
4822 * @IWM_TX_CMD_FLG_PAPD_TYPE: 0 for reference power, 1 for nominal power
4825 #define IWM_TX_CMD_FLG_PROT_REQUIRE (1 << 0)
4854 * enum iwm_tx_pm_timeouts - pm timeout values in TX command
4860 IWM_PM_FRAME_NONE = 0,
4868 #define IWM_TX_CMD_SEC_WEP 0x01
4869 #define IWM_TX_CMD_SEC_CCM 0x02
4870 #define IWM_TX_CMD_SEC_TKIP 0x03
4871 #define IWM_TX_CMD_SEC_EXT 0x04
4872 #define IWM_TX_CMD_SEC_MSK 0x07
4874 #define IWM_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
4875 #define IWM_TX_CMD_SEC_KEY128 0x08
4881 * bits 0:2 - security control (IWM_TX_CMD_SEC_*)
4882 * bit 3 - immediate ACK required
4883 * bit 4 - rate is taken from STA table
4884 * bit 5 - frame belongs to BA stream
4885 * bit 6 - immediate BA response expected
4886 * bit 7 - unused
4887 * bits 8:15 - Station ID
4888 * bits 16:31 - rate
4890 #define IWM_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
4891 #define IWM_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
4892 #define IWM_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
4893 #define IWM_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
4894 #define IWM_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
4895 #define IWM_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
4897 #define IWM_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
4901 * TX command Frame life time in us - to be written in pm_frame_timeout
4903 #define IWM_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
4906 #define IWM_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
4909 * TID for non QoS frames - to be written in tid_tspec
4912 #define IWM_TID_NON_QOS 0
4916 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
4925 * enum iwm_tx_offload_assist_flags_pos - set %iwm_tx_cmd offload_assist values
4937 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
4939 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
4941 #define IWM_TX_CMD_OFFLD_IP_HDR (1 << 0)
4950 * struct iwm_tx_cmd - TX command struct to FW
4951 * ( IWM_TX_CMD = 0x1c )
4960 * Applied if IWM_TX_CMD_FLG_STA_RATE_MSK is set, normally 0 for data frames.
4965 * btkill_cnd + reserved), first 32 bits. "0" disables usage.
4971 * @driver_txop: duration od EDCA TXOP, in 32-usec units. Set this if not
4979 * + 8-byte MIC (not used for CCM/WEP)
4980 * It does not include post-MAC padding, i.e.,
4982 * Range of len: 14-2342 bytes.
5011 uint8_t payload[0];
5012 struct ieee80211_frame hdr[0];
5025 #define IWM_TX_STATUS_MSK 0x000000ff
5026 #define IWM_TX_STATUS_SUCCESS 0x01
5027 #define IWM_TX_STATUS_DIRECT_DONE 0x02
5029 #define IWM_TX_STATUS_POSTPONE_DELAY 0x40
5030 #define IWM_TX_STATUS_POSTPONE_FEW_BYTES 0x41
5031 #define IWM_TX_STATUS_POSTPONE_BT_PRIO 0x42
5032 #define IWM_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
5033 #define IWM_TX_STATUS_POSTPONE_CALC_TTAK 0x44
5035 #define IWM_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
5036 #define IWM_TX_STATUS_FAIL_SHORT_LIMIT 0x82
5037 #define IWM_TX_STATUS_FAIL_LONG_LIMIT 0x83
5038 #define IWM_TX_STATUS_FAIL_UNDERRUN 0x84
5039 #define IWM_TX_STATUS_FAIL_DRAIN_FLOW 0x85
5040 #define IWM_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
5041 #define IWM_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
5042 #define IWM_TX_STATUS_FAIL_DEST_PS 0x88
5043 #define IWM_TX_STATUS_FAIL_HOST_ABORTED 0x89
5044 #define IWM_TX_STATUS_FAIL_BT_RETRY 0x8a
5045 #define IWM_TX_STATUS_FAIL_STA_INVALID 0x8b
5046 #define IWM_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
5047 #define IWM_TX_STATUS_FAIL_TID_DISABLE 0x8d
5048 #define IWM_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
5049 #define IWM_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f
5050 #define IWM_TX_STATUS_FAIL_FW_DROP 0x90
5051 #define IWM_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91
5052 #define IWM_TX_STATUS_INTERNAL_ABORT 0x92
5053 #define IWM_TX_MODE_MSK 0x00000f00
5054 #define IWM_TX_MODE_NO_BURST 0x00000000
5055 #define IWM_TX_MODE_IN_BURST_SEQ 0x00000100
5056 #define IWM_TX_MODE_FIRST_IN_BURST 0x00000200
5057 #define IWM_TX_QUEUE_NUM_MSK 0x0001f000
5058 #define IWM_TX_NARROW_BW_MSK 0x00060000
5059 #define IWM_TX_NARROW_BW_1DIV2 0x00020000
5060 #define IWM_TX_NARROW_BW_1DIV4 0x00040000
5061 #define IWM_TX_NARROW_BW_1DIV8 0x00060000
5070 #define IWM_AGG_TX_STATE_STATUS_MSK 0x0fff
5071 #define IWM_AGG_TX_STATE_TRANSMITTED 0x0000
5072 #define IWM_AGG_TX_STATE_UNDERRUN 0x0001
5073 #define IWM_AGG_TX_STATE_BT_PRIO 0x0002
5074 #define IWM_AGG_TX_STATE_FEW_BYTES 0x0004
5075 #define IWM_AGG_TX_STATE_ABORT 0x0008
5076 #define IWM_AGG_TX_STATE_LAST_SENT_TTL 0x0010
5077 #define IWM_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020
5078 #define IWM_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040
5079 #define IWM_AGG_TX_STATE_SCD_QUERY 0x0080
5080 #define IWM_AGG_TX_STATE_TEST_BAD_CRC32 0x0100
5081 #define IWM_AGG_TX_STATE_RESPONSE 0x01ff
5082 #define IWM_AGG_TX_STATE_DUMP_TX 0x0200
5083 #define IWM_AGG_TX_STATE_DELAY_TX 0x0400
5085 #define IWM_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWM_AGG_TX_STATE_TRY_CNT_POS)
5101 * IWM_REPLY_TX = 0x1c (response)
5111 * frames that used block-acknowledge. All frames were transmitted at
5115 * Note that, for aggregation, ACK (block-ack) status is not delivered
5116 * here; block-ack has not been received by the time the device records
5124 * struct iwm_agg_tx_status - per packet TX aggregation status
5131 #if 0
5132 /* OpenBSD update - convert code to use this */
5142 * bits [3:0] initial rate index
5144 * bit-7 invalid rate indication
5146 #define IWM_TX_RES_INIT_RATE_INDEX_MSK 0x0f
5147 #define IWM_TX_RES_RATE_TABLE_COLOR_MSK 0x70
5148 #define IWM_TX_RES_INV_RATE_INDEX_MSK 0x80
5150 #define IWM_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
5154 * struct iwm_tx_resp - notifies that fw is TXing a packet
5155 * ( IWM_REPLY_TX = 0x1c )
5160 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
5162 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
5163 * for agg: RTS + CTS + aggregation tx time + block-ack time.
5174 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
5176 * @status: for non-agg: frame status IWM_TX_STATUS_*
5209 * struct iwm_ba_notif - notifies about reception of BA
5210 * ( IWM_BA_NOTIF = 0xc5 )
5212 * @sta_id: Index of recipient (BA-sending) station in fw's station table
5223 * for Tx-ing then this value will be set to 0 by FW.
5243 * struct iwm_mac_beacon_cmd - beacon template command
5256 struct ieee80211_frame frame[0];
5273 * struct iwm_tx_path_flush_cmd -- queue/FIFO flush command
5285 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command
5297 * iwm_get_scd_ssn - returns the SSN of the SCD
5298 * @tx_resp: the Tx response from the fw (agg or non-agg)
5311 return le32_to_cpup((uint32_t *)&tx_resp->status +
5312 tx_resp->frame_count) & 0xfff;
5316 * END mvm/fw-api-tx.h
5320 * BEGIN mvm/fw-api-scan.h
5324 * struct iwm_scd_txq_cfg_cmd - New txq hw scheduler config command
5329 * @enable: 1 queue enable, 0 queue disable
5330 * @aggregate: 1 aggregated queue, 0 otherwise
5366 #define IWM_SCAN_CHANNEL_TYPE_ACTIVE (1 << 0)
5367 #define IWM_SCAN_CHANNEL_NSSIDS(x) (((1 << (x)) - 1) << 1)
5373 * struct iwm_ssid_ie - directed scan network information element
5403 * iwm_scan_schedule_lmac - schedule of scan offload
5415 * iwm_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
5433 * iwm_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
5434 * @flags: bits 1-20: directed scan to i'th ssid
5436 * @channel_number: channel number 1-13 etc
5448 * iwm_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
5457 /* iwm_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
5470 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2
5484 #define IWM_SCAN_CHANNEL_FLAG_EBS (1 << 0)
5488 /* iwm_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
5492 * 1 - EBS is disabled.
5493 * 2 - every second scan will be full scan(and so on).
5509 * @IWM_LMAC_SCAN_FLAGS_RRM_ENABLED: insert WFA vendor-specific TPC report
5515 #define IWM_LMAC_SCAN_FLAG_PASS_ALL (1 << 0)
5525 #define IWM_SCAN_PRIORITY_LOW 0
5530 * iwm_scan_req_lmac - SCAN_REQUEST_CMD_API_S_VER_1
5533 * @active-dwell: dwell time for active channels
5534 * @passive-dwell: dwell time for passive channels
5535 * @fragmented-dwell: dwell time for fragmented passive scan
5582 * iwm_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
5599 * struct iwm_scan_results_notif - scan results for one channel -
5602 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
5615 #define IWM_SCAN_CLIENT_SCHED_SCAN (1 << 0)
5620 * iwm_scan_offload_blacklist - IWM_SCAN_OFFLOAD_BLACKLIST_S
5623 * @client_bitmap: clients ignore this entry - enum scan_framework_client
5635 #define IWM_SCAN_OFFLOAD_SELECT_2_4 0x4
5636 #define IWM_SCAN_OFFLOAD_SELECT_5_2 0x8
5637 #define IWM_SCAN_OFFLOAD_SELECT_ANY 0xc
5640 * iwm_scan_offload_profile - IWM_SCAN_OFFLOAD_PROFILE_S
5642 * @unicast_cipher: encryption olgorithm to match - bitmap
5643 * @aut_alg: authentication olgorithm to match - bitmap
5646 * @client_bitmap: clients waiting for match - enum scan_framework_client
5659 * iwm_scan_offload_profile_cfg - IWM_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
5666 * @active_clients: active clients bitmap - enum scan_framework_client
5693 * struct iwm_lmac_scan_complete_notif - notifies end of scanning (all channels)
5717 * 8-bit mask (see IWM_SCAN_MASK).
5722 #define IWM_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)
5741 /* Bits 26-31 are for num of channels in channel_array */
5745 #define IWM_SCAN_CONFIG_RATE_6M (1 << 0)
5759 /* Bits 16-27 are for supported rates */
5762 #define IWM_CHANNEL_FLAG_EBS (1 << 0)
5770 * @tx_chains: valid_tx antenna - ANT_* definitions
5771 * @rx_chains: valid_rx antenna - ANT_* definitions
5772 * @legacy_rates: default legacy rates - enum scan_config_rates
5781 * @channel_flags: default channel flags - enum iwm_channel_flags
5811 #define IWM_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)
5814 #define IWM_UMAC_SCAN_UID_TYPE_OFFSET 0
5817 #define IWM_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)
5844 #define IWM_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)
5849 * @flags: bitmap - 0-19: directed scan to i'th ssid.
5850 * @channel_num: channel number 1-13 etc.
5856 #define IWM_SCAN_CHANNEL_UMAC_NSSIDS(x) ((1 << (x)) - 1)
5865 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
5875 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5894 * struct iwm_scan_req_umac_tail - the rest of the UMAC scan request command
5924 #define IWM_SCAN_LB_LMAC_IDX 0
5931 * @ooc_priority: out of channel priority - &enum iwl_scan_priority
5945 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
5947 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
6072 * struct iwm_scan_offload_profile_match - match information
6090 * struct iwm_scan_offload_profiles_query - match results query response
6115 * struct iwm_umac_scan_iter_complete_notif - notifies end of scanning iteration
6137 #define IWM_GSCAN_START_CMD 0x0
6138 #define IWM_GSCAN_STOP_CMD 0x1
6139 #define IWM_GSCAN_SET_HOTLIST_CMD 0x2
6140 #define IWM_GSCAN_RESET_HOTLIST_CMD 0x3
6141 #define IWM_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4
6142 #define IWM_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5
6143 #define IWM_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD
6144 #define IWM_GSCAN_HOTLIST_CHANGE_EVENT 0xFE
6145 #define IWM_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF
6148 * END mvm/fw-api-scan.h
6152 * BEGIN mvm/fw-api-sta.h
6171 * @IWM_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
6194 #define IWM_STA_FLG_MAX_AGG_SIZE_8K (0 << IWM_STA_FLG_MAX_AGG_SIZE_SHIFT)
6211 #define IWM_STA_FLG_FAT_EN_20MHZ (0 << 26)
6217 #define IWM_STA_FLG_MIMO_EN_SISO (0 << 28)
6232 * @IWM_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
6233 * station info array (1 - n 1X mode)
6240 #define IWM_STA_KEY_FLG_NO_ENC (0 << 0)
6241 #define IWM_STA_KEY_FLG_WEP (1 << 0)
6242 #define IWM_STA_KEY_FLG_CCM (2 << 0)
6243 #define IWM_STA_KEY_FLG_TKIP (3 << 0)
6244 #define IWM_STA_KEY_FLG_EXT (4 << 0)
6245 #define IWM_STA_KEY_FLG_CMAC (6 << 0)
6246 #define IWM_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)
6247 #define IWM_STA_KEY_FLG_EN_MSK (7 << 0)
6267 #define IWM_STA_MODIFY_QUEUE_REMOVAL (1 << 0)
6283 * @IWM_STA_SLEEP_STATE_MOREDATA: set more-data bit on
6286 #define IWM_STA_SLEEP_STATE_AWAKE 0
6287 #define IWM_STA_SLEEP_STATE_PS_POLL (1 << 0)
6292 #define IWM_STA_ID_SEED (0x0f)
6293 #define IWM_STA_ID_POS (0)
6296 #define IWM_STA_COLOR_SEED (0x7)
6306 #define IWM_STA_KEY_IDX_INVALID (0xff)
6313 * struct iwm_keyinfo - key information
6316 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
6318 * @key: 16-byte unicast decryption key
6320 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
6321 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
6336 #define IWM_ADD_STA_STATUS_MASK 0xFF
6337 #define IWM_ADD_STA_BAID_VALID_MASK 0x8000
6338 #define IWM_ADD_STA_BAID_MASK 0x7F00
6342 * struct iwm_add_sta_cmd_v7 - Add/modify a station in the fw's sta table.
6343 * ( REPLY_ADD_STA = 0x18 )
6344 * @add_modify: 1: modify existing, 0: add new station
6352 * alone. 1 - modify, 0 - don't change.
6355 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
6358 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
6360 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
6363 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
6366 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
6367 * mac-addr.
6371 * The device contains an internal table of per-station information, with info
6376 * entry, or modifying a pre-existing one.
6401 * struct iwm_add_sta_cmd - Add/modify a station in the fw's sta table.
6402 * ( REPLY_ADD_STA = 0x18 )
6404 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
6413 * alone. 1 - modify, 0 - don't change.
6418 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
6421 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
6423 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
6426 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
6430 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
6431 * mac-addr.
6440 * The device contains an internal table of per-station information, with info
6445 * entry, or modifying a pre-existing one.
6475 * ( REPLY_ADD_STA = 0x18 )
6476 * @IWM_STA_LINK: Link station - normal RX and TX traffic.
6483 #define IWM_STA_LINK 0
6490 * struct iwm_add_sta_key_common - add/modify sta key common part
6491 * ( REPLY_ADD_STA_KEY = 0x17 )
6507 * struct iwm_add_sta_key_cmd_v1 - add/modify sta key
6511 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
6521 * struct iwm_add_sta_key_cmd - add/modify sta key
6542 #define IWM_ADD_STA_SUCCESS 0x1
6543 #define IWM_ADD_STA_STATIONS_OVERLOAD 0x2
6544 #define IWM_ADD_STA_IMMEDIATE_BA_FAILURE 0x4
6545 #define IWM_ADD_STA_MODIFY_NON_EXISTING_STA 0x8
6548 * struct iwm_rm_sta_cmd - Add / modify a station in the fw's station table
6549 * ( IWM_REMOVE_STA = 0x19 )
6559 * ( IWM_MGMT_MCAST_KEY = 0x1f )
6593 struct iwm_wep_key wep_key[0];
6600 #define IWM_BT_COEX_DISABLE 0x0
6601 #define IWM_BT_COEX_NW 0x1
6602 #define IWM_BT_COEX_BT 0x2
6603 #define IWM_BT_COEX_WIFI 0x3
6606 #define IWM_BT_COEX_MPLUT_ENABLED (1 << 0)
6614 * struct iwm_bt_coex_cmd - bt coex configuration command
6627 * Location Aware Regulatory (LAR) API - MCC updates
6631 * struct iwm_mcc_update_cmd_v1 - Request the device to update geographic
6633 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6647 * struct iwm_mcc_update_cmd - Request the device to update geographic
6649 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6667 * iwm_mcc_update_resp_v1 - response to MCC_UPDATE_CMD.
6686 uint32_t channels[0];
6690 * iwm_mcc_update_resp_v2 - response to MCC_UPDATE_CMD.
6713 uint32_t channels[0];
6716 #define IWM_GEO_NO_INFO 0
6717 #define IWM_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)
6720 * iwm_mcc_update_resp_v3 - response to MCC_UPDATE_CMD.
6743 uint32_t channels[0];
6747 * struct iwm_mcc_chub_notif - chub notifies of mcc change
6748 * (MCC_CHUB_UPDATE_CMD = 0xc9)
6754 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
6767 #define IWM_MCC_RESP_NEW_CHAN_PROFILE 0
6777 #define IWM_MCC_SOURCE_OLD_FW 0
6787 #define IWM_MCC_SOURCE_GET_CURRENT 0x10
6788 #define IWM_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11
6791 * struct iwm_dts_measurement_notif_v1 - measurements notification
6802 * struct iwm_dts_measurement_notif_v2 - measurements notification
6816 * Some cherry-picked definitions
6826 * former flags field, since that's always 0 on commands and thus can
6836 return cmdid & 0xff;
6842 return ((cmdid & 0xff00) >> 8);
6848 return ((cmdid & 0xff0000) >> 16);
6885 #define IWM_MAX_CMD_PAYLOAD_SIZE ((4096 - 4) - sizeof(struct iwm_cmd_header))
6886 #define IWM_CMD_FAILED_MSK 0x40
6903 uint8_t data_wide[IWM_DEF_CMD_PAYLOAD_SIZE -
6918 * 28-26: Reserved
6923 * 21-16: RX queue
6924 * 15-14: Reserved
6925 * 13-00: RX frame size
6932 #define IWM_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
6933 #define IWM_FH_RSCSR_FRAME_INVALID 0x55550000
6934 #define IWM_FH_RSCSR_FRAME_ALIGN 0x40
6938 #define IWM_FH_RSCSR_RXQ_MASK 0x3F0000
6944 return le32toh(pkt->len_n_flags) & IWM_FH_RSCSR_FRAME_SIZE_MSK;
6951 return iwm_rx_packet_len(pkt) - sizeof(pkt->hdr);
6955 #define IWM_MIN_DBM -100
6956 #define IWM_MAX_DBM -33 /* realistic guess */
6959 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
6962 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6965 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
6974 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
6978 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \