Lines Matching defs:enable
97 #define IWM_CSR_INT_MASK (0x00c) /* host interrupt enable */
100 #define IWM_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
610 /* enable the ID buf for read */
646 /* Used to enable DBGM */
1611 * 31-30: Rx DMA channel enable: '00' off/pause, '01' pause at end of frame,
1705 * 31-30: Tx DMA channel enable: '00' off/pause, '01' pause at end of frame,
2208 /* This defines the bitmap of various calibrations to enable in both
3828 * @IWM_MAC_PROT_FLG_HT_PROT: enable HT protection
4196 * @IWM_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
4197 * @IWM_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
4933 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
4934 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum
5329 * @enable: 1 queue enable, 0 queue disable
5340 uint8_t enable;
6346 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
6405 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable