1239 	IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);  in iwm_enable_interrupts()
1245 	IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);  in iwm_restore_interrupts()
1252 	IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);  in iwm_disable_interrupts()
1255 	IWM_WRITE(sc, IWM_CSR_INT, ~0);  in iwm_disable_interrupts()
1256 	IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, ~0);  in iwm_disable_interrupts()
1269 	IWM_WRITE(sc, IWM_CSR_DRAM_INT_TBL_REG,  in iwm_ict_reset()
1279 	IWM_WRITE(sc, IWM_CSR_INT, ~0);  in iwm_ict_reset()
1326 			IWM_WRITE(sc,  in iwm_stop_device()
1411 	IWM_WRITE(sc, IWM_CSR_HW_IF_CONFIG_REG,  in iwm_nic_config()
1485 	IWM_WRITE(sc, IWM_RFH_Q0_FRBDCB_WIDX_TRG, 8);  in iwm_nic_rx_mq_init()
1501 	IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);  in iwm_nic_rx_legacy_init()
1502 	IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);  in iwm_nic_rx_legacy_init()
1503 	IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RDPTR, 0);  in iwm_nic_rx_legacy_init()
1504 	IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);  in iwm_nic_rx_legacy_init()
1507 	IWM_WRITE(sc,  in iwm_nic_rx_legacy_init()
1512 	IWM_WRITE(sc,  in iwm_nic_rx_legacy_init()
1524 	IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG,  in iwm_nic_rx_legacy_init()
1540 	IWM_WRITE(sc, IWM_FH_RSCSR_CHNL0_WPTR, 8);  in iwm_nic_rx_legacy_init()
1566 	IWM_WRITE(sc, IWM_FH_KW_MEM_ADDR_REG, sc->kw_dma.paddr >> 4);  in iwm_nic_tx_init()
1573 		IWM_WRITE(sc, IWM_FH_MEM_CBBC_QUEUE(qid),  in iwm_nic_tx_init()
1631 	IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, qid << 8 | 0);  in iwm_enable_txq()
1765 		IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(chnl),  in iwm_trans_pcie_fw_alive()
2439 	IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2442 	IWM_WRITE(sc, IWM_FH_SRVC_CHNL_SRAM_ADDR_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2445 	IWM_WRITE(sc, IWM_FH_TFDIB_CTRL0_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2448 	IWM_WRITE(sc, IWM_FH_TFDIB_CTRL1_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2452 	IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_BUF_STS_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2457 	IWM_WRITE(sc, IWM_FH_TCSR_CHNL_TX_CONFIG_REG(IWM_FH_SRVC_CHNL),  in iwm_pcie_load_firmware_chunk()
2518 			IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, val);  in iwm_pcie_load_cpu_sections_8000()
2530 			IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFF);  in iwm_pcie_load_cpu_sections_8000()
2532 			IWM_WRITE(sc, IWM_FH_UCODE_LOAD_STATUS, 0xFFFFFFFF);  in iwm_pcie_load_cpu_sections_8000()
2614 	IWM_WRITE(sc, IWM_CSR_RESET, 0);  in iwm_pcie_load_given_ucode()
2654 	IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);  in iwm_enable_fw_load_int()
2671 	IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF);  in iwm_start_fw()
2676 	IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);  in iwm_start_fw()
2677 	IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR,  in iwm_start_fw()
2681 	IWM_WRITE(sc, IWM_CSR_INT, 0xFFFFFFFF);  in iwm_start_fw()
2700 	IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);  in iwm_start_fw()
2701 	IWM_WRITE(sc, IWM_CSR_UCODE_DRV_GP1_CLR, IWM_CSR_UCODE_SW_BIT_RFKILL);  in iwm_start_fw()
3935 	IWM_WRITE(sc, IWM_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);  in iwm_tx()
5668 	IWM_WRITE(sc, wreg, rounddown2(hw, 8));  in iwm_notif_intr()
5680 	IWM_WRITE(sc, IWM_CSR_INT_MASK, 0);  in iwm_intr()
5720 	IWM_WRITE(sc, IWM_CSR_INT, r1 | ~sc->sc_intmask);  in iwm_intr()
5773 		IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_TX_MASK);  in iwm_intr()
5790 		IWM_WRITE(sc, IWM_CSR_INT, IWM_CSR_INT_BIT_RX_PERIODIC);  in iwm_intr()
5799 		IWM_WRITE(sc, IWM_CSR_FH_INT_STATUS, IWM_CSR_FH_INT_RX_MASK);  in iwm_intr()
6127 	IWM_WRITE(sc, IWM_CSR_INT, 0xffffffff);  in iwm_attach()