Lines Matching +full:0 +full:x10e
61 #define BIU_BLOCK (0 << _BLK_REG_SHFT)
66 #define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
67 #define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
68 #define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
69 #define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
70 #define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
71 #define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
72 #define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
73 #define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
74 #define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
75 #define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
76 #define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
77 #define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
78 #define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
79 #define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
88 #define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00) /* Flash Access Address */
89 #define BIU2400_FLASH_DATA (BIU_BLOCK+0x04) /* Flash Data */
90 #define BIU2400_CSR (BIU_BLOCK+0x08) /* ISP Control/Status */
91 #define BIU2400_ICR (BIU_BLOCK+0x0C) /* ISP to PCI Interrupt Control */
92 #define BIU2400_ISR (BIU_BLOCK+0x10) /* ISP to PCI Interrupt Status */
94 #define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
95 #define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
96 #define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
97 #define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
99 #define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
100 #define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
102 #define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
103 #define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
105 #define BIU2400_R2HSTS (BIU_BLOCK+0x44) /* RISC to Host Status */
107 #define BIU2400_HCCR (BIU_BLOCK+0x48) /* Host Command and Control Status */
108 #define BIU2400_GPIOD (BIU_BLOCK+0x4C) /* General Purpose I/O Data */
109 #define BIU2400_GPIOE (BIU_BLOCK+0x50) /* General Purpose I/O Enable */
110 #define BIU2400_IOBBA (BIU_BLOCK+0x54) /* I/O Bus Base Address */
111 #define BIU2400_HSEMA (BIU_BLOCK+0x58) /* Host-to-Host Semaphore */
121 #define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
124 #define BIU2400_SOFT_RESET (1 << 0)
127 #define BIU2400_ICR_ENA_RISC_INT 0x8
131 #define BIU2400_ISR_RISC_INT 0x8
134 #define HCCR_2400_CMD_NOP 0x00000000
135 #define HCCR_2400_CMD_RESET 0x10000000
136 #define HCCR_2400_CMD_CLEAR_RESET 0x20000000
137 #define HCCR_2400_CMD_PAUSE 0x30000000
138 #define HCCR_2400_CMD_RELEASE 0x40000000
139 #define HCCR_2400_CMD_SET_HOST_INT 0x50000000
140 #define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
141 #define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
143 #define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
151 #define INMAILBOX0 (MBOX_BLOCK+0x0)
152 #define INMAILBOX1 (MBOX_BLOCK+0x2)
153 #define INMAILBOX2 (MBOX_BLOCK+0x4)
154 #define INMAILBOX3 (MBOX_BLOCK+0x6)
155 #define INMAILBOX4 (MBOX_BLOCK+0x8)
156 #define INMAILBOX5 (MBOX_BLOCK+0xA)
157 #define INMAILBOX6 (MBOX_BLOCK+0xC)
158 #define INMAILBOX7 (MBOX_BLOCK+0xE)
160 #define OUTMAILBOX0 (MBOX_BLOCK+0x0)
161 #define OUTMAILBOX1 (MBOX_BLOCK+0x2)
162 #define OUTMAILBOX2 (MBOX_BLOCK+0x4)
163 #define OUTMAILBOX3 (MBOX_BLOCK+0x6)
164 #define OUTMAILBOX4 (MBOX_BLOCK+0x8)
165 #define OUTMAILBOX5 (MBOX_BLOCK+0xA)
166 #define OUTMAILBOX6 (MBOX_BLOCK+0xC)
167 #define OUTMAILBOX7 (MBOX_BLOCK+0xE)
173 /* if timeout == 0, then default timeout is picked */
188 (mbxp)->ibitm = ~0; \
189 (mbxp)->obitm = ~0; \
190 (mbxp)->param[0] = code; \
206 ISP_WRITE(isp, BIU2400_ICR, 0)
215 #define ISP2400_NVRAM_PORT_ADDR(c) (0x100 * (c) + 0x80)
230 (((uint64_t)(c)[27]) << 0))
240 (((uint64_t)(c)[35]) << 0))
257 #define ISP24XX_BASE_ADDR 0x7ff00000
258 #define ISP24XX_FLT_ADDR 0x11400
261 #define ISP25XX_FLT_ADDR 0x50400
263 #define ISP27XX_BASE_ADDR 0x7f800000
264 #define ISP27XX_FLT_ADDR (0x3F1000 / 4)
266 #define ISP28XX_BASE_ADDR 0x7f7d0000
267 #define ISP28XX_FLT_ADDR (0x11000 / 4)
271 #define FLT_MAX_REGIONS 0xFF
274 #define ISP2XXX_FLT_VERSION(c) ((c)[0] | ((c)[1] << 8))
278 ((c)[0 + FLT_REGION_SIZE * o] | ((c)[1 + FLT_REGION_SIZE * o] << 8))
282 ((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) | \
287 ((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) | \
292 ((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) | \
306 #define FLT_REG_FW 0x01
307 #define FLT_REG_BOOT_CODE 0x07
308 #define FLT_REG_VPD_0 0x14
309 #define FLT_REG_NVRAM_0 0x15
310 #define FLT_REG_VPD_1 0x16
311 #define FLT_REG_NVRAM_1 0x17
312 #define FLT_REG_VPD_2 0xd4
313 #define FLT_REG_NVRAM_2 0xd5
314 #define FLT_REG_VPD_3 0xd6
315 #define FLT_REG_NVRAM_3 0xd7
316 #define FLT_REG_FDT 0x1a
317 #define FLT_REG_FLT 0x1c
318 #define FLT_REG_NPIV_CONF_0 0x29
319 #define FLT_REG_NPIV_CONF_1 0x2a
320 #define FLT_REG_GOLD_FW 0x2f
321 #define FLT_REG_FCP_PRIO_0 0x87
322 #define FLT_REG_FCP_PRIO_1 0x88
325 #define FLT_REG_IMG_PRI_27XX 0x95
326 #define FLT_REG_IMG_SEC_27XX 0x96
327 #define FLT_REG_FW_SEC_27XX 0x02
328 #define FLT_REG_BOOTLOAD_SEC_27XX 0x9
329 #define FLT_REG_VPD_SEC_27XX_0 0x50
330 #define FLT_REG_VPD_SEC_27XX_1 0x52
331 #define FLT_REG_VPD_SEC_27XX_2 0xd8
332 #define FLT_REG_VPD_SEC_27XX_3 0xda
335 #define FLT_REG_AUX_IMG_PRI_28XX 0x125
336 #define FLT_REG_AUX_IMG_SEC_28XX 0x126
337 #define FLT_REG_NVRAM_SEC_28XX_0 0x10d
338 #define FLT_REG_NVRAM_SEC_28XX_1 0x10f
339 #define FLT_REG_NVRAM_SEC_28XX_2 0x111
340 #define FLT_REG_NVRAM_SEC_28XX_3 0x113
341 #define FLT_REG_VPD_SEC_28XX_0 0x10c
342 #define FLT_REG_VPD_SEC_28XX_1 0x10e
343 #define FLT_REG_VPD_SEC_28XX_2 0x110
344 #define FLT_REG_VPD_SEC_28XX_3 0x112
346 #define ISP27XX_IMG_STATUS_VER_MAJOR 0x01
347 #define ISP27XX_IMG_STATUS_VER_MINOR 0x00
348 #define ISP27XX_IMG_STATUS_SIGN 0xfacefade
349 #define ISP28XX_IMG_STATUS_SIGN 0xfacefadf
350 #define ISP28XX_AUX_IMG_STATUS_SIGN 0xfacefaed
351 #define ISP27XX_DEFAULT_IMAGE 0