Lines Matching +full:scu +full:- +full:index
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
60 * @brief This file contains the constants and structures for the SCU memory
72 // Generate a value for an SCU register
76 // Generate a bit value for an SCU register
88 // Unions for bitfield definitions of SCU Registers
287 // --------------------------------------------------------------------------
314 // --------------------------------------------------------------------------
496 //* SCU Link Layer Registers
529 //* SCU SAS Maximum Arbitration Wait Time Timeout Register
909 // ----------------------------------------------------------------------------
921 // ----------------------------------------------------------------------------
962 * See SCU SMU Specification on how this register space is used.
1037 // MSI-X registers not included
1057 * @brief These are the SCU SDMA Registers
1058 * See SCU SDMA specification on how these registers are used.
1088 //* SCU Link Registers
1128 * @brief These are the SCU Transport Layer registers see SSPTL spec for how
1261 * @brief SCU Link Layer Registers
1262 * See the SCU SSLL Specification on how these registers are used.
1397 // 0x0110 - 0x011C PLAPRDCTRLxREG
1411 // ----------------------------------------------------------------------------
1413 // ----------------------------------------------------------------------------
1430 * @brief SCU SGPIO Registers
1431 * See the SCU SGPIO Specification on how these registers are used.
1460 //* Access additional entries by SCU_VIIT_BASE + index * 0x10
1470 //* SCU PORT TASK SCHEDULER REGISTERS
1497 * See the SCU SCHED Specification on how these registers are used.
1511 * See the SCU SCHED Specification on how these registers are used.
1641 * See SCU AFE Specification for use of these registers.
1643 * @note For ARLINGTON_BUILD see the SCU AFE specification.
1653 // 0x44 - 0x4c
1657 // 0xd0 - 0xfc
1721 // 0x0060-0x006c
1735 // 0x0088-0x00fc
1746 * See SCU AFE Specification for use of these registers.
1759 // 0x0014 - 0x001c
1765 // 0x0028 - 0x003C
1773 // 0x0070 - 0x007c
1781 // 0x00B0 - 0x0100
1789 // 0x0110 - 0x011C
1795 // 0x0128 - 0x012c
1803 // 0x0154 - 0x017c
1811 // 0x01B0 - 0x01BC
1815 // 0x01c4 - 0x01fc
1817 // 0x0200 - 0x05fc
1820 // 0x0600 - 0x06FC
1850 // 0x0018-0x007c
1858 // 0x008C-0x00fc
1882 // 0x012c-0x01a8 AFE_DFX_P0_DRx
1886 // 0x01b0-0x020c AFE_DFX_P0_IRx
1892 // 0x0218-0x245 AFE_DFX_P1_DRx
1894 // 0x0258-0x029c
1896 // 0x02a0-0x02bc AFE_DFX_P1_IRx
1898 // 0x02c0-0x2fc
1921 // 0x032c-0x07fc
1924 // 0x0800-0x0bfc
1927 // 0x0c00-0x0ffc
2053 * @brief The SCU Hardware pairs up the TL registers with the LL registers
2067 * @brief SCU Protocol Engine Memory mapped register space. These
2069 * at most two PEG for a single SCU part.
2087 * @brief SCU regsiters including both PEG registers if we turn on that
2091 * See SCU SMU Specification for how these registers are mapped.
2096 // 0x0000 - PEG 0
2099 // 0x6000 - SDMA and Miscellaneous
2109 // 0x8000 - PEG 1
2112 // 0xE000 - AFE Registers