Lines Matching +full:0 +full:x0310
91 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_SHIFT (0UL)
92 #define SMU_POST_CONTEXT_PORT_CONTEXT_INDEX_MASK (0x00000FFFUL)
94 #define SMU_POST_CONTEXT_PORT_LOGICAL_PORT_INDEX_MASK (0x0000F000UL)
96 #define SMU_POST_CONTEXT_PORT_PROTOCOL_ENGINE_MASK (0x00030000UL)
98 #define SMU_POST_CONTEXT_PORT_COMMAND_CONTEXT_MASK (0x00FC0000UL)
99 #define SMU_POST_CONTEXT_PORT_RESERVED_MASK (0xFF000000UL)
106 #define SMU_INTERRUPT_STATUS_COMPLETION_MASK (0x80000000UL)
108 #define SMU_INTERRUPT_STATUS_QUEUE_SUSPEND_MASK (0x00000002UL)
109 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_SHIFT (0UL)
110 #define SMU_INTERRUPT_STATUS_QUEUE_ERROR_MASK (0x00000001UL)
111 #define SMU_INTERRUPT_STATUS_RESERVED_MASK (0x7FFFFFFCUL)
122 #define SMU_INTERRUPT_MASK_COMPLETION_MASK (0x80000000UL)
124 #define SMU_INTERRUPT_MASK_QUEUE_SUSPEND_MASK (0x00000002UL)
125 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_SHIFT (0UL)
126 #define SMU_INTERRUPT_MASK_QUEUE_ERROR_MASK (0x00000001UL)
127 #define SMU_INTERRUPT_MASK_RESERVED_MASK (0x7FFFFFFCUL)
137 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_SHIFT (0UL)
138 #define SMU_INTERRUPT_COALESCING_CONTROL_TIMER_MASK (0x0000001FUL)
140 #define SMU_INTERRUPT_COALESCING_CONTROL_NUMBER_MASK (0x0000FF00UL)
141 #define SMU_INTERRUPT_COALESCING_CONTROL_RESERVED_MASK (0xFFFF00E0UL)
147 #define SMU_TASK_CONTEXT_RANGE_START_SHIFT (0UL)
148 #define SMU_TASK_CONTEXT_RANGE_START_MASK (0x00000FFFUL)
150 #define SMU_TASK_CONTEXT_RANGE_ENDING_MASK (0x0FFF0000UL)
152 #define SMU_TASK_CONTEXT_RANGE_ENABLE_MASK (0x80000000UL)
153 #define SMU_TASK_CONTEXT_RANGE_RESERVED_MASK (0x7000F000UL)
163 #define SMU_COMPLETION_QUEUE_PUT_POINTER_SHIFT (0UL)
164 #define SMU_COMPLETION_QUEUE_PUT_POINTER_MASK (0x00003FFFUL)
166 #define SMU_COMPLETION_QUEUE_PUT_CYCLE_BIT_MASK (0x00008000UL)
168 #define SMU_COMPLETION_QUEUE_PUT_EVENT_POINTER_MASK (0x03FF0000UL)
170 #define SMU_COMPLETION_QUEUE_PUT_EVENT_CYCLE_BIT_MASK (0x04000000UL)
171 #define SMU_COMPLETION_QUEUE_PUT_RESERVED_MASK (0xF8004000UL)
181 #define SMU_COMPLETION_QUEUE_GET_POINTER_SHIFT (0UL)
182 #define SMU_COMPLETION_QUEUE_GET_POINTER_MASK (0x00003FFFUL)
184 #define SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_MASK (0x00008000UL)
186 #define SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK (0x03FF0000UL)
188 #define SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_MASK (0x04000000UL)
190 #define SMU_COMPLETION_QUEUE_GET_ENABLE_MASK (0x40000000UL)
192 #define SMU_COMPLETION_QUEUE_GET_EVENT_ENABLE_MASK (0x80000000UL)
193 #define SMU_COMPLETION_QUEUE_GET_RESERVED_MASK (0x38004000UL)
212 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_SHIFT (0UL)
213 #define SMU_COMPLETION_QUEUE_CONTROL_QUEUE_LIMIT_MASK (0x00003FFFUL)
215 #define SMU_COMPLETION_QUEUE_CONTROL_EVENT_LIMIT_MASK (0x03FF0000UL)
216 #define SMU_COMPLETION_QUEUE_CONTROL_RESERVED_MASK (0xFC00C000UL)
229 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT (0UL)
230 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK (0x00000FFFUL)
232 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK (0x00007000UL)
234 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK (0x07FF8000UL)
236 #define SMU_DEVICE_CONTEXT_CAPACITY_MAX_PEG_MASK (0x08000000UL)
237 #define SMU_DEVICE_CONTEXT_CAPACITY_RESERVED_MASK (0xF0000000UL)
267 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_SHIFT (0UL)
268 #define SMU_CLOCK_GATING_CONTROL_IDLE_ENABLE_MASK (0x00000001UL)
270 #define SMU_CLOCK_GATING_CONTROL_XCLK_ENABLE_MASK (0x00000002UL)
272 #define SMU_CLOCK_GATING_CONTROL_TXCLK_ENABLE_MASK (0x00000004UL)
274 #define SMU_CLOCK_GATING_CONTROL_REGCLK_ENABLE_MASK (0x00000008UL)
276 #define SMU_CLOCK_GATING_CONTROL_IDLE_TIMEOUT_MASK (0x000F0000UL)
278 #define SMU_CLOCK_GATING_CONTROL_FORCE_IDLE_MASK (0x80000000UL)
279 #define SMU_CLOCK_GATING_CONTROL_RESERVED_MASK (0x7FF0FFF0UL)
289 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_SHIFT (0UL)
290 #define SMU_CONTROL_STATUS_TASK_CONTEXT_RANGE_ENABLE_MASK (0x00000001UL)
292 #define SMU_CONTROL_STATUS_COMPLETION_BYTE_SWAP_ENABLE_MASK (0x00000002UL)
294 #define SMU_CONTROL_STATUS_CONTEXT_RAM_INIT_COMPLETED_MASK (0x00010000UL)
296 #define SMU_CONTROL_STATUS_SCHEDULER_RAM_INIT_COMPLETED_MASK (0x00020000UL)
297 #define SMU_CONTROL_STATUS_RESERVED_MASK (0xFFFCFFFCUL)
316 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_SHIFT (0UL)
317 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE0_MASK (0x00000001UL)
319 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE1_MASK (0x00000002UL)
321 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE2_MASK (0x00000004UL)
323 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_PE3_MASK (0x00000008UL)
325 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE0_MASK (0x00000100UL)
327 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE1_MASK (0x00000200UL)
329 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE2_MASK (0x00000400UL)
331 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_PE3_MASK (0x00000800UL)
338 SMU_RESET_PROTOCOL_ENGINE(peg, 0) \
346 SMU_RESET_PEG_PROTOCOL_ENGINES(0) \
351 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP0_MASK (0x00010000UL)
353 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG0_LP2_MASK (0x00020000UL)
355 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP0_MASK (0x00040000UL)
357 #define SMU_SOFTRESET_CONTROL_RESET_WIDE_PORT_PEG1_LP2_MASK (0x00080000UL)
363 #define SMU_SOFTRESET_CONTROL_RESET_PEG0_MASK (0x00100000UL)
365 #define SMU_SOFTRESET_CONTROL_RESET_PEG1_MASK (0x00200000UL)
367 #define SMU_SOFTRESET_CONTROL_RESET_SCU_MASK (0x00400000UL)
374 | SMU_RESET_WIDE_PORT_QUEUE(peg, 0) \
381 SMU_RESET_PROTOCOL_ENGINE_GROUP(0) \
385 #define SMU_RESET_SCU() (0xFFFFFFFF)
390 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_SHIFT (0UL)
391 #define SMU_TASK_CONTEXT_ASSIGNMENT_STARTING_MASK (0x00000FFFUL)
393 #define SMU_TASK_CONTEXT_ASSIGNMENT_ENDING_MASK (0x0FFF0000UL)
395 #define SMU_TASK_CONTEXT_ASSIGNMENT_RANGE_CHECK_ENABLE_MASK (0x80000000UL)
396 #define SMU_TASK_CONTEXT_ASSIGNMENT_RESERVED_MASK (0x7000F000UL)
405 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_SHIFT (0UL)
406 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_QUEUE_SIZE_MASK (0x00000FFFUL)
407 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_CONTROL_RESERVED_MASK (0xFFFFF000UL)
416 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_SHIFT (0UL)
417 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_POINTER_MASK (0x00000FFFUL)
419 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_CYCLE_BIT_MASK (0x00001000UL)
420 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_PUT_RESERVED_MASK (0xFFFFE000UL)
431 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_SHIFT (0UL)
432 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_POINTER_MASK (0x00000FFFUL)
436 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_ENABLE_BIT_MASK (0x80000000UL)
437 #define SCU_SDMA_UNSOLICITED_FRAME_QUEUE_GET_RESERVED_MASK (0x7FFFE000UL)
461 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SHIFT (0UL)
462 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_MASK (0x0000FFFFUL)
464 #define SCU_PDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00010000UL)
466 #define SCU_PDMA_CONFIGURATION_PCI_NO_SNOOP_ENABLE_MASK (0x00020000UL)
468 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_BYTE_SWAP_MASK (0x00040000UL)
470 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_SGL_FETCH_MASK (0x00080000UL)
472 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_RX_HEADER_RAM_WRITE_MASK (0x00100000UL)
474 #define SCU_PDMA_CONFIGURATION_BIG_ENDIAN_CONTROL_XPI_UF_ADDRESS_FETCH_MASK (0x00200000UL)
476 #define SCU_PDMA_CONFIGURATION_ADDRESS_MODIFIER_SELECT_MASK (0x00400000UL)
477 #define SCU_PDMA_CONFIGURATION_RESERVED_MASK (0xFF800000UL)
490 #define SCU_CDMA_CONFIGURATION_PCI_RELAXED_ORDERING_ENABLE_MASK (0x00000100UL)
498 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_SHIFT (0UL)
499 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_TIMEOUT_MASK (0x000000FFUL)
501 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_LOCK_TIME_MASK (0x0000FF00UL)
503 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_RATE_CHANGE_DELAY_MASK (0x00FF0000UL)
505 #define SCU_LINK_LAYER_SPEED_NEGOTIATION_TIMER_VALUES_DWORD_SYNC_TIMEOUT_MASK (0xFF000000UL)
506 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_REQUIRED_MASK (0x00000000UL)
507 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_DEFAULT_MASK (0x7D00676FUL)
508 #define SCU_LINK_LAYER_SPEED_NECGOIATION_TIMER_VALUES_RESERVED_MASK (0x00FF0000UL)
515 #define SCU_LINK_STATUS_DWORD_SYNC_AQUIRED_MASK (0x00000004UL)
517 #define SCU_LINK_STATUS_TRANSMIT_PORT_SELECTION_DONE_MASK (0x00000010UL)
519 #define SCU_LINK_STATUS_RECEIVER_CREDIT_EXHAUSTED_MASK (0x00000020UL)
520 #define SCU_LINK_STATUS_RESERVED_MASK (0xFFFFFFCDUL)
531 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_SHIFT (0UL)
532 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_VALUE_MASK (0x00007FFFUL)
534 #define SCU_SAS_MAX_ARBITRATION_WAIT_TIME_TIMEOUT_SCALE_MASK (0x00008000UL)
547 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_TARGET_MASK (0x00000002UL)
549 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_TARGET_MASK (0x00000004UL)
551 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_TARGET_MASK (0x00000008UL)
553 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DA_SATA_HOST_MASK (0x00000100UL)
555 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SMP_INITIATOR_MASK (0x00000200UL)
557 #define SCU_SAS_TRANSMIT_IDENTIFICATION_STP_INITIATOR_MASK (0x00000400UL)
559 #define SCU_SAS_TRANSMIT_IDENTIFICATION_SSP_INITIATOR_MASK (0x00000800UL)
561 #define SCU_SAS_TRANSMIT_IDENTIFICATION_REASON_CODE_MASK (0x000F0000UL)
563 #define SCU_SAS_TRANSMIT_IDENTIFICATION_ADDRESS_FRAME_TYPE_MASK (0x0F000000UL)
565 #define SCU_SAS_TRANSMIT_IDENTIFICATION_DEVICE_TYPE_MASK (0x70000000UL)
566 #define SCU_SAS_TRANSMIT_IDENTIFICATION_RESERVED_MASK (0x80F0F1F1UL)
576 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_BREAK_REPLY_CAPABLE_MASK (0x00010000UL)
578 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_REQUESTED_INSIDE_ZPSDS_MASK (0x00020000UL)
580 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_INSIDE_ZPSDS_PERSISTENT_MASK (0x00040000UL)
582 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_ID_MASK (0xFF000000UL)
583 #define SCU_LINK_LAYER_IDENTIFY_FRAME_PHY_IDENTIFIER_RESERVED_MASK (0x00F800FFUL)
593 #define SCU_SAS_PHY_CONFIGURATION_TX_PARITY_CHECK_MASK (0x00000010UL)
595 #define SCU_SAS_PHY_CONFIGURATION_TX_BAD_CRC_MASK (0x00000040UL)
597 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_SCRAMBLER_MASK (0x00000080UL)
599 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_DESCRAMBLER_MASK (0x00000100UL)
601 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_CREDIT_INSERTION_MASK (0x00000200UL)
603 #define SCU_SAS_PHY_CONFIGURATION_SUSPEND_PROTOCOL_ENGINE_MASK (0x00000800UL)
605 #define SCU_SAS_PHY_CONFIGURATION_SATA_SPINUP_HOLD_MASK (0x00001000UL)
607 #define SCU_SAS_PHY_CONFIGURATION_TRANSMIT_PORT_SELECTION_SIGNAL_MASK (0x00002000UL)
609 #define SCU_SAS_PHY_CONFIGURATION_HARD_RESET_MASK (0x00004000UL)
611 #define SCU_SAS_PHY_CONFIGURATION_OOB_ENABLE_MASK (0x00008000UL)
613 #define SCU_SAS_PHY_CONFIGURATION_ENABLE_FRAME_TX_INSERT_ALIGN_MASK (0x00800000UL)
615 #define SCU_SAS_PHY_CONFIGURATION_FORWARD_IDENTIFY_FRAME_MASK (0x08000000UL)
617 #define SCU_SAS_PHY_CONFIGURATION_DISABLE_BYTE_TRANSPOSE_STP_FRAME_MASK (0x10000000UL)
619 #define SCU_SAS_PHY_CONFIGURATION_OOB_RESET_MASK (0x20000000UL)
621 #define SCU_SAS_PHY_CONFIGURATION_THREE_IAF_ENABLE_MASK (0x40000000UL)
623 #define SCU_SAS_PHY_CONFIGURATION_OOB_ALIGN0_ENABLE_MASK (0x80000000UL)
624 #define SCU_SAS_PHY_CONFIGURATION_REQUIRED_MASK (0x0100000FUL)
625 #define SCU_SAS_PHY_CONFIGURATION_DEFAULT_MASK (0x4180100FUL)
626 #define SCU_SAS_PHY_CONFIGURATION_RESERVED_MASK (0x00000000UL)
631 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_SHIFT (0UL)
632 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_GENERAL_MASK (0x000007FFUL)
634 #define SCU_LINK_LAYER_ALIGN_INSERTION_FREQUENCY_CONNECTED_MASK (0x00ff0000UL)
639 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_SHIFT (0UL)
640 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_COUNT_MASK (0x0003FFFFUL)
642 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_ENABLE_MASK (0x80000000UL)
643 #define SCU_LINK_LAYER_ENABLE_SPINUP_CONTROL_RESERVED_MASK (0x7FFC0000UL)
653 #define SCU_LINK_LAYER_PHY_CAPABILITIES_TXSSCTYPE_MASK (0x00000002UL)
655 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RLLRATE_MASK (0x000000F0UL)
657 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO15GBPS_MASK (0x00000100UL)
659 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW15GBPS_MASK (0x00000201UL)
661 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO30GBPS_MASK (0x00000401UL)
663 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW30GBPS_MASK (0x00000801UL)
665 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SWO60GBPS_MASK (0x00001001UL)
667 #define SCU_LINK_LAYER_PHY_CAPABILITIES_SW60GBPS_MASK (0x00002001UL)
669 #define SCU_LINK_LAYER_PHY_CAPABILITIES_EVEN_PARITY_MASK (0x80000000UL)
670 #define SCU_LINK_LAYER_PHY_CAPABILITIES_DEFAULT_MASK (0x00003F01UL)
671 #define SCU_LINK_LAYER_PHY_CAPABILITIES_REQUIRED_MASK (0x00000001UL)
672 #define SCU_LINK_LAYER_PHY_CAPABILITIES_RESERVED_MASK (0x7FFFC00DUL)
681 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_SHIFT (0UL)
682 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_VIRTUAL_EXPANDER_PHY_ZONE_GROUP_MASK (0x0000…
684 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_INSIDE_SOURCE_ZONE_GROUP_MASK (0x8000…
685 #define SCU_LINK_LAYER_PHY_SOURCE_ZONE_GROUP_CONTROL_RESERVED_MASK (0x7FFF…
694 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_LOCKED_MASK (0x0000…
696 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE0_UPDATING_MASK (0x0000…
698 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_LOCKED_MASK (0x0000…
700 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZONE1_UPDATING_MASK (0x0000…
702 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE0_MASK (0x0003…
704 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE0_MASK (0x0008…
706 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE1_MASK (0x0030…
708 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE1_MASK (0x0080…
710 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE2_MASK (0x0300…
712 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE2_MASK (0x0800…
714 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_ZPT_ASSOCIATION_PE3_MASK (0x3000…
716 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_AIP_ENABLE_PE3_MASK (0x8000…
717 #define SCU_PROTOCOL_ENGINE_GROUP_VIRTUAL_ZONING_EXPANDER_CONTROL_RESERVED_MASK (0x4444…
729 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_SHIFT (0UL)
730 #define SCU_PTSG_CONTROL_IT_NEXUS_TIMEOUT_MASK (0x0000FFFFUL)
732 #define SCU_PTSG_CONTROL_TASK_TIMEOUT_MASK (0x00FF0000UL)
734 #define SCU_PTSG_CONTROL_PTSG_ENABLE_MASK (0x01000000UL)
736 #define SCU_PTSG_CONTROL_ETM_ENABLE_MASK (0x02000000UL)
737 #define SCU_PTSG_CONTROL_DEFAULT_MASK (0x00020002UL)
738 #define SCU_PTSG_CONTROL_REQUIRED_MASK (0x00000000UL)
739 #define SCU_PTSG_CONTROL_RESERVED_MASK (0xFC000000UL)
749 #define SCU_PTSG_REAL_TIME_CLOCK_SHIFT (0UL)
750 #define SCU_PTSG_REAL_TIME_CLOCK_MASK (0x0000FFFFUL)
751 #define SCU_PTSG_REAL_TIME_CLOCK_RESERVED_MASK (0xFFFF0000UL)
757 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_SHIFT (0UL)
758 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_PRESCALER_VALUE_MASK (0x00FFFFFFUL)
759 #define SCU_PTSG_REAL_TIME_CLOCK_CONTROL_RESERVED_MASK (0xFF000000UL)
765 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_SHIFT (0UL)
766 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_SUSPEND_MASK (0x00000001UL)
768 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_ENABLE_MASK (0x00000002UL)
769 #define SCU_PTSG_PORT_TASK_SCHEDULER_CONTROL_RESERVED_MASK (0xFFFFFFFCUL)
775 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_SHIFT (0UL)
776 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_NEXT_RN_VALID_MASK (0x00000001UL)
778 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_ACTIVE_RNSC_LIST_VALID_MASK (0x00000002UL)
780 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_PTS_SUSPENDED_MASK (0x00000004UL)
781 #define SCU_PTSG_PORT_TASK_SCHEDULER_STATUS_RESERVED_MASK (0xFFFFFFF8UL)
790 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_SHIFT (0UL)
791 #define SCU_SGPIO_CONTROL_SGPIO_ENABLE_MASK (0x00000001UL)
793 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_CLOCK_SELECT_MASK (0x00000002UL)
795 #define SCU_SGPIO_CONTROL_SGPIO_SERIAL_SHIFT_WIDTH_SELECT_MASK (0x00000004UL)
797 #define SCU_SGPIO_CONTROL_SGPIO_TEST_BIT_MASK (0x00008000UL)
798 #define SCU_SGPIO_CONTROL_SGPIO_RESERVED_MASK (0xFFFF7FF8UL)
803 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_SHIFT (0UL)
804 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R0_MASK (0x0000000FUL)
806 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R1_MASK (0x000000F0UL)
808 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R2_MASK (0x00000F00UL)
810 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_R3_MASK (0x0000F000UL)
811 #define SCU_SGPIO_PROGRAMMABLE_BLINK_REGISTER_RESERVED_MASK (0xFFFF0000UL)
816 #define SCU_SGPIO_START_DRIVE_LOWER_R0_SHIFT (0UL)
817 #define SCU_SGPIO_START_DRIVE_LOWER_R0_MASK (0x00000003UL)
819 #define SCU_SGPIO_START_DRIVE_LOWER_R1_MASK (0x00000030UL)
821 #define SCU_SGPIO_START_DRIVE_LOWER_R2_MASK (0x00000300UL)
823 #define SCU_SGPIO_START_DRIVE_LOWER_R3_MASK (0x00003000UL)
824 #define SCU_SGPIO_START_DRIVE_LOWER_RESERVED_MASK (0xFFFF8888UL)
829 #define SCU_SGPIO_START_DRIVE_UPPER_R0_SHIFT (0UL)
830 #define SCU_SGPIO_START_DRIVE_UPPER_R0_MASK (0x00000003UL)
832 #define SCU_SGPIO_START_DRIVE_UPPER_R1_MASK (0x00000030UL)
834 #define SCU_SGPIO_START_DRIVE_UPPER_R2_MASK (0x00000300UL)
836 #define SCU_SGPIO_START_DRIVE_UPPER_R3_MASK (0x00003000UL)
837 #define SCU_SGPIO_START_DRIVE_UPPER_RESERVED_MASK (0xFFFF8888UL)
842 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_SHIFT (0UL)
843 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D0_MASK (0x00000003UL)
845 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D1_MASK (0x00000030UL)
847 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D2_MASK (0x00000300UL)
849 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_D3_MASK (0x00003000UL)
850 #define SCU_SGPIO_SERIAL_INPUT_DATA_LOWER_RESERVED_MASK (0xFFFF8888UL)
855 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_SHIFT (0UL)
856 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D0_MASK (0x00000003UL)
858 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D1_MASK (0x00000030UL)
860 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D2_MASK (0x00000300UL)
862 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_D3_MASK (0x00003000UL)
863 #define SCU_SGPIO_SERIAL_INPUT_DATA_UPPER_RESERVED_MASK (0xFFFF8888UL)
868 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_SHIFT (0UL)
869 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_MASK (0x0000000FUL)
870 #define SCU_SGPIO_VENDOR_SPECIFIC_CODE_RESERVED_MASK (0xFFFFFFF0UL)
875 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_SHIFT (0UL)
876 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA0_MASK (0x00000003UL)
878 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA0_MASK (0x00000004UL)
880 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA0_MASK (0x00000008UL)
882 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA1_MASK (0x00000030UL)
884 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA1_MASK (0x00000040UL)
886 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA1_MASK (0x00000080UL)
888 #define SCU_SGPIO_OUPUT_DATA_SELECT_INPUT_DATA2_MASK (0x00000300UL)
890 #define SCU_SGPIO_OUPUT_DATA_SELECT_INVERT_INPUT_DATA2_MASK (0x00000400UL)
892 #define SCU_SGPIO_OUPUT_DATA_SELECT_JOG_ENABLE_DATA2_MASK (0x00000800UL)
893 #define SCU_SGPIO_OUPUT_DATA_SELECT_RESERVED_MASK (0xFFFFF000UL)
916 // The TCA is only accessible from FN#0 (Physical Function) and each
917 // is programmed by (BAR0 + SCU_SMU_TCA_OFFSET + (FN# * 0x04)) or
918 // TCA0 for FN#0 is at BAR0 + 0x0400
919 // TCA1 for FN#1 is at BAR0 + 0x0404
923 #define SCU_SMU_PCP_OFFSET 0x0000
924 #define SCU_SMU_AMR_OFFSET 0x0004
925 #define SCU_SMU_ISR_OFFSET 0x0010
926 #define SCU_SMU_IMR_OFFSET 0x0014
927 #define SCU_SMU_ICC_OFFSET 0x0018
928 #define SCU_SMU_HTTLBAR_OFFSET 0x0020
929 #define SCU_SMU_HTTUBAR_OFFSET 0x0024
930 #define SCU_SMU_TCR_OFFSET 0x0028
931 #define SCU_SMU_CQLBAR_OFFSET 0x0030
932 #define SCU_SMU_CQUBAR_OFFSET 0x0034
933 #define SCU_SMU_CQPR_OFFSET 0x0040
934 #define SCU_SMU_CQGR_OFFSET 0x0044
935 #define SCU_SMU_CQC_OFFSET 0x0048
936 // Accessible to FN#0 only
937 #define SCU_SMU_RNCLBAR_OFFSET 0x0080
938 #define SCU_SMU_RNCUBAR_OFFSET 0x0084
939 #define SCU_SMU_DCC_OFFSET 0x0090
940 #define SCU_SMU_DFC_OFFSET 0x0094
941 #define SCU_SMU_SMUCSR_OFFSET 0x0098
942 #define SCU_SMU_SCUSRCR_OFFSET 0x009C
943 #define SCU_SMU_SMAW_OFFSET 0x00A0
944 #define SCU_SMU_SMDW_OFFSET 0x00A4
945 // Accessible to FN#0 only
946 #define SCU_SMU_TCA_OFFSET 0x0400
948 #define SCU_SMU_MT_MLAR0_OFFSET 0x2000
949 #define SCU_SMU_MT_MUAR0_OFFSET 0x2004
950 #define SCU_SMU_MT_MDR0_OFFSET 0x2008
951 #define SCU_SMU_MT_VCR0_OFFSET 0x200C
952 #define SCU_SMU_MT_MLAR1_OFFSET 0x2010
953 #define SCU_SMU_MT_MUAR1_OFFSET 0x2014
954 #define SCU_SMU_MT_MDR1_OFFSET 0x2018
955 #define SCU_SMU_MT_VCR1_OFFSET 0x201C
956 #define SCU_SMU_MPBA_OFFSET 0x3000
966 // 0x0000 PCP
968 // 0x0004 AMR
972 // 0x0010 ISR
974 // 0x0014 IMR
976 // 0x0018 ICC
979 // 0x0020 HTTLBAR
981 // 0x0024 HTTUBAR
983 // 0x0028 TCR
986 // 0x0030 CQLBAR
988 // 0x0034 CQUBAR
992 // 0x0040 CQPR
994 // 0x0044 CQGR
996 // 0x0048 CQC
1002 // Accessible to FN#0 only
1003 // 0x0080 RNCLBAR
1005 // 0x0084 RNCUBAR
1009 // 0x0090 DCC
1011 // 0x0094 DFC
1013 // 0x0098 SMUCSR
1015 // 0x009C SCUSRCR
1017 // 0x00A0 SMAW
1019 // 0x00A4 SMDW
1021 // 0x00A8 CGUCR
1023 // 0x00AC CGUPC
1034 // Accessible to FN#0 only
1035 // 0x0400 TCA
1043 #define SCU_SDMA_BASE 0x6000
1044 #define SCU_SDMA_PUFATLHAR_OFFSET 0x0000
1045 #define SCU_SDMA_PUFATUHAR_OFFSET 0x0004
1046 #define SCU_SDMA_UFLHBAR_OFFSET 0x0008
1047 #define SCU_SDMA_UFUHBAR_OFFSET 0x000C
1048 #define SCU_SDMA_UFQC_OFFSET 0x0010
1049 #define SCU_SDMA_UFQPP_OFFSET 0x0014
1050 #define SCU_SDMA_UFQGP_OFFSET 0x0018
1051 #define SCU_SDMA_PDMACR_OFFSET 0x001C
1052 #define SCU_SDMA_CDMACR_OFFSET 0x0080
1062 // 0x0000 PUFATLHAR
1064 // 0x0004 PUFATUHAR
1066 // 0x0008 UFLHBAR
1068 // 0x000C UFUHBAR
1070 // 0x0010 UFQC
1072 // 0x0014 UFQPP
1074 // 0x0018 UFQGP
1076 // 0x001C PDMACR
1078 // Reserved until offset 0x80
1079 U32 reserved_0020_007C[0x18];
1080 // 0x0080 CDMACR
1083 U32 reserved_0084_0400[0xDF];
1090 #define SCU_PEG0_OFFSET 0x0000
1091 #define SCU_PEG1_OFFSET 0x8000
1093 #define SCU_TL0_OFFSET 0x0000
1094 #define SCU_TL1_OFFSET 0x0400
1095 #define SCU_TL2_OFFSET 0x0800
1096 #define SCU_TL3_OFFSET 0x0C00
1098 #define SCU_LL_OFFSET 0x0080
1105 #define SCU_TLCR_OFFSET 0x0000
1106 #define SCU_TLADTR_OFFSET 0x0004
1107 #define SCU_TLTTMR_OFFSET 0x0008
1108 #define SCU_TLEECR0_OFFSET 0x000C
1109 #define SCU_STPTLDARNI_OFFSET 0x0010
1112 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_SHIFT (0UL)
1113 #define SCU_TLCR_HASH_SAS_CHECKING_ENABLE_MASK (0x00000001UL)
1115 #define SCU_TLCR_CLEAR_TCI_NCQ_MAPPING_TABLE_MASK (0x00000002UL)
1117 #define SCU_TLCR_STP_WRITE_DATA_PREFETCH_MASK (0x00000008UL)
1119 #define SCU_TLCR_CMD_NAK_STATUS_CODE_MASK (0x00000010UL)
1120 #define SCU_TLCR_RESERVED_MASK (0xFFFFFFEBUL)
1133 // 0x0000 TLCR
1135 // 0x0004 TLADTR
1137 // 0x0008 TLTTMR
1139 // 0x000C reserved
1141 // 0x0010 STPTLDARNI
1143 // 0x0014 TLFEWPORCTRL
1145 // 0x0018 TLFEWPORDATA
1147 // 0x001C RXTLSSCSR1
1149 // 0x0020 RXTLSSCSR2
1151 // 0x0024 AWTRDDCR
1154 U32 reserved_0028_007F[0x16];
1159 #define SCU_SCUVZECRx_OFFSET 0x1080
1162 #define SCU_SAS_SPDTOV_OFFSET 0x0000
1163 #define SCU_SAS_LLSTA_OFFSET 0x0004
1164 #define SCU_SATA_PSELTOV_OFFSET 0x0008
1165 #define SCU_SAS_TIMETOV_OFFSET 0x0010
1166 #define SCU_SAS_LOSTOT_OFFSET 0x0014
1167 #define SCU_SAS_LNKTOV_OFFSET 0x0018
1168 #define SCU_SAS_PHYTOV_OFFSET 0x001C
1169 #define SCU_SAS_AFERCNT_OFFSET 0x0020
1170 #define SCU_SAS_WERCNT_OFFSET 0x0024
1171 #define SCU_SAS_TIID_OFFSET 0x0028
1172 #define SCU_SAS_TIDNH_OFFSET 0x002C
1173 #define SCU_SAS_TIDNL_OFFSET 0x0030
1174 #define SCU_SAS_TISSAH_OFFSET 0x0034
1175 #define SCU_SAS_TISSAL_OFFSET 0x0038
1176 #define SCU_SAS_TIPID_OFFSET 0x003C
1177 #define SCU_SAS_TIRES2_OFFSET 0x0040
1178 #define SCU_SAS_ADRSTA_OFFSET 0x0044
1179 #define SCU_SAS_MAWTTOV_OFFSET 0x0048
1180 #define SCU_SAS_ECENCR_OFFSET 0x0050
1181 #define SCU_SAS_FRPLDFIL_OFFSET 0x0054
1182 #define SCU_SAS_RFCNT_OFFSET 0x0060
1183 #define SCU_SAS_TFCNT_OFFSET 0x0064
1184 #define SCU_SAS_RFDCNT_OFFSET 0x0068
1185 #define SCU_SAS_TFDCNT_OFFSET 0x006C
1186 #define SCU_SAS_LERCNT_OFFSET 0x0070
1187 #define SCU_SAS_RDISERRCNT_OFFSET 0x0074
1188 #define SCU_SAS_CRERCNT_OFFSET 0x0078
1189 #define SCU_STPCTL_OFFSET 0x007C
1190 #define SCU_SAS_PCFG_OFFSET 0x0080
1191 #define SCU_SAS_CLKSM_OFFSET 0x0084
1192 #define SCU_SAS_TXCOMWAKE_OFFSET 0x0088
1193 #define SCU_SAS_TXCOMINIT_OFFSET 0x008C
1194 #define SCU_SAS_TXCOMSAS_OFFSET 0x0090
1195 #define SCU_SAS_COMINIT_OFFSET 0x0094
1196 #define SCU_SAS_COMWAKE_OFFSET 0x0098
1197 #define SCU_SAS_COMSAS_OFFSET 0x009C
1198 #define SCU_SAS_SFERCNT_OFFSET 0x00A0
1199 #define SCU_SAS_CDFERCNT_OFFSET 0x00A4
1200 #define SCU_SAS_DNFERCNT_OFFSET 0x00A8
1201 #define SCU_SAS_PRSTERCNT_OFFSET 0x00AC
1202 #define SCU_SAS_CNTCTL_OFFSET 0x00B0
1203 #define SCU_SAS_SSPTOV_OFFSET 0x00B4
1204 #define SCU_FTCTL_OFFSET 0x00B8
1205 #define SCU_FRCTL_OFFSET 0x00BC
1206 #define SCU_FTWMRK_OFFSET 0x00C0
1207 #define SCU_ENSPINUP_OFFSET 0x00C4
1208 #define SCU_SAS_TRNTOV_OFFSET 0x00C8
1209 #define SCU_SAS_PHYCAP_OFFSET 0x00CC
1210 #define SCU_SAS_PHYCTL_OFFSET 0x00D0
1211 #define SCU_SAS_LLCTL_OFFSET 0x00D8
1212 #define SCU_AFE_XCVRCR_OFFSET 0x00DC
1213 #define SCU_AFE_LUTCR_OFFSET 0x00E0
1215 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_SHIFT (0UL)
1216 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_ALIGN_DETECTION_MASK (0x000000FFUL)
1218 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_HOT_PLUG_MASK (0x0000FF00UL)
1220 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_COMSAS_DETECTION_MASK (0x00FF0000UL)
1222 #define SCU_SAS_PHY_TIMER_TIMEOUT_VALUES_RATE_CHANGE_MASK (0xFF000000UL)
1227 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_SHIFT (0UL)
1228 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_MASK (0x00000003UL)
1229 #define SCU_SAS_LINK_LAYER_CONTROL_MAX_LINK_RATE_GEN1 (0UL)
1233 #define SCU_SAS_LINK_LAYER_CONTROL_BROADCAST_PRIMITIVE_MASK (0x000003FCUL)
1235 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_ACTIVE_TASK_DISABLE_MASK (0x00010000UL)
1237 #define SCU_SAS_LINK_LAYER_CONTROL_CLOSE_NO_OUTBOUND_TASK_DISABLE_MASK (0x00020000UL)
1239 #define SCU_SAS_LINK_LAYER_CONTROL_NO_OUTBOUND_TASK_TIMEOUT_MASK (0xFF000000UL)
1240 #define SCU_SAS_LINK_LAYER_CONTROL_RESERVED (0x00FCFC00UL)
1248 //#define SCU_FRXHECR_DCNT_OFFSET 0x00B0
1249 #define SCU_PSZGCR_OFFSET 0x00E4
1250 #define SCU_SAS_RECPHYCAP_OFFSET 0x00E8
1251 //#define SCU_TX_LUTSEL_OFFSET 0x00B8
1253 #define SCU_SAS_PTxC_OFFSET 0x00D4 // Same offset as SAS_TCTSTM
1256 #define SCU_SAS_LLSTA_DWORD_SYNCA_BIT 0x4
1266 // 0x0000 SAS_SPDTOV
1268 // 0x0004 SAS_LLSTA
1270 // 0x0008 SATA_PSELTOV
1273 // 0x0010 SAS_TIMETOV
1275 // 0x0014 SAS_RCDTOV
1277 // 0x0018 SAS_LNKTOV
1279 // 0x001C SAS_PHYTOV
1281 // 0x0020 SAS_AFERCNT
1283 // 0x0024 SAS_WERCNT
1285 // 0x0028 SAS_TIID
1287 // 0x002C SAS_TIDNH
1289 // 0x0030 SAS_TIDNL
1291 // 0x0034 SAS_TISSAH
1293 // 0x0038 SAS_TISSAL
1295 // 0x003C SAS_TIPID
1297 // 0x0040 SAS_TIRES2
1299 // 0x0044 SAS_ADRSTA
1301 // 0x0048 SAS_MAWTTOV
1303 // 0x004C SAS_PTxC
1305 // 0x0050 SAS_ECENCR
1307 // 0x0054 SAS_FRPLDFIL
1309 // 0x0058 SAS_LLHANG_TOT
1312 // 0x0060 SAS_RFCNT
1314 // 0x0064 SAS_TFCNT
1316 // 0x0068 SAS_RFDCNT
1318 // 0x006C SAS_TFDCNT
1320 // 0x0070 SAS_LERCNT
1322 // 0x0074 SAS_RDISERRCNT
1324 // 0x0078 SAS_CRERCNT
1326 // 0x007C STPCTL
1328 // 0x0080 SAS_PCFG
1330 // 0x0084 SAS_CLKSM
1332 // 0x0088 SAS_TXCOMWAKE
1334 // 0x008C SAS_TXCOMINIT
1336 // 0x0090 SAS_TXCOMSAS
1338 // 0x0094 SAS_COMINIT
1340 // 0x0098 SAS_COMWAKE
1342 // 0x009C SAS_COMSAS
1344 // 0x00A0 SAS_SFERCNT
1346 // 0x00A4 SAS_CDFERCNT
1348 // 0x00A8 SAS_DNFERCNT
1350 // 0x00AC SAS_PRSTERCNT
1352 // 0x00B0 SAS_CNTCTL
1354 // 0x00B4 SAS_SSPTOV
1356 // 0x00B8 FTCTL
1358 // 0x00BC FRCTL
1360 // 0x00C0 FTWMRK
1362 // 0x00C4 ENSPINUP
1364 // 0x00C8 SAS_TRNTOV
1366 // 0x00CC SAS_PHYCAP
1368 // 0x00D0 SAS_PHYCTL
1371 // 0x00D8 LLCTL
1373 // 0x00DC AFE_XCVRCR
1375 // 0x00E0 AFE_LUTCR
1377 // 0x00E4 PSZGCR
1379 // 0x00E8 SAS_RECPHYCAP
1382 // 0x00F0 SNAFERXRSTCTL
1384 // 0x00F4 SAS_SSIPMCTL
1386 // 0x00F8 SAS_PSPREQ_PRIM
1388 // 0x00FC SAS_PSSREQ_PRIM
1390 // 0x0100 SAS_PPSACK_PRIM
1392 // 0x0104 SAS_PSNAK_PRIM
1394 // 0x0108 SAS_SSIPMTOV
1397 // 0x0110 - 0x011C PLAPRDCTRLxREG
1399 // 0x0120 PLAPRDSUMREG
1401 // 0x0124 PLACONTROLREG
1404 U32 reserved_0128_037f[0x96];
1408 // 0x00D4 // Same offset as SAS_TCTSTM SAS_PTxC
1414 #define SCU_SGPIO_OFFSET 0x1400
1416 //#define SCU_SGPIO_OFFSET 0x6000 // later moves to 0x1400 see HSD 652625
1417 #define SCU_SGPIO_SGICR_OFFSET 0x0000
1418 #define SCU_SGPIO_SGPBR_OFFSET 0x0004
1419 #define SCU_SGPIO_SGSDLR_OFFSET 0x0008
1420 #define SCU_SGPIO_SGSDUR_OFFSET 0x000C
1421 #define SCU_SGPIO_SGSIDLR_OFFSET 0x0010
1422 #define SCU_SGPIO_SGSIDUR_OFFSET 0x0014
1423 #define SCU_SGPIO_SGVSCR_OFFSET 0x0018
1424 // Address from 0x0820 to 0x083C
1425 #define SCU_SGPIO_SGODSR_OFFSET 0x0020
1435 // 0x0000 SGPIO_SGICR
1437 // 0x0004 SGPIO_SGPBR
1439 // 0x0008 SGPIO_SGSDLR
1441 // 0x000C SGPIO_SGSDUR
1443 // 0x0010 SGPIO_SGSIDLR
1445 // 0x0014 SGPIO_SGSIDUR
1447 // 0x0018 SGPIO_SGVSCR
1449 // 0x001C Reserved
1451 // 0x0020 SGPIO_SGODSR
1454 U32 reserved_1444_14ff[0x30];
1460 //* Access additional entries by SCU_VIIT_BASE + index * 0x10
1462 #define SCU_VIIT_BASE 0x1c00
1473 #define SCU_PTSG_BASE 0x1000
1475 #define SCU_PTSG_PTSGCR_OFFSET 0x0000
1476 #define SCU_PTSG_RTCR_OFFSET 0x0004
1477 #define SCU_PTSG_RTCCR_OFFSET 0x0008
1478 #define SCU_PTSG_PTS0CR_OFFSET 0x0010
1479 #define SCU_PTSG_PTS0SR_OFFSET 0x0014
1480 #define SCU_PTSG_PTS1CR_OFFSET 0x0018
1481 #define SCU_PTSG_PTS1SR_OFFSET 0x001C
1482 #define SCU_PTSG_PTS2CR_OFFSET 0x0020
1483 #define SCU_PTSG_PTS2SR_OFFSET 0x0024
1484 #define SCU_PTSG_PTS3CR_OFFSET 0x0028
1485 #define SCU_PTSG_PTS3SR_OFFSET 0x002C
1486 #define SCU_PTSG_PCSPE0CR_OFFSET 0x0030
1487 #define SCU_PTSG_PCSPE1CR_OFFSET 0x0034
1488 #define SCU_PTSG_PCSPE2CR_OFFSET 0x0038
1489 #define SCU_PTSG_PCSPE3CR_OFFSET 0x003C
1490 #define SCU_PTSG_ETMTSCCR_OFFSET 0x0040
1491 #define SCU_PTSG_ETMRNSCCR_OFFSET 0x0044
1515 // 0x0000 PTSGCR
1517 // 0x0004 RTCR
1519 // 0x0008 RTCCR
1521 // 0x000C
1523 // 0x0010 PTS0CR
1524 // 0x0014 PTS0SR
1525 // 0x0018 PTS1CR
1526 // 0x001C PTS1SR
1527 // 0x0020 PTS2CR
1528 // 0x0024 PTS2SR
1529 // 0x0028 PTS3CR
1530 // 0x002C PTS3SR
1532 // 0x0030 PCSPE0CR
1533 // 0x0034 PCSPE1CR
1534 // 0x0038 PCSPE2CR
1535 // 0x003C PCSPE3CR
1537 // 0x0040 ETMTSCCR
1539 // 0x0044 ETMRNSCCR
1542 U32 reserved_1048_107f[0x0E];
1546 #define SCU_PTSG_SCUVZECR_OFFSET 0x003C
1551 #define SCU_AFE_MMR_BASE 0xE000
1554 #define SCU_AFE_PLL_CTL_OFFSET 0x0000
1555 #define SCU_AFE_RXPI_CTL_OFFSET 0x0004
1556 #define SCU_AFE_MBIAS_CTL0_OFFSET 0x000C
1557 #define SCU_AFE_MBIAS_CTL1_OFFSET 0x0010
1558 #define SCU_AFE_COMM_STA_OFFSET 0x0020
1559 #define SCU_AFE_RXPI_STA_OFFSET 0x0024
1560 #define SCU_AFE_XCVR0_CTL0_OFFSET 0x0040
1561 #define SCU_AFE_XCVR1_CTL0_OFFSET 0x0044
1562 #define SCU_AFE_XCVR2_CTL0_OFFSET 0x0048
1563 #define SCU_AFE_XCVR3_CTL0_OFFSET 0x004C
1564 #define SCU_AFE_XCVR0_CTL1_OFFSET 0x0050
1565 #define SCU_AFE_XCVR1_CTL1_OFFSET 0x0054
1566 #define SCU_AFE_XCVR2_CTL1_OFFSET 0x0058
1567 #define SCU_AFE_XCVR3_CTL1_OFFSET 0x005C
1568 #define SCU_AFE_XCVR0_RXEQ_CTL_OFFSET 0x0060
1569 #define SCU_AFE_XCVR1_RXEQ_CTL_OFFSET 0x0064
1570 #define SCU_AFE_XCVR2_RXEQ_CTL_OFFSET 0x0068
1571 #define SCU_AFE_XCVR3_RXEQ_CTL_OFFSET 0x006C
1572 #define SCU_AFE_XCVR0_CDR_STA_OFFSET 0x0080
1573 #define SCU_AFE_XCVR1_CDR_STA_OFFSET 0x0084
1574 #define SCU_AFE_XCVR2_CDR_STA_OFFSET 0x0088
1575 #define SCU_AFE_XCVR3_CDR_STA_OFFSET 0x008C
1576 #define SCU_AFE_XCVR0_RXEQ_STA0_OFFSET 0x0090
1577 #define SCU_AFE_XCVR1_RXEQ_STA0_OFFSET 0x0094
1578 #define SCU_AFE_XCVR2_RXEQ_STA0_OFFSET 0x0098
1579 #define SCU_AFE_XCVR3_RXEQ_STA0_OFFSET 0x009C
1580 #define SCU_AFE_XCVR0_RXEQ_STA1_OFFSET 0x00A0
1581 #define SCU_AFE_XCVR1_RXEQ_STA1_OFFSET 0x00A4
1582 #define SCU_AFE_XCVR2_RXEQ_STA1_OFFSET 0x00A8
1583 #define SCU_AFE_XCVR3_RXEQ_STA1_OFFSET 0x00AC
1584 #define SCU_AFE_DFX_MSTR_CTL_OFFSET 0x0104
1585 #define SCU_AFE_NTL_CTL_OFFSET 0x010C
1586 #define SCU_AFE_DFX_XCVR_STA_CLR_OFFSET 0x0120
1587 #define SCU_AFE_NTL_STA_OFFSET 0x0124
1588 #define SCU_AFE_DFX_XCVR0_STA0_OFFSET 0x0130
1589 #define SCU_AFE_DFX_XCVR1_STA0_OFFSET 0x0134
1590 #define SCU_AFE_DFX_XCVR2_STA0_OFFSET 0x0138
1591 #define SCU_AFE_DFX_XCVR3_STA0_OFFSET 0x013C
1592 #define SCU_AFE_DFX_XCVR0_STA1_OFFSET 0x0140
1593 #define SCU_AFE_DFX_XCVR1_STA1_OFFSET 0x0144
1594 #define SCU_AFE_DFX_XCVR2_STA1_OFFSET 0x0148
1595 #define SCU_AFE_DFX_XCVR3_STA1_OFFSET 0x014C
1596 #define SCU_AFE_DFX_MON_CTL_OFFSET 0x0150
1598 #define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR0_OFFSET 0x0180
1599 #define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR1_OFFSET 0x0184
1600 #define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR2_OFFSET 0x0188
1601 #define SCU_AFE_DFX_RX_CTL0_AFE0_XCVR3_OFFSET 0x018C
1602 #define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR0_OFFSET 0x0980
1603 #define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR1_OFFSET 0x0984
1604 #define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR2_OFFSET 0x0988
1605 #define SCU_AFE_DFX_RX_CTL0_AFE1_XCVR3_OFFSET 0x098C
1607 #define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR0_OFFSET 0x0190
1608 #define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR1_OFFSET 0x0194
1609 #define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR2_OFFSET 0x0198
1610 #define SCU_AFE_DFX_RX_CTL1_AFE0_XCVR3_OFFSET 0x019C
1611 #define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR0_OFFSET 0x0990
1612 #define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR1_OFFSET 0x0994
1613 #define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR2_OFFSET 0x0998
1614 #define SCU_AFE_DFX_RX_CTL1_AFE1_XCVR3_OFFSET 0x099C
1616 #define SCU_AFE_PLL_DFX_CTL_OFFSET 0x01C0
1618 #define SCU_AFE_XCVR0_DFX_DATA_OFFSET 0x0200 // [0:0F]
1619 #define SCU_AFE_XCVR0_CC_OFFSET 0x0240
1620 #define SCU_AFE_XCVR0_DFX_IR_OFFSET 0x0250 // [0:1F]
1622 #define SCU_AFE_XCVR1_DFX_DATA_OFFSET 0x0300 // [0:0F]
1623 #define SCU_AFE_XCVR1_CC_OFFSET 0x0340
1624 #define SCU_AFE_XCVR1_DFX_IR_OFFSET 0x0350 // [0:1F]
1626 #define SCU_AFE_XCVR2_DFX_DATA_OFFSET 0x0400 // [0:0F]
1627 #define SCU_AFE_XCVR2_CC_OFFSET 0x0440
1628 #define SCU_AFE_XCVR2_DFX_IR_OFFSET 0x0450 // [0:1F]
1630 #define SCU_AFE_XCVR3_DFX_DATA_OFFSET 0x0500 // [0:0F]
1631 #define SCU_AFE_XCVR3_CC_OFFSET 0x0540
1632 #define SCU_AFE_XCVR3_DFX_IR_OFFSET 0x0550 // [0:1F]
1649 // 0x00
1650 U32 afe_transceiver_dfx_data[0x10];
1651 // 0x40
1653 // 0x44 - 0x4c
1655 // 0x50
1656 U32 afe_transceiver_dfx_instruction[0x20];
1657 // 0xd0 - 0xfc
1658 U32 reserved_00d0_00fc[0x0C];
1667 // AFE 0 is at offset 0x0800
1668 // AFE 1 is at offset 0x0900
1669 // AFE 2 is at offset 0x0a00
1670 // AFE 3 is at offset 0x0b00
1673 // 0x0000 AFE_XCVR_CTRL0
1675 // 0x0004 AFE_XCVR_CTRL1
1677 // 0x0008
1679 // 0x000c afe_dfx_rx_control0
1681 // 0x0010 AFE_DFX_RX_CTRL1
1683 // 0x0014
1685 // 0x0018 AFE_DFX_RX_STS0
1687 // 0x001c AFE_DFX_RX_STS1
1689 // 0x0020
1691 // 0x0024 AFE_TX_CTRL
1693 // 0x0028 AFE_TX_AMP_CTRL0
1695 // 0x002c AFE_TX_AMP_CTRL1
1697 // 0x0030 AFE_TX_AMP_CTRL2
1699 // 0x0034 AFE_TX_AMP_CTRL3
1701 // 0x0038 afe_tx_ssc_control
1703 // 0x003c
1705 // 0x0040 AFE_RX_SSC_CTRL0
1707 // 0x0044 AFE_RX_SSC_CTRL1
1709 // 0x0048 AFE_RX_SSC_CTRL2
1711 // 0x004c AFE_RX_EQ_STS0
1713 // 0x0050 AFE_RX_EQ_STS1
1715 // 0x0054 AFE_RX_CDR_STS
1717 // 0x0058
1719 // 0x005c AFE_CHAN_CTRL
1721 // 0x0060-0x006c
1722 U32 reserved_0060_006c[0x04];
1723 // 0x0070 AFE_XCVR_EC_STS0
1725 // 0x0074 AFE_XCVR_EC_STS1
1727 // 0x0078 AFE_XCVR_EC_STS2
1729 // 0x007c afe_xcvr_ec_status3
1731 // 0x0080 AFE_XCVR_EC_STS4
1733 // 0x0084 AFE_XCVR_EC_STS5
1735 // 0x0088-0x00fc
1736 U32 reserved_008c_00fc[0x1e];
1751 // 0x0000
1753 // 0x0004
1755 // 0x0008
1757 // 0x000C
1759 // 0x0014 - 0x001c
1761 // 0x0020
1763 // 0x0024
1765 // 0x0028 - 0x003C
1767 // 0x0040
1769 // 0x0050
1771 // 0x0060
1773 // 0x0070 - 0x007c
1775 // 0x0080
1777 // 0x0090
1779 // 0x00A0
1781 // 0x00B0 - 0x0100
1782 U32 reserved_00b0_0100[0x15];
1783 // 0x0104
1785 // 0x0108
1787 // 0x010c
1789 // 0x0110 - 0x011C
1791 // 0x0120
1793 // 0x0124
1795 // 0x0128 - 0x012c
1797 // 0x0130
1799 // 0x0140
1801 // 0x0150
1803 // 0x0154 - 0x017c
1804 U32 reserved_0154_017C[0x0B];
1805 // 0x0180
1807 // 0x0190
1809 // 0x1A0
1811 // 0x01B0 - 0x01BC
1813 // 0x01C0
1815 // 0x01c4 - 0x01fc
1816 U32 reserved_01c4_01fc[0x0F];
1817 // 0x0200 - 0x05fc
1820 // 0x0600 - 0x06FC
1821 U32 reserved_0600_06FC[0x40];
1823 // 0x0700
1826 U32 reserved_0800_2000[0x600];
1839 // 0Xe000 AFE_BIAS_CTRL
1842 // 0x0008 AFE_PLL_CTRL0
1844 // 0x000c AFE_PLL_CTRL1
1846 // 0x0010 AFE_PLL_CTRL2
1848 // 0x0014 AFE_CB_STS
1850 // 0x0018-0x007c
1851 U32 reserved_18_7c[0x1a];
1852 // 0x0080 AFE_PMSN_MCTRL0
1854 // 0x0084 AFE_PMSN_MCTRL1
1856 // 0x0088 AFE_PMSN_MCTRL2
1858 // 0x008C-0x00fc
1859 U32 reserved_008c_00fc[0x1D];
1860 // 0x0100 AFE_DFX_MST_CTRL0
1862 // 0x0104 AFE_DFX_MST_CTRL1
1864 // 0x0108 AFE_DFX_DCL_CTRL
1866 // 0x010c AFE_DFX_DMON_CTRL
1868 // 0x0110 AFE_DFX_AMONP_CTRL
1870 // 0x0114 AFE_DFX_AMONN_CTRL
1872 // 0x0118 AFE_DFX_NTL_STS
1874 // 0x011c AFE_DFX_FIFO_STS0
1876 // 0x0120 AFE_DFX_FIFO_STS1
1878 // 0x0124 AFE_DFX_MPAT_CTRL
1880 // 0x0128 AFE_DFX_P0_CTRL
1882 // 0x012c-0x01a8 AFE_DFX_P0_DRx
1884 // 0x01ac
1886 // 0x01b0-0x020c AFE_DFX_P0_IRx
1888 // 0x0210
1890 // 0x0214 AFE_DFX_P1_CTRL
1892 // 0x0218-0x245 AFE_DFX_P1_DRx
1894 // 0x0258-0x029c
1895 U32 reserved_0258_029c[0x12];
1896 // 0x02a0-0x02bc AFE_DFX_P1_IRx
1898 // 0x02c0-0x2fc
1899 U32 reserved_02c0_02fc[0x10];
1900 // 0x0300 AFE_DFX_TX_PMSN_CTRL
1902 // 0x0304 AFE_DFX_RX_PMSN_CTRL
1905 // 0x030c AFE_DFX_NOA_CTRL0
1907 // 0x0310 AFE_DFX_NOA_CTRL1
1909 // 0x0314 AFE_DFX_NOA_CTRL2
1911 // 0x0318 AFE_DFX_NOA_CTRL3
1913 // 0x031c AFE_DFX_NOA_CTRL4
1915 // 0x0320 AFE_DFX_NOA_CTRL5
1917 // 0x0324 AFE_DFX_NOA_CTRL6
1919 // 0x0328 AFE_DFX_NOA_CTRL7
1921 // 0x032c-0x07fc
1922 U32 reserved_032c_07fc[0x135];
1924 // 0x0800-0x0bfc
1927 // 0x0c00-0x0ffc
1928 U32 reserved_0c00_0ffc[0x0100];
1937 U32 table[0xE0];
1957 * @brief CRAM register. MMR base address for CRAMC is 0x6400
1963 U32 sram_base_address_0; //0x0000
1964 U32 sram_upper_base_address_0; //0x0004
1965 U32 sram_ecc_control_0; //0x0008
1966 U32 sram_ecc_log_0; //0x000c
1967 U32 sram_ecc_addrress_0; //0x0010
1968 U32 sram_ecc_context_address_0; //0x0014
1969 U32 sram_ecc_test_0; //0x0018
1970 U32 sram_parity_control_and_status_0; //0x001C
1971 U32 sram_parity_address_0; //0x0020
1972 U32 sram_parity_upper_address_0; //0x0024
1973 U32 sram_parity_context_0; //0x0028
1974 U32 sram_memory_controller_interrupt_status_0; //0x002C
1975 U32 sram_mcu_read_arbiter_control_0; //0x0030
1976 U32 sram_mcu_write_arbiter_control_0; //0x0034
1977 U32 smcu_error_event_counter_0_0; //0x0038
1985 * 0x6600 relative to SCUBAR.
1989 U32 sram_base_address_1; //0x0000
1990 U32 sram_upper_base_address_1; //0x0004
1991 U32 sram_ecc_control_1; //0x0008
1992 U32 sram_ecc_log_1; //0x000c
1993 U32 sram_ecc_addrress_1; //0x0010
1994 U32 sram_ecc_context_address_1; //0x0014
1995 U32 sram_ecc_test_1; //0x0018
1996 U32 sram_parity_control_and_status_1; //0x001C
1997 U32 sram_parity_address_1; //0x0020
1998 U32 sram_parity_upper_address_1; //0x0024
1999 U32 sram_parity_context_1; //0x0028
2000 U32 sram_memory_controller_interrupt_status_1; //0x002C
2001 U32 sram_mcu_read_arbiter_control_1; //0x0030
2002 U32 sram_mcu_write_arbiter_control_1; //0x0034
2003 U32 smcu_error_event_counter_0_1; //0x0038
2078 U32 reserved_01500_1BFF[0x1C0];
2096 // 0x0000 - PEG 0
2099 // 0x6000 - SDMA and Miscellaneous
2103 U32 reserved_6800_69FF[0x80];
2107 U32 reserved_6d00_7fff[0x4c0];
2109 // 0x8000 - PEG 1
2112 // 0xE000 - AFE Registers