81 #define scic_sds_controller_smu_register_write(controller, reg, value) \  argument
85       (value) \
93 #define scu_afe_register_write(controller, reg, value) \  argument
97       (value) \
117 #define scu_sgpio_peg0_register_write(controller, reg, value) \  argument
121       (value) \
129 #define scu_controller_viit_register_write(controller, index, reg, value) \  argument
133       value \
146 #define scu_controller_scratch_ram_register_write(controller, index, value) \  argument
150       value \
159 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \  argument
163       value \
182 #define SMU_PCP_WRITE(controller, value) \  argument
184        controller, post_context_port, value \
187 #define SMU_TCR_READ(controller, value) \  argument
192 #define SMU_TCR_WRITE(controller, value) \  argument
194        controller, task_context_range, value \
225 #define SMU_CQGR_WRITE(controller, value) \  argument
227        controller, completion_queue_get, value \
230 #define SMU_CQGR_READ(controller, value) \  argument
235 #define SMU_CQPR_WRITE(controller, value) \  argument
237        controller, completion_queue_put, value \
284 #define SMU_ICC_WRITE(controller, value) \  argument
286       controller, interrupt_coalesce_control, value \
289 #define SMU_CQC_WRITE(controller, value) \  argument
291        controller, completion_queue_control, value \
294 #define SMU_SMUSRCR_WRITE(controller, value) \  argument
296       controller, soft_reset_control, value \
299 #define SMU_TCA_WRITE(controller, index, value) \  argument
301        controller, task_context_assignment[index], value \
329 #define SMU_CGUCR_WRITE(controller, value) \  argument
331       controller, clock_gating_control, value \
351 #define scic_sds_controller_scu_register_write(controller, reg, value) \  argument
355       (value) \
374 #define scu_sdma_register_write(controller, reg, value) \  argument
378       (value) \
420 #define SCU_UFQC_WRITE(controller, value) \  argument
424        value \
433 #define SCU_UFQPP_WRITE(controller, value) \  argument
437       value \
440 #define SCU_UFQGP_WRITE(controller, value) \  argument
444       value \
453 #define SCU_PDMACR_WRITE(controller, value) \  argument
457       value \
466 #define SCU_CDMACR_WRITE(controller, value) \  argument
470       value \
487 #define scu_cram_register_write(controller, reg, value) \  argument
491       (value) \
505 #define scu_fbram_register_write(controller, reg, value) \  argument
509       (value) \
525 #define SCU_SECR0_WRITE(controller, value) \  argument
529       value \
539 #define SCU_SECR1_WRITE(controller, value) \  argument
543       value \
562 #define scu_ptsg_register_write(controller, reg, value) \  argument
566       (value) \
580 #define SCU_PTSGCR_WRITE(controller, value) \  argument
584        value \