75 #define scic_sds_controller_smu_register_read(controller, reg) \  argument
77       (controller), \
78       (controller)->smu_registers->reg \
81 #define scic_sds_controller_smu_register_write(controller, reg, value) \  argument
83       (controller), \
84       (controller)->smu_registers->reg, \
93 #define scu_afe_register_write(controller, reg, value) \  argument
95       (controller), \
96       (controller)->scu_registers->afe.reg, \
100 #define scu_afe_register_read(controller, reg) \  argument
102       (controller), \
103       (controller)->scu_registers->afe.reg \
111 #define scu_sgpio_peg0_register_read(controller, reg) \  argument
113       (controller), \
114       (controller)->scu_registers->peg0.sgpio.reg \
117 #define scu_sgpio_peg0_register_write(controller, reg, value) \  argument
119       (controller), \
120       (controller)->scu_registers->peg0.sgpio.reg, \
129 #define scu_controller_viit_register_write(controller, index, reg, value) \  argument
131       (controller), \
132       (controller)->scu_registers->peg0.viit[index].reg, \
146 #define scu_controller_scratch_ram_register_write(controller, index, value) \  argument
148       (controller), \
149 …  ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index], \
153 #define scu_controller_scratch_ram_register_read(controller, index) \  argument
155       (controller), \
156 …   ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt0.table[index] \
159 #define scu_controller_scratch_ram_register_write_ext(controller, index, value) \  argument
161       (controller), \
162 …  ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index], \
166 #define scu_controller_scratch_ram_register_read_ext(controller, index) \  argument
168       (controller), \
169 …   ((SCU_REGISTERS_T *)scic_cb_pci_get_bar(controller, PATSBURG_SCU_BAR))->peg0.zpt1.table[index] \
182 #define SMU_PCP_WRITE(controller, value) \  argument
184        controller, post_context_port, value \
187 #define SMU_TCR_READ(controller, value) \  argument
189        controller, task_context_range \
192 #define SMU_TCR_WRITE(controller, value) \  argument
194        controller, task_context_range, value \
197 #define SMU_HTTBAR_WRITE(controller, address) \  argument
200       controller, \
205       controller, \
211 #define SMU_CQBAR_WRITE(controller, address) \  argument
214       controller, \
219       controller, \
225 #define SMU_CQGR_WRITE(controller, value) \  argument
227        controller, completion_queue_get, value \
230 #define SMU_CQGR_READ(controller, value) \  argument
232        controller, completion_queue_get \
235 #define SMU_CQPR_WRITE(controller, value) \  argument
237        controller, completion_queue_put, value \
240 #define SMU_RNCBAR_WRITE(controller, address) \  argument
243       controller, \
248       controller, \
254 #define SMU_AMR_READ(controller) \  argument
256       controller, address_modifier \
259 #define SMU_IMR_READ(controller) \  argument
261       controller, interrupt_mask \
264 #define SMU_IMR_WRITE(controller, mask) \  argument
266       controller, interrupt_mask, mask \
269 #define SMU_ISR_READ(controller) \  argument
271       controller, interrupt_status \
274 #define SMU_ISR_WRITE(controller, status) \  argument
276       controller, interrupt_status, status \
279 #define SMU_ICC_READ(controller) \  argument
281       controller, interrupt_coalesce_control \
284 #define SMU_ICC_WRITE(controller, value) \  argument
286       controller, interrupt_coalesce_control, value \
289 #define SMU_CQC_WRITE(controller, value) \  argument
291        controller, completion_queue_control, value \
294 #define SMU_SMUSRCR_WRITE(controller, value) \  argument
296       controller, soft_reset_control, value \
299 #define SMU_TCA_WRITE(controller, index, value) \  argument
301        controller, task_context_assignment[index], value \
304 #define SMU_TCA_READ(controller, index) \  argument
306        controller, task_context_assignment[index] \
309 #define SMU_DCC_READ(controller) \  argument
311       controller, device_context_capacity \
314 #define SMU_DFC_READ(controller) \  argument
316       controller, device_function_capacity \
319 #define SMU_SMUCSR_READ(controller) \  argument
321       controller, control_status \
324 #define SMU_CGUCR_READ(controller) \  argument
326       controller, clock_gating_control \
329 #define SMU_CGUCR_WRITE(controller, value) \  argument
331       controller, clock_gating_control, value \
334 #define SMU_CQPR_READ(controller) \  argument
336        controller, completion_queue_put \
345 #define scic_sds_controller_scu_register_read(controller, reg) \  argument
347       (controller), \
348       (controller)->scu_registers->reg \
351 #define scic_sds_controller_scu_register_write(controller, reg, value) \  argument
353       (controller), \
354       (controller)->scu_registers->reg, \
368 #define scu_sdma_register_read(controller, reg) \  argument
370       (controller), \
371       (controller)->scu_registers->sdma.reg \
374 #define scu_sdma_register_write(controller, reg, value) \  argument
376       (controller), \
377       (controller)->scu_registers->sdma.reg, \
386 #define SCU_PUFATHAR_WRITE(controller, address) \  argument
389       controller, \
394       controller, \
400 #define SCU_UFHBAR_WRITE(controller, address) \  argument
403       controller, \
408       controller, \
414 #define SCU_UFQC_READ(controller) \  argument
416        controller,  \
420 #define SCU_UFQC_WRITE(controller, value) \  argument
422        controller, \
427 #define SCU_UFQPP_READ(controller) \  argument
429        controller, \
433 #define SCU_UFQPP_WRITE(controller, value) \  argument
435       controller, \
440 #define SCU_UFQGP_WRITE(controller, value) \  argument
442       controller, \
447 #define SCU_PDMACR_READ(controller) \  argument
449       controller, \
453 #define SCU_PDMACR_WRITE(controller, value) \  argument
455       controller, \
460 #define SCU_CDMACR_READ(controller) \  argument
462      controller, \
466 #define SCU_CDMACR_WRITE(controller, value) \  argument
468       controller, \
481 #define scu_cram_register_read(controller, reg) \  argument
483       (controller), \
484       (controller)->scu_registers->cram.reg \
487 #define scu_cram_register_write(controller, reg, value) \  argument
489       (controller), \
490       (controller)->scu_registers->cram.reg, \
499 #define scu_fbram_register_read(controller, reg) \  argument
501       (controller), \
502       (controller)->scu_registers->fbram.reg \
505 #define scu_fbram_register_write(controller, reg, value) \  argument
507       (controller), \
508       (controller)->scu_registers->fbram.reg, \
525 #define SCU_SECR0_WRITE(controller, value) \  argument
527       controller, \
539 #define SCU_SECR1_WRITE(controller, value) \  argument
541       controller, \
556 #define scu_ptsg_register_read(controller, reg) \  argument
558       (controller), \
559       (controller)->scu_registers->peg0.ptsg.reg \
562 #define scu_ptsg_register_write(controller, reg, value) \  argument
564       (controller), \
565       (controller)->scu_registers->peg0.ptsg.reg, \
574 #define SCU_PTSGCR_READ(controller) \  argument
576        (controller), \
580 #define SCU_PTSGCR_WRITE(controller, value) \  argument
582        (controller), \
587 #define SCU_PTSGRTC_READ(controller) \  argument
589        controller, \