Lines Matching +full:0 +full:x10000080
111 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
148 * back to 0.
161 * to 0.
222 this_controller->next_phy_to_start = 0; in scic_sds_controller_initialize_phy_startup()
247 0, in scic_sds_controller_initialize_power_control()
251 this_controller->power_control.phys_waiting = 0; in scic_sds_controller_initialize_power_control()
252 this_controller->power_control.remote_devices_granted_power = 0; in scic_sds_controller_initialize_power_control()
444 // Assign all the TCs to function 0 in scic_sds_controller_assign_task_entries()
446 task_assignment = SMU_TCA_READ(this_controller, 0); in scic_sds_controller_assign_task_entries()
451 | (SMU_TCA_GEN_VAL(STARTING, 0)) in scic_sds_controller_assign_task_entries()
456 SMU_TCA_WRITE(this_controller, 0, task_assignment); in scic_sds_controller_assign_task_entries()
473 this_controller->completion_queue_get = 0; in scic_sds_controller_initialize_completion_queue()
484 (SMU_CQGR_GEN_VAL(POINTER, 0)) in scic_sds_controller_initialize_completion_queue()
485 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) in scic_sds_controller_initialize_completion_queue()
496 (SMU_CQPR_GEN_VAL(POINTER, 0)) in scic_sds_controller_initialize_completion_queue()
497 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) in scic_sds_controller_initialize_completion_queue()
503 for (index = 0; index < this_controller->completion_queue_entries; index++) in scic_sds_controller_initialize_completion_queue()
508 this_controller->completion_queue[index] = 0x80000000; in scic_sds_controller_initialize_completion_queue()
533 SCU_UFQGP_GEN_VAL(POINTER, 0) in scic_sds_controller_initialize_unsolicited_frame_queue()
540 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); in scic_sds_controller_initialize_unsolicited_frame_queue()
581 this_controller, this_controller->lex_registers + 0xC4); in scic_sds_controller_lex_status_read_fence()
586 "Controller 0x%x lex_status = 0x%08x\n", in scic_sds_controller_lex_status_read_fence()
602 this_controller, this_controller->lex_registers + 0x28, 0x0020FFFF) ; in scic_sds_controller_lex_atux_initialization()
606 this_controller, this_controller->lex_registers + 0xC0, 0x00000700); in scic_sds_controller_lex_atux_initialization()
612 this_controller, this_controller->lex_registers + 0x70, 0x00000002); in scic_sds_controller_lex_atux_initialization()
616 this_controller, this_controller->lex_registers + 0xC0, 0x00000300); in scic_sds_controller_lex_atux_initialization()
622 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF); in scic_sds_controller_lex_atux_initialization()
629 #if 0 in scic_sds_controller_lex_atux_initialization()
632 this_controller, this_controller->lex_registers + 0x28, 0x0000FFFF); in scic_sds_controller_lex_atux_initialization()
637 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ; in scic_sds_controller_lex_atux_initialization()
644 #if 0 in scic_sds_controller_lex_atux_initialization()
647 this_controller, this_controller->lex_registers + 0x28, 0x0040FFFF) ; in scic_sds_controller_lex_atux_initialization()
652 this_controller, this_controller->lex_registers + 0xC0, 0x00000100); in scic_sds_controller_lex_atux_initialization()
658 this_controller, this_controller->lex_registers + 0xC0, 0x00000000); in scic_sds_controller_lex_atux_initialization()
665 this_controller, this_controller->lex_registers + 0xC0, 0x00000800); in scic_sds_controller_lex_atux_initialization()
670 #if 0 in scic_sds_controller_lex_atux_initialization()
674 this_controller, this_controller->lex_registers + 0xC0, 0x27800000); in scic_sds_controller_lex_atux_initialization()
679 this_controller, this_controller->lex_registers + 0x28, 0x0000FF77); in scic_sds_controller_lex_atux_initialization()
682 this_controller, this_controller->lex_registers + 0x28, 0x0000FF55); in scic_sds_controller_lex_atux_initialization()
685 this_controller, this_controller->lex_registers + 0x28, 0x0000FF11); in scic_sds_controller_lex_atux_initialization()
688 this_controller, this_controller->lex_registers + 0x28, 0x0000FF00); in scic_sds_controller_lex_atux_initialization()
691 this_controller, this_controller->lex_registers + 0x28, 0x0003FF00); in scic_sds_controller_lex_atux_initialization()
708 this_controller, this_controller->lex_registers + 0x88, 0x09090909); in scic_sds_controller_enable_chipwatch()
711 this_controller, this_controller->lex_registers + 0x8C, 0xcac9c862); in scic_sds_controller_enable_chipwatch()
737 // pe_afe0_rst_n = 0 in scic_sds_controller_afe_initialization()
740 // pe_afe0_txrst0,1,2,3_n = 0 in scic_sds_controller_afe_initialization()
741 // pe_afe0_rxrst0,1,2,3_n = 0 in scic_sds_controller_afe_initialization()
746 this_controller, afe_pll_control, 0x00247506); in scic_sds_controller_afe_initialization()
748 // 2. Write 0x00000000 to AFE XCVR Ctrl2 in scic_sds_controller_afe_initialization()
750 this_controller, afe_dfx_transceiver_status_clear, 0x00000000); in scic_sds_controller_afe_initialization()
752 // 3. afe0_override_en = 0 in scic_sds_controller_afe_initialization()
753 // afe0_pll_dis_override = 0 in scic_sds_controller_afe_initialization()
754 // afe0_tx_rst_override = 0 in scic_sds_controller_afe_initialization()
762 this_controller, afe_transceiver_control0[0], 0x0700141e); in scic_sds_controller_afe_initialization()
765 // Write 0x00200506 to AFE PLL Ctrl Register 0 in scic_sds_controller_afe_initialization()
766 scu_afe_register_write(this_controller, afe_pll_control, 0x00200506); in scic_sds_controller_afe_initialization()
767 scu_afe_register_write(this_controller, afe_pll_dfx_control, 0x10000080); in scic_sds_controller_afe_initialization()
770 scu_afe_register_write(this_controller, afe_bias_control[0], 0x00124814); in scic_sds_controller_afe_initialization()
771 scu_afe_register_write(this_controller, afe_bias_control[1], 0x24900000); in scic_sds_controller_afe_initialization()
775 this_controller, afe_transceiver_control0[0], 0x0702941e); in scic_sds_controller_afe_initialization()
778 this_controller, afe_transceiver_control1[0], 0x0000000a); in scic_sds_controller_afe_initialization()
782 this_controller, afe_transceiver_equalization_control[0], 0x00ba2223); in scic_sds_controller_afe_initialization()
785 this_controller, reserved_0028_003c[2], 0x00000000); in scic_sds_controller_afe_initialization()
789 this_controller, afe_dfx_transmit_control_register[0], 0x03815428); in scic_sds_controller_afe_initialization()
793 this_controller, afe_dfx_transceiver_status_clear, 0x00000010); in scic_sds_controller_afe_initialization()
796 scu_afe_register_write(this_controller, afe_pll_control, 0x00200504); in scic_sds_controller_afe_initialization()
799 scu_afe_register_write(this_controller, afe_pll_control, 0x00200505); in scic_sds_controller_afe_initialization()
802 // (afe0_comm_sta [1:0] should go to 1'b11, and in scic_sds_controller_afe_initialization()
803 // [5:2] is 0x5, 0x6, 0x7, 0x8, or 0x9 in scic_sds_controller_afe_initialization()
804 scu_afe_register_write(this_controller, afe_pll_control, 0x00200501); in scic_sds_controller_afe_initialization()
806 while ((scu_afe_register_read(this_controller, afe_common_status) & 0x03) != 0x03) in scic_sds_controller_afe_initialization()
812 // 13. pe_afe0_rxpdn0 = 0 in scic_sds_controller_afe_initialization()
815 // pe_afe_txoob0_n = 0 in scic_sds_controller_afe_initialization()
817 this_controller, afe_transceiver_control0[0], 0x07028c11); in scic_sds_controller_afe_initialization()
832 this_controller, afe_dfx_master_control0, 0x0000000f); in scic_sds_controller_afe_initialization()
835 this_controller, afe_bias_control, 0x0000aa00); in scic_sds_controller_afe_initialization()
838 this_controller, afe_pll_control0, 0x80000908); in scic_sds_controller_afe_initialization()
847 while((afe_status & 0x00001000) == 0); in scic_sds_controller_afe_initialization()
849 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) in scic_sds_controller_afe_initialization()
853 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000157); in scic_sds_controller_afe_initialization()
856 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016d1a); in scic_sds_controller_afe_initialization()
859 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01501014); in scic_sds_controller_afe_initialization()
862 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000); in scic_sds_controller_afe_initialization()
865 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08); in scic_sds_controller_afe_initialization()
867 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00); in scic_sds_controller_afe_initialization()
869 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09); in scic_sds_controller_afe_initialization()
871 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e); in scic_sds_controller_afe_initialization()
874 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00000000); in scic_sds_controller_afe_initialization()
877 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3208903f); in scic_sds_controller_afe_initialization()
882 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154); in scic_sds_controller_afe_initialization()
886 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801611a); in scic_sds_controller_afe_initialization()
890 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x3801631a); in scic_sds_controller_afe_initialization()
894 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016318); in scic_sds_controller_afe_initialization()
898 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319); in scic_sds_controller_afe_initialization()
902 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x38016319); in scic_sds_controller_afe_initialization()
908 this_controller, afe_dfx_master_control0, 0x00010f00); in scic_sds_controller_afe_initialization()
913 this_controller, afe_dfx_master_control0, 0x0081000f); in scic_sds_controller_afe_initialization()
916 this_controller, afe_bias_control, 0x0000aa00); in scic_sds_controller_afe_initialization()
919 this_controller, afe_pll_control0, 0x80000908); in scic_sds_controller_afe_initialization()
930 while((afe_status & 0x00001000) == 0); in scic_sds_controller_afe_initialization()
934 this_controller, afe_dfx_master_control1, 0x00000000); in scic_sds_controller_afe_initialization()
937 this_controller, afe_pmsn_master_control0, 0x7bd316ad); in scic_sds_controller_afe_initialization()
939 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) in scic_sds_controller_afe_initialization()
943 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000174); in scic_sds_controller_afe_initialization()
946 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000); in scic_sds_controller_afe_initialization()
949 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0000651a); in scic_sds_controller_afe_initialization()
952 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518); in scic_sds_controller_afe_initialization()
955 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006518); in scic_sds_controller_afe_initialization()
957 #if 0 in scic_sds_controller_afe_initialization()
960 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00000000); in scic_sds_controller_afe_initialization()
963 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control0, 0x000bdd08); in scic_sds_controller_afe_initialization()
965 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control1, 0x000ffc00); in scic_sds_controller_afe_initialization()
967 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control2, 0x000b7c09); in scic_sds_controller_afe_initialization()
969 this_controller, scu_afe_xcvr[phy_id].afe_tx_amp_control3, 0x000afc6e); in scic_sds_controller_afe_initialization()
974 this_controller, scu_afe_xcvr[phy_id].afe_channel_control, 0x00000154); in scic_sds_controller_afe_initialization()
979 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x00000080); in scic_sds_controller_afe_initialization()
982 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x01041042); in scic_sds_controller_afe_initialization()
985 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x320891bf); in scic_sds_controller_afe_initialization()
989 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006118); in scic_sds_controller_afe_initialization()
993 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006108); in scic_sds_controller_afe_initialization()
998 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x0317108f); in scic_sds_controller_afe_initialization()
1002 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01e00021); in scic_sds_controller_afe_initialization()
1006 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006109); in scic_sds_controller_afe_initialization()
1010 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006009); in scic_sds_controller_afe_initialization()
1014 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00006209); in scic_sds_controller_afe_initialization()
1020 this_controller, afe_dfx_master_control0, 0x00010f00); in scic_sds_controller_afe_initialization()
1055 this_controller, afe_dfx_master_control0, 0x0081000f); in scic_sds_controller_afe_initialization()
1066 this_controller, afe_pmsn_master_control2, 0x0007FFFF); in scic_sds_controller_afe_initialization()
1072 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500); in scic_sds_controller_afe_initialization()
1074 scu_afe_register_write(this_controller, afe_bias_control, 0x00005A00); in scic_sds_controller_afe_initialization()
1077 scu_afe_register_write(this_controller, afe_bias_control, 0x00005F00); in scic_sds_controller_afe_initialization()
1079 scu_afe_register_write(this_controller, afe_bias_control, 0x00005500); in scic_sds_controller_afe_initialization()
1088 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040908); in scic_sds_controller_afe_initialization()
1093 scu_afe_register_write(this_controller, afe_pll_control0, 0x80040A08); in scic_sds_controller_afe_initialization()
1097 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08); in scic_sds_controller_afe_initialization()
1099 scu_afe_register_write(this_controller, afe_pll_control0, 0x00000b08); in scic_sds_controller_afe_initialization()
1101 scu_afe_register_write(this_controller, afe_pll_control0, 0x80000b08); in scic_sds_controller_afe_initialization()
1115 while((afe_status & 0x00001000) == 0); in scic_sds_controller_afe_initialization()
1122 this_controller, afe_pmsn_master_control0, 0x7bcc96ad); in scic_sds_controller_afe_initialization()
1126 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) in scic_sds_controller_afe_initialization()
1135 // Enable....(0xe800) in scic_sds_controller_afe_initialization()
1137 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004512 in scic_sds_controller_afe_initialization()
1142 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x0050100F in scic_sds_controller_afe_initialization()
1150 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00030000 in scic_sds_controller_afe_initialization()
1158 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202 in scic_sds_controller_afe_initialization()
1163 // Enable....(0xe800) in scic_sds_controller_afe_initialization()
1165 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014500 in scic_sds_controller_afe_initialization()
1173 this_controller, scu_afe_xcvr[phy_id].afe_tx_ssc_control, 0x00010202 in scic_sds_controller_afe_initialization()
1178 // Enable....(0xe800) in scic_sds_controller_afe_initialization()
1180 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001C500 in scic_sds_controller_afe_initialization()
1185 // & increase TX int & ext bias 20%....(0xe85c) in scic_sds_controller_afe_initialization()
1191 0x000003D4 in scic_sds_controller_afe_initialization()
1199 0x000003F0 in scic_sds_controller_afe_initialization()
1208 0x000003d7 in scic_sds_controller_afe_initialization()
1214 // & increase TX int & ext bias 20%....(0xe85c) in scic_sds_controller_afe_initialization()
1218 0x000003d4 in scic_sds_controller_afe_initialization()
1226 0x000001e7 in scic_sds_controller_afe_initialization()
1232 // & increase TX int & ext bias 20%....(0xe85c) in scic_sds_controller_afe_initialization()
1236 0x000001e4 in scic_sds_controller_afe_initialization()
1244 cable_length_long ? 0x000002F7 : in scic_sds_controller_afe_initialization()
1245 cable_length_medium ? 0x000001F7 : 0x000001F7 in scic_sds_controller_afe_initialization()
1251 // & increase TX int & ext bias 20%....(0xe85c) in scic_sds_controller_afe_initialization()
1255 cable_length_long ? 0x000002F4 : in scic_sds_controller_afe_initialization()
1256 cable_length_medium ? 0x000001F4 : 0x000001F4 in scic_sds_controller_afe_initialization()
1265 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1269 0x00040000 in scic_sds_controller_afe_initialization()
1278 // RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On), in scic_sds_controller_afe_initialization()
1279 // RDD=0x0(RX Detect Enabled) ....(0xe800) in scic_sds_controller_afe_initialization()
1281 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00004100); in scic_sds_controller_afe_initialization()
1287 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x00014100); in scic_sds_controller_afe_initialization()
1293 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control0, 0x0001c100); in scic_sds_controller_afe_initialization()
1303 0x3F09983F in scic_sds_controller_afe_initialization()
1311 0x3F11103F in scic_sds_controller_afe_initialization()
1319 0x3F11103F in scic_sds_controller_afe_initialization()
1323 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1325 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000); in scic_sds_controller_afe_initialization()
1330 this_controller, scu_afe_xcvr[phy_id].afe_xcvr_control1, 0x01400c0f); in scic_sds_controller_afe_initialization()
1334 this_controller, scu_afe_xcvr[phy_id].afe_rx_ssc_control0, 0x3f6f103f); in scic_sds_controller_afe_initialization()
1337 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1339 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000); in scic_sds_controller_afe_initialization()
1345 cable_length_long ? 0x01500C0C : in scic_sds_controller_afe_initialization()
1346 cable_length_medium ? 0x01400C0D : 0x02400C0D in scic_sds_controller_afe_initialization()
1351 this_controller, scu_afe_xcvr[phy_id].afe_dfx_rx_control1, 0x000003e0); in scic_sds_controller_afe_initialization()
1356 cable_length_long ? 0x33091C1F : in scic_sds_controller_afe_initialization()
1357 cable_length_medium ? 0x3315181F : 0x2B17161F in scic_sds_controller_afe_initialization()
1361 // Enable TX equalization (0xe824) in scic_sds_controller_afe_initialization()
1363 this_controller, scu_afe_xcvr[phy_id].afe_tx_control, 0x00040000); in scic_sds_controller_afe_initialization()
1395 this_controller, afe_dfx_master_control0, 0x00010f00); in scic_sds_controller_afe_initialization()
1428 "scic_sds_controller_transition_to_ready(0x%x, 0x%x) enter\n", in scic_sds_controller_transition_to_ready()
1511 for (index = 0; index < this_controller->logical_port_entries; index++) in scic_sds_controller_stop_ports()
1589 for (index = 0; index < SCI_MAX_PHYS; index++) in scic_sds_controller_is_start_complete()
1743 for (index = 0; index < SCI_MAX_PHYS; index++) in scic_sds_controller_stop_phys()
1783 for (index = 0; index < this_controller->remote_node_entries; index++) in scic_sds_controller_stop_devices()
1788 device_status = scic_remote_device_stop(this_controller->device_table[index], 0); in scic_sds_controller_stop_devices()
1798 "Controller stop operation failed to stop device 0x%x because of status %d.\n", in scic_sds_controller_stop_devices()
1877 this_controller->power_control.remote_devices_granted_power = 0; in scic_sds_controller_power_control_timer_handler()
1879 if (this_controller->power_control.phys_waiting == 0) in scic_sds_controller_power_control_timer_handler()
1888 for (i=0; in scic_sds_controller_power_control_timer_handler()
1890 && (this_controller->power_control.phys_waiting != 0); in scic_sds_controller_power_control_timer_handler()
1910 for (j = 0; j < SCI_MAX_PHYS; j++) in scic_sds_controller_power_control_timer_handler()
1964 //no_of_devices_granted_power will be set to 0 in scic_sds_controller_power_control_queue_insert()
1973 for(i = 0; i < SCI_MAX_PHYS; i++) in scic_sds_controller_power_control_queue_insert()
2277 "SCIC Controller 0x%x received SMU command error 0x%x\n", in scic_sds_controller_event_completion()
2297 "SCIC Controller 0x%x received fatal controller event 0x%x\n", in scic_sds_controller_event_completion()
2325 … "SCIC Controller 0x%x received event 0x%x for io request object that doesnt exist.\n", in scic_sds_controller_event_completion()
2345 … "SCIC Controller 0x%x received event 0x%x for remote device object that doesnt exist.\n", in scic_sds_controller_event_completion()
2385 … "SCIC Controller 0x%x received event 0x%x for remote device object 0x%0x that doesnt exist.\n", in scic_sds_controller_event_completion()
2415 U32 completion_count = 0; in scic_sds_controller_process_completions()
2425 "scic_sds_controller_process_completions(0x%x) enter\n", in scic_sds_controller_process_completions()
2432 "completion queue beginning get : 0x%08x\n", in scic_sds_controller_process_completions()
2456 "completion queue entry : 0x%08x\n", in scic_sds_controller_process_completions()
2497 if (completion_count > 0) in scic_sds_controller_process_completions()
2511 "completion queue ending get : 0x%08x\n", in scic_sds_controller_process_completions()
2530 U32 completion_count = 0; in scic_sds_controller_transitioned_process_completions()
2540 "scic_sds_controller_transitioned_process_completions(0x%x) enter\n", in scic_sds_controller_transitioned_process_completions()
2547 "completion queue beginning get : 0x%08x\n", in scic_sds_controller_transitioned_process_completions()
2572 "completion queue entry : 0x%08x\n", in scic_sds_controller_transitioned_process_completions()
2601 if (completion_count > 0) in scic_sds_controller_transitioned_process_completions()
2615 "completion queue ending get : 0x%08x\n", in scic_sds_controller_transitioned_process_completions()
2647 "scic_sds_controller_standard_interrupt_handler(0x%d,0x%d) enter\n", in scic_sds_controller_standard_interrupt_handler()
2697 "scic_sds_controller_polling_interrupt_handler(0x%d) enter\n", in scic_sds_controller_polling_interrupt_handler()
2712 SMU_ISR_QUEUE_SUSPEND)) == 0) in scic_sds_controller_polling_interrupt_handler()
2740 "scic_sds_controller_polling_completion_handler(0x%d) enter\n", in scic_sds_controller_polling_completion_handler()
2829 "scic_sds_controller_legacy_completion_handler(0x%d) enter\n", in scic_sds_controller_legacy_completion_handler()
2835 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_legacy_completion_handler()
2839 volatile U32 int_mask_value = 0; in scic_sds_controller_legacy_completion_handler()
2840 ULONG count = 0; in scic_sds_controller_legacy_completion_handler()
2860 } while (int_mask_value != 0); in scic_sds_controller_legacy_completion_handler()
2889 SMU_IMR_WRITE(this_controller, 0xFFFFFFFF); in scic_sds_controller_single_vector_interrupt_handler()
2895 (interrupt_status == 0) in scic_sds_controller_single_vector_interrupt_handler()
2907 if (interrupt_status != 0) in scic_sds_controller_single_vector_interrupt_handler()
2916 SMU_ISR_WRITE(this_controller, 0x00000000); in scic_sds_controller_single_vector_interrupt_handler()
2917 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_single_vector_interrupt_handler()
2940 "scic_sds_controller_single_vector_completion_handler(0x%d) enter\n", in scic_sds_controller_single_vector_completion_handler()
2996 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_single_vector_completion_handler()
3031 SMU_IMR_WRITE(this_controller, 0xFF000000); in scic_sds_controller_normal_vector_interrupt_handler()
3032 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_normal_vector_interrupt_handler()
3055 "scic_sds_controller_normal_vector_completion_handler(0x%d) enter\n", in scic_sds_controller_normal_vector_completion_handler()
3068 SMU_IMR_WRITE(this_controller, 0xFF000000); in scic_sds_controller_normal_vector_completion_handler()
3069 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_normal_vector_completion_handler()
3096 if (interrupt_status != 0) in scic_sds_controller_error_vector_interrupt_handler()
3108 SMU_IMR_WRITE(this_controller, 0x000000FF); in scic_sds_controller_error_vector_interrupt_handler()
3109 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_error_vector_interrupt_handler()
3132 "scic_sds_controller_error_vector_completion_handler(0x%d) enter\n", in scic_sds_controller_error_vector_completion_handler()
3166 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_sds_controller_error_vector_completion_handler()
3302 … "SCIC Controller 0x%x remote device started event from device 0x%x in unexpected state %d\n", in scic_sds_controller_remote_device_started()
3323 for (index = 0; index < this_controller->remote_node_entries; index++) in scic_sds_controller_has_remote_devices_stopping()
3363 … "SCIC Controller 0x%x remote device stopped event from device 0x%x in unexpected state %d\n", in scic_sds_controller_remote_device_stopped()
3387 "SCIC Controller 0x%08x post request 0x%08x\n", in scic_sds_controller_post_request()
3706 this_controller->oem_parameters.sds1.controller.ssc_sata_tx_spread_level = 0; in scic_sds_controller_set_default_config_parameters()
3707 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_spread_level = 0; in scic_sds_controller_set_default_config_parameters()
3708 this_controller->oem_parameters.sds1.controller.ssc_sas_tx_type = 0; in scic_sds_controller_set_default_config_parameters()
3711 this_controller->oem_parameters.sds1.controller.cable_selection_mask = 0; in scic_sds_controller_set_default_config_parameters()
3714 for (index = 0; index < SCI_MAX_PORTS; index++) in scic_sds_controller_set_default_config_parameters()
3716 this_controller->oem_parameters.sds1.ports[index].phy_mask = 0; in scic_sds_controller_set_default_config_parameters()
3720 for (index = 0; index < SCI_MAX_PHYS; index++) in scic_sds_controller_set_default_config_parameters()
3726 //the frequencies cannot be 0 in scic_sds_controller_set_default_config_parameters()
3727 this_controller->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f; in scic_sds_controller_set_default_config_parameters()
3728 … this_controller->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff; in scic_sds_controller_set_default_config_parameters()
3729 …this_controller->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; in scic_sds_controller_set_default_config_parameters()
3734 // Hence, usage of 0x5FCFFFFF. in scic_sds_controller_set_default_config_parameters()
3736 = 0x5FCFFFFF; in scic_sds_controller_set_default_config_parameters()
3740 = 0x00000001 + this_controller->controller_index; in scic_sds_controller_set_default_config_parameters()
3746 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000E7C03; in scic_sds_controller_set_default_config_parameters()
3747 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000E7C03; in scic_sds_controller_set_default_config_parameters()
3748 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000E7C03; in scic_sds_controller_set_default_config_parameters()
3749 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000E7C03; in scic_sds_controller_set_default_config_parameters()
3753 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control0 = 0x000BDD08; in scic_sds_controller_set_default_config_parameters()
3754 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control1 = 0x000B7069; in scic_sds_controller_set_default_config_parameters()
3755 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control2 = 0x000B7C09; in scic_sds_controller_set_default_config_parameters()
3756 this_controller->oem_parameters.sds1.phys[index].afe_tx_amp_control3 = 0x000AFC6E; in scic_sds_controller_set_default_config_parameters()
3793 "scic_sds_controller_release_resource(0x%x) enter\n", in scic_sds_controller_release_resource()
3819 for(index = 0; index < SCI_MAX_PORTS+1; index++) in scic_sds_controller_release_resource()
3825 for(index = 0; index < SCI_MAX_PHYS; index++) in scic_sds_controller_release_resource()
3874 "scic_controller_construct(0x%x, 0x%x) enter\n", in scic_controller_construct()
3879 memset(this_controller, 0, sizeof(SCIC_SDS_CONTROLLER_T)); in scic_controller_construct()
3921 "scic_controller_initialize(0x%x, 0x%d) enter\n", in scic_controller_initialize()
3953 return 0; in scic_controller_get_suggested_start_timeout()
3987 "scic_controller_start(0x%x, 0x%d) enter\n", in scic_controller_start()
4025 "scic_controller_stop(0x%x, 0x%d) enter\n", in scic_controller_stop()
4062 "scic_controller_reset(0x%x) enter\n", in scic_controller_reset()
4100 if (message_count == 0) in scic_controller_get_handler_methods()
4102 handler_methods[0].interrupt_handler in scic_controller_get_handler_methods()
4104 handler_methods[0].completion_handler in scic_controller_get_handler_methods()
4114 handler_methods[0].interrupt_handler in scic_controller_get_handler_methods()
4116 handler_methods[0].completion_handler in scic_controller_get_handler_methods()
4123 handler_methods[0].interrupt_handler in scic_controller_get_handler_methods()
4125 handler_methods[0].completion_handler in scic_controller_get_handler_methods()
4139 if (message_count == 0) in scic_controller_get_handler_methods()
4142 handler_methods[0].interrupt_handler in scic_controller_get_handler_methods()
4144 handler_methods[0].completion_handler in scic_controller_get_handler_methods()
4175 "scic_controller_start_io(0x%x, 0x%x, 0x%x, 0x%x) enter\n", in scic_controller_start_io()
4204 "scic_controller_terminate_request(0x%x, 0x%x, 0x%x) enter\n", in scic_controller_terminate_request()
4232 "scic_controller_complete_io(0x%x, 0x%x, 0x%x) enter\n", in scic_controller_complete_io()
4263 "scic_controller_start_task(0x%x, 0x%x, 0x%x, 0x%x) enter\n", in scic_controller_start_task()
4303 "scic_controller_complete_task(0x%x, 0x%x, 0x%x) enter\n", in scic_controller_complete_task()
4343 "scic_controller_get_port_handle(0x%x, 0x%x, 0x%x) enter\n", in scic_controller_get_port_handle()
4371 "scic_controller_get_phy_handle(0x%x, 0x%x, 0x%x) enter\n", in scic_controller_get_phy_handle()
4385 "Controller:0x%x PhyId:0x%x invalid phy index\n", in scic_controller_get_phy_handle()
4406 "scic_controller_allocate_io_tag(0x%x) enter\n", in scic_controller_allocate_io_tag()
4440 "scic_controller_free_io_tag(0x%x, 0x%x) enter\n", in scic_controller_free_io_tag()
4474 SMU_IMR_WRITE(this_controller, 0x00000000); in scic_controller_enable_interrupts()
4488 SMU_IMR_WRITE(this_controller, 0xffffffff); in scic_controller_disable_interrupts()
4504 "scic_controller_set_mode(0x%x, 0x%x) enter\n", in scic_controller_set_mode()
4571 SMU_SMUSRCR_WRITE(this_controller, 0xFFFFFFFF); in scic_sds_controller_reset_hardware()
4577 SMU_CQGR_WRITE(this_controller, 0x00000000); in scic_sds_controller_reset_hardware()
4580 SCU_UFQGP_WRITE(this_controller, 0x00000000); in scic_sds_controller_reset_hardware()
4605 for (index = 0; index < SCI_MAX_PHYS; index++) in scic_user_parameters_set()
4618 (scic_parms->sds1.phys[index].align_insertion_frequency == 0) || in scic_user_parameters_set()
4619 (scic_parms->sds1.phys[index].notify_enable_spin_up_insertion_frequency == 0) in scic_user_parameters_set()
4627 (scic_parms->sds1.stp_inactivity_timeout == 0) || in scic_user_parameters_set()
4628 (scic_parms->sds1.ssp_inactivity_timeout == 0) || in scic_user_parameters_set()
4629 (scic_parms->sds1.stp_max_occupancy_timeout == 0) || in scic_user_parameters_set()
4630 (scic_parms->sds1.ssp_max_occupancy_timeout == 0) || in scic_user_parameters_set()
4631 (scic_parms->sds1.no_outbound_task_timeout == 0) in scic_user_parameters_set()
4680 U8 combined_phy_mask = 0; in scic_oem_parameters_set()
4691 for(index=0; index<SCI_MAX_PORTS; index++) in scic_oem_parameters_set()
4699 for(index=0; index<SCI_MAX_PHYS; index++) in scic_oem_parameters_set()
4702 scic_parms->sds1.phys[index].sas_address.sci_format.high == 0 in scic_oem_parameters_set()
4703 && scic_parms->sds1.phys[index].sas_address.sci_format.low == 0 in scic_oem_parameters_set()
4711 (scic_parms->sds1.phys[index].afe_tx_amp_control0 == 0) || in scic_oem_parameters_set()
4712 (scic_parms->sds1.phys[index].afe_tx_amp_control1 == 0) || in scic_oem_parameters_set()
4713 (scic_parms->sds1.phys[index].afe_tx_amp_control2 == 0) || in scic_oem_parameters_set()
4714 (scic_parms->sds1.phys[index].afe_tx_amp_control3 == 0) in scic_oem_parameters_set()
4724 for(index=0; index<SCI_MAX_PHYS; index++) in scic_oem_parameters_set()
4726 if (scic_parms->sds1.ports[index].phy_mask != 0) in scic_oem_parameters_set()
4734 for(index=0; index<SCI_MAX_PHYS; index++) in scic_oem_parameters_set()
4739 if (combined_phy_mask == 0) in scic_oem_parameters_set()
4754 if (old_oem_params->controller.do_enable_ssc != 0) in scic_oem_parameters_set()
4757 && (old_oem_params->controller.do_enable_ssc != 0x01)) in scic_oem_parameters_set()
4766 if ( !((test == 0x0) || (test == 0x2) || (test == 0x3) || in scic_oem_parameters_set()
4767 (test == 0x6) || (test == 0x7)) ) in scic_oem_parameters_set()
4771 if (oem_params->controller.ssc_sas_tx_type == 0) in scic_oem_parameters_set()
4773 if ( !((test == 0x0) || (test == 0x2) || (test == 0x3)) ) in scic_oem_parameters_set()
4779 if ( !((test == 0x0) || (test == 0x3) || (test == 0x6)) ) in scic_oem_parameters_set()
4823 U8 timeout_encode = 0; in scic_controller_set_interrupt_coalescence()
4824 U32 min = 0; in scic_controller_set_interrupt_coalescence()
4825 U32 max = 0; in scic_controller_set_interrupt_coalescence()
4834 // 0 - - Disabled in scic_controller_set_interrupt_coalescence()
4867 if (coalesce_timeout == 0) in scic_controller_set_interrupt_coalescence()
4868 timeout_encode = 0; in scic_controller_set_interrupt_coalescence()
4957 *value = 0x00000000; in scic_controller_read_scratch_ram_dword()
5043 for (index = 0; index < SCI_MAX_PORTS; index++) in scic_controller_suspend()
5049 SMU_CQGR_WRITE(this_controller, 0x00000000); in scic_controller_suspend()
5050 SCU_UFQGP_WRITE(this_controller, 0x00000000); in scic_controller_suspend()
5053 // by setting CQGR and CQPR back to 0 in scic_controller_suspend()
5054 SMU_ISR_WRITE(this_controller, 0xFFFFFFFF); in scic_controller_suspend()
5057 this_controller->completion_queue_get = 0; in scic_controller_suspend()
5079 for (index = 0; index < SCI_MAX_PORTS; index++) in scic_controller_resume()
5086 for (index = 0; index < SCI_MAX_PHYS; index ++) in scic_controller_resume()
5091 if ((link_layer_status & SCU_SAS_LLSTA_DWORD_SYNCA_BIT) == 0) in scic_controller_resume()
5116 "scic_controller_transition(0x%x) enter\n", in scic_controller_transition()
5125 for (index = 0; index < SCI_MAX_PORTS; index++) in scic_controller_transition()
5127 if (this_controller->port_table[index].started_request_count != 0) in scic_controller_transition()
5317 "scic_sds_controller_resetting_state_enter(0x%x) enter\n", in scic_sds_controller_general_reset_handler()
5366 "scic_sds_controller_reset_state_initialize_handler(0x%x) enter\n", in scic_sds_controller_reset_state_initialize_handler()
5410 SMU_SMUSRCR_WRITE(this_controller, 0x00000000); in scic_sds_controller_reset_state_initialize_handler()
5453 for (index = 0; index < max_supported_ports; index++) in scic_sds_controller_reset_state_initialize_handler()
5499 for (index = 0; in scic_sds_controller_reset_state_initialize_handler()
5520 for (index = 0; in scic_sds_controller_reset_state_initialize_handler()
5558 … "Invalid Port Configuration from scic_sds_controller_reset_state_initialize_handler(0x%x) \n", in scic_sds_controller_reset_state_initialize_handler()
5621 for (index = 0; index < this_controller->task_context_entries; index++) in scic_sds_controller_initialized_state_start_handler()
5657 index = 0; in scic_sds_controller_initialized_state_start_handler()
5671 if (timeout != 0) in scic_sds_controller_initialized_state_start_handler()
5771 if (timeout != 0) in scic_sds_controller_ready_state_stop_handler()
6222 … "scic_sds_controller_resetting_state_enter(0x%x) enter\n not allowed with fatal memory error", in scic_sds_controller_failed_state_reset_handler()
6530 for (index = 0; index < (SCI_MAX_PORTS + 1); index++) in scic_sds_controller_reset_state_enter()
6540 for (index = 0; index < SCI_MAX_PHYS; index++) in scic_sds_controller_reset_state_enter()
6550 this_controller->invalid_phy_mask = 0; in scic_sds_controller_reset_state_enter()
6698 this_controller, 0x10, 250); in scic_sds_controller_ready_state_enter()
6733 scic_controller_set_interrupt_coalescence(this_controller, 0, 0); in scic_sds_controller_ready_state_exit()
6857 "scic_sds_controller_resetting_state_enter(0x%x) enter\n", in scic_sds_controller_resetting_state_enter()
6893 for (index = 0; in scic_sds_abort_reqests()
6894 (index < SCI_MAX_IO_REQUESTS) && (request_count > 0); in scic_sds_abort_reqests()