Lines Matching refs:GENMASK_ULL

332 #ifndef GENMASK_ULL
333 #define GENMASK_ULL(high, low)	((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (lo…  macro
361 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
363 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
365 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
367 #define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)
369 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
371 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
373 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
375 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
377 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
381 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
383 #define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)
389 #define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)
399 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
401 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
403 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)
407 #define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52)
414 #define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)
416 #define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)
418 #define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)
420 #define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)
422 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
424 #define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)
426 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
428 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
430 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
439 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
441 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
443 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
447 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
449 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
451 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
453 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)
455 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
457 #define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)
463 #define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)
465 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
467 #define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)
469 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
471 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
473 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
475 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
477 #define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)
481 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
483 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
489 #define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)
491 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
497 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
500 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
502 #define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)
504 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
507 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
509 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
511 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
513 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
519 #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)
526 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
529 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
531 #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)
533 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
551 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
553 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
557 #define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62)
559 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
561 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
563 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
565 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
567 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
569 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
572 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
582 #define IRDMACQ_OP GENMASK_ULL(61, 56)
585 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
593 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
597 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
601 #define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)
603 #define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)
605 #define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)
607 #define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)
609 #define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)
614 #define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)
616 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
618 #define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)
620 #define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)
622 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
628 #define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)
630 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
632 #define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)
634 #define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)
636 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
638 #define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)
642 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
644 #define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)
648 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
650 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
654 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
657 #define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)
667 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
669 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
692 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
702 #define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)
708 #define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)
714 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
716 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
721 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
725 #define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)
737 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
743 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
745 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
747 #define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)
749 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
761 #define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)
763 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
776 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
779 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
784 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
790 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
792 #define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)
794 #define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)
796 #define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)
798 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
800 #define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)
802 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
804 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
806 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
814 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
816 #define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)
818 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
822 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
829 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
831 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
833 #define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)
842 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
844 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
851 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
856 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
858 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
860 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
862 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
872 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
874 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
882 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
885 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
889 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
892 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
894 #define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)
896 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
898 #define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)
900 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
902 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
904 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
914 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
918 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
920 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
922 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
931 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
933 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
939 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
941 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
955 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
969 #define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)
973 #define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)
980 #define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)
984 #define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)
996 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
1000 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
1002 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
1010 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
1012 #define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)
1014 #define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)
1020 #define IRDMAQPC_TOS GENMASK_ULL(31, 24)
1022 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
1024 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
1026 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
1028 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
1030 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
1032 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
1034 #define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)
1036 #define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)
1038 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
1040 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
1042 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
1052 #define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)
1054 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
1056 #define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)
1058 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
1060 #define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)
1062 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
1064 #define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)
1066 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
1068 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
1070 #define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)
1072 #define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)
1074 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
1076 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
1078 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
1080 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
1082 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
1084 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
1086 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
1088 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
1090 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
1092 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
1094 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
1096 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
1098 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
1100 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
1102 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
1104 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
1106 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
1108 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
1110 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
1112 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
1114 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
1116 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
1118 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
1120 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
1122 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
1124 #define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)
1126 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
1128 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
1130 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
1132 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
1134 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
1136 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
1138 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
1141 #define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)
1166 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
1168 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
1170 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
1182 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
1184 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
1189 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
1191 #define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)
1193 #define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)
1195 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
1197 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
1199 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
1201 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
1203 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
1205 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
1207 #define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)
1209 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
1211 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
1213 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
1215 #define IRDMA_RSVD GENMASK_ULL(55, 41)
1218 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
1222 #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)
1236 #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)
1247 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
1249 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
1251 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
1253 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
1255 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
1257 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
1259 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
1261 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
1267 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
1274 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
1276 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
1282 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
1291 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
1293 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
1299 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
1302 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
1304 #define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)
1308 #define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)
1310 #define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)
1312 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
1314 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
1316 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
1318 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
1344 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
1346 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
1348 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
1350 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
1353 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
1355 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
1357 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
1359 #define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)
1361 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
1363 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
1365 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
1367 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
1369 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0)