Lines Matching +full:48 +full:- +full:bit
1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2015 - 2023 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
96 #define IRDMA_BYTE_48 48
181 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
274 IRDMA_OP_CQ_MODIFY = 48,
333 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (lo…
336 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
344 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
346 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
348 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
350 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
427 #define IRDMA_CQPSQ_WS_VSI_S 48
428 #define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)
464 #define IRDMA_CQPHC_MIN_RATE_S 48
465 #define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)
472 #define IRDMA_CQPHC_RAI_FACTOR_S 48
473 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
552 #define IRDMA_CQ_UDVLAN_S 48
553 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
629 #define IRDMA_UDA_QPSQ_IPLEN_S 48
630 #define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)
668 #define IRDMA_CQPSQ_QP_TERMLEN_S 48
669 #define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)
691 #define IRDMA_CQPSQ_QP_QPTYPE_S 48
692 #define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)
730 #define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48
731 #define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
762 #define IRDMA_CQPSQ_STAG_ARIGHTS_S 48
763 #define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)
824 /* Manage Push Page - MPP */
838 /* Upload Context - UCTX */
843 #define IRDMA_CQPSQ_UCTX_QPTYPE_S 48
844 #define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)
901 #define IRDMA_CQPSQ_FWQE_SQMJERR_S 48
902 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
1023 #define IRDMAQPC_DESTPORTNUM_S 48
1024 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
1039 #define IRDMAQPC_ARPIDX_S 48
1040 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
1057 #define IRDMAQPC_PDIDX_S 48
1058 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
1121 #define IRDMAQPC_REXMIT_THRESH_S 48
1122 #define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)
1183 #define IRDMAQPC_SNDMARKOFFSET_S 48
1184 #define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)
1212 #define IRDMA_FEATURE_TYPE_S 48
1213 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
1266 #define IRDMAQPSQ_INLINEDATALEN_S 48
1267 #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)
1281 #define IRDMAQPSQ_STAGRIGHTS_S 48
1282 #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)
1313 #define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48
1314 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
1339 #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)
1340 #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)
1341 #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)
1373 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
1378 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
1383 (_ceq)->ceqe_base[_pos].buf \
1399 offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
1400 (_cqe) = (_cq)->cq_base[offset].buf; \
1404 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1409 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1430 (_retcode) = -ENOSPC; \
1441 (_retcode) = -ENOSPC; \
1452 (_retcode) = -ENOSPC; \
1459 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1463 (_retcode) = -ENOSPC; \
1483 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1488 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1493 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1498 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1503 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1507 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1516 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1521 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1526 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1568 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1569 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1570 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1571 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1572 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1573 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1574 IRDMA_SHADOWAREA_M = (128 - 1),
1575 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1576 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1589 * set_64bit_val - set 64 bit value to hw wqe
1600 * set_32bit_val - set 32 bit value to hw wqe
1611 * get_64bit_val - read 64 bit value from wqe
1622 * get_32bit_val - read 32 bit value from wqe
1625 * @val: return 32 bit value