Lines Matching +full:32 +full:-
1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2015 - 2023 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
94 #define IRDMA_BYTE_32 32
181 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
199 #define IRDMA_QP_WQE_MIN_SIZE 32
258 IRDMA_OP_MC_DESTROY = 32,
333 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (lo…
336 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
344 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
346 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
348 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
350 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
360 #define IRDMA_CQPSQ_QHASH_VLANID_S 32
361 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
362 #define IRDMA_CQPSQ_QHASH_QPN_S 32
363 #define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)
370 #define IRDMA_CQPSQ_QHASH_ADDR0_S 32
371 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
374 #define IRDMA_CQPSQ_QHASH_ADDR2_S 32
375 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
380 #define IRDMA_CQPSQ_QHASH_OPCODE_S 32
381 #define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)
398 #define IRDMA_CQPSQ_STATS_OP_S 32
399 #define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)
421 #define IRDMA_CQPSQ_WS_OP_S 32
422 #define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)
429 #define IRDMA_CQPSQ_WS_WEIGHT_S 32
430 #define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)
438 #define IRDMA_CQPSQ_UP_OP_S 32
439 #define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)
442 #define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32
443 #define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)
448 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32
449 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)
450 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32
451 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)
470 #define IRDMA_CQPHC_HAI_FACTOR_S 32
471 #define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)
480 #define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32
481 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
490 #define IRDMA_CQPHC_CEQPERVF_S 32
491 #define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)
496 #define IRDMA_CQPHC_ENABLED_VFS_S 32
497 #define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)
532 #define IRDMA_CQ_WQEIDX_S 32
533 #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)
560 #define IRDMA_CQ_IMMDATAUP32_S 32
561 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
564 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32
565 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
568 #define IRDMACQ_QPID_S 32
569 #define IRDMACQ_QPID GENMASK_ULL(55, 32)
597 #define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)
615 #define IRDMA_UDA_QPSQ_OPCODE_S 32
616 #define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)
649 #define IRDMA_CQPSQ_OPCODE_S 32
650 #define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)
666 #define IRDMA_CQPSQ_QP_NEWMSS_S 32
667 #define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)
677 #define IRDMA_CQPSQ_QP_OP_S 32
720 #define IRDMA_CQPSQ_CQ_OP_S 32
721 #define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)
748 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32
749 #define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)
797 #define IRDMA_CQPSQ_MLM_MAC4_S 32
798 #define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)
817 #define IRDMA_CQPSQ_MVPBP_SD_INX_S 32
818 #define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)
824 /* Manage Push Page - MPP */
838 /* Upload Context - UCTX */
857 #define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32
858 #define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)
887 #define IRDMA_COMMIT_FPM_BASE_S 32
899 #define IRDMA_CQPSQ_FWQE_SQMNERR_S 32
900 #define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)
921 #define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32
922 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
930 #define IRDMA_CQPSQ_UPESD_BM_S 32
931 #define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)
995 #define IRDMAQPC_PPIDX_S 32
996 #define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)
1021 #define IRDMAQPC_SRCPORTNUM_S 32
1022 #define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)
1025 #define IRDMAQPC_DESTIPADDR0_S 32
1026 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
1029 #define IRDMAQPC_DESTIPADDR2_S 32
1030 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
1037 #define IRDMAQPC_VLANTAG_S 32
1038 #define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)
1053 #define IRDMAQPC_RCVSCALE_S 32
1054 #define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)
1061 #define IRDMAQPC_PKEY_S 32
1062 #define IRDMAQPC_PKEY GENMASK_ULL(47, 32)
1065 #define IRDMAQPC_QKEY_S 32
1066 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
1075 #define IRDMAQPC_TIMESTAMP_AGE_S 32
1076 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
1079 #define IRDMAQPC_ISN_S 32
1080 #define IRDMAQPC_ISN GENMASK_ULL(55, 32)
1083 #define IRDMAQPC_LSN_S 32
1084 #define IRDMAQPC_LSN GENMASK_ULL(55, 32)
1085 #define IRDMAQPC_SNDWND_S 32
1086 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
1091 #define IRDMAQPC_RCVWND_S 32
1092 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
1095 #define IRDMAQPC_SNDUNA_S 32
1096 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
1099 #define IRDMAQPC_PSNUNA_S 32
1100 #define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)
1103 #define IRDMAQPC_RTTVAR_S 32
1104 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
1107 #define IRDMAQPC_CWND_S 32
1108 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
1109 #define IRDMAQPC_CWNDROCE_S 32
1110 #define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)
1113 #define IRDMAQPC_SNDWL2_S 32
1114 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
1115 #define IRDMAQPC_ERR_RQ_IDX_S 32
1116 #define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32)
1127 #define IRDMAQPC_RXCQNUM_S 32
1128 #define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)
1167 #define IRDMAQPC_TLOW_S 32
1168 #define IRDMAQPC_TLOW GENMASK_ULL(39, 32)
1181 #define IRDMAQPC_RCVMARKOFFSET_S 32
1182 #define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)
1194 #define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32
1195 #define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)
1198 #define IRDMAQPC_LOCAL_IPADDR2_S 32
1199 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
1202 #define IRDMAQPC_LOCAL_IPADDR0_S 32
1203 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
1210 #define IRDMA_FEATURE_CNT_S 32
1211 #define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)
1217 #define IRDMAQPSQ_OPCODE_S 32
1218 #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)
1246 #define IRDMAQPSQ_FRAG_LEN_S 32
1247 #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)
1252 #define IRDMAQPSQ_GEN1_FRAG_STAG_S 32
1253 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
1258 #define IRDMAQPSQ_DESTQPN_S 32
1259 #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)
1290 #define IRDMAQPSQ_PARENTMRSTAG_S 32
1291 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
1349 #define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32
1350 #define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)
1354 #define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32
1355 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
1356 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32
1357 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
1360 #define IRDMA_QUERY_FPM_TIMERBUCKET_S 32
1361 #define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)
1362 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32
1363 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
1364 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32
1365 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
1366 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32
1367 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
1373 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
1378 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
1383 (_ceq)->ceqe_base[_pos].buf \
1399 offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
1400 (_cqe) = (_cq)->cq_base[offset].buf; \
1404 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1409 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1430 (_retcode) = -ENOSPC; \
1441 (_retcode) = -ENOSPC; \
1452 (_retcode) = -ENOSPC; \
1459 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1463 (_retcode) = -ENOSPC; \
1483 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1488 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1493 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1498 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1503 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1507 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1516 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1521 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1526 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1542 IRDMA_WQE_SIZE_32 = 32,
1568 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1569 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1570 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1571 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1572 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1573 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1574 IRDMA_SHADOWAREA_M = (128 - 1),
1575 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1576 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1589 * set_64bit_val - set 64 bit value to hw wqe
1600 * set_32bit_val - set 32 bit value to hw wqe
1611 * get_64bit_val - read 64 bit value from wqe
1622 * get_32bit_val - read 32 bit value from wqe
1625 * @val: return 32 bit value