Lines Matching +full:0 +full:- +full:63
1 /*-
2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
4 * Copyright (c) 2015 - 2023 Intel Corporation
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
50 #define IRDMA_IRD_HW_SIZE_4 0
56 #define IRDMA_QP_STATE_INVALID 0
81 #define RDMA_OPCODE_M 0x0f
84 #define CQE_MAJOR_DRV 0x8000
90 #define IRDMA_BYTE_0 0
123 #define IRDMA_AE_SOURCE_RSVD 0x0
124 #define IRDMA_AE_SOURCE_RQ 0x1
125 #define IRDMA_AE_SOURCE_RQ_0011 0x3
127 #define IRDMA_AE_SOURCE_CQ 0x2
128 #define IRDMA_AE_SOURCE_CQ_0110 0x6
129 #define IRDMA_AE_SOURCE_CQ_1010 0xa
130 #define IRDMA_AE_SOURCE_CQ_1110 0xe
132 #define IRDMA_AE_SOURCE_SQ 0x5
133 #define IRDMA_AE_SOURCE_SQ_0111 0x7
135 #define IRDMA_AE_SOURCE_IN_WR 0x9
136 #define IRDMA_AE_SOURCE_IN_RR 0xb
137 #define IRDMA_AE_SOURCE_OUT_RR 0xd
138 #define IRDMA_AE_SOURCE_OUT_RR_1111 0xf
140 #define IRDMA_AE_SOURCE_RSRC_EXHT_Q1 0x1
141 #define IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR 0x5
143 #define IRDMA_TCP_STATE_NON_EXISTENT 0
181 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
183 #define IRDMAQP_TERM_SEND_TERM_AND_FIN 0
195 #define IRDMA_CQE_QTYPE_RQ 0
208 #define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
213 #define IRDMAQP_OP_RDMA_WRITE 0x00
214 #define IRDMAQP_OP_RDMA_READ 0x01
215 #define IRDMAQP_OP_RDMA_SEND 0x03
216 #define IRDMAQP_OP_RDMA_SEND_INV 0x04
217 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05
218 #define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06
219 #define IRDMAQP_OP_BIND_MW 0x08
220 #define IRDMAQP_OP_FAST_REGISTER 0x09
221 #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a
222 #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b
223 #define IRDMAQP_OP_NOP 0x0c
224 #define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d
225 #define IRDMAQP_OP_GEN_RTS_AE 0x30
281 #define IRDMA_CQP_OP_CREATE_QP 0x00
282 #define IRDMA_CQP_OP_MODIFY_QP 0x01
283 #define IRDMA_CQP_OP_DESTROY_QP 0x02
284 #define IRDMA_CQP_OP_CREATE_CQ 0x03
285 #define IRDMA_CQP_OP_MODIFY_CQ 0x04
286 #define IRDMA_CQP_OP_DESTROY_CQ 0x05
287 #define IRDMA_CQP_OP_ALLOC_STAG 0x09
288 #define IRDMA_CQP_OP_REG_MR 0x0a
289 #define IRDMA_CQP_OP_QUERY_STAG 0x0b
290 #define IRDMA_CQP_OP_REG_SMR 0x0c
291 #define IRDMA_CQP_OP_DEALLOC_STAG 0x0d
292 #define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e
293 #define IRDMA_CQP_OP_MANAGE_ARP 0x0f
294 #define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11
295 #define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12
296 #define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13
297 #define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14
298 #define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15
299 #define IRDMA_CQP_OP_CREATE_CEQ 0x16
300 #define IRDMA_CQP_OP_DESTROY_CEQ 0x18
301 #define IRDMA_CQP_OP_CREATE_AEQ 0x19
302 #define IRDMA_CQP_OP_DESTROY_AEQ 0x1b
303 #define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c
304 #define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d
305 #define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e
306 #define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f
307 #define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20
308 #define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21
309 #define IRDMA_CQP_OP_FLUSH_WQES 0x22
311 #define IRDMA_CQP_OP_GEN_AE 0x22
312 #define IRDMA_CQP_OP_MANAGE_APBVT 0x23
313 #define IRDMA_CQP_OP_NOP 0x24
314 #define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25
315 #define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26
316 #define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27
317 #define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28
318 #define IRDMA_CQP_OP_SUSPEND_QP 0x29
319 #define IRDMA_CQP_OP_RESUME_QP 0x2a
320 #define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b
321 #define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c
322 #define IRDMA_CQP_OP_MANAGE_STATS 0x2d
323 #define IRDMA_CQP_OP_GATHER_STATS 0x2e
324 #define IRDMA_CQP_OP_UP_MAP 0x2f
333 #define GENMASK_ULL(high, low) ((0xFFFFFFFFFFFFFFFFULL >> (64ULL - ((high) - (low) + 1ULL))) << (lo…
336 #define GENMASK(high, low) ((0xFFFFFFFFUL >> (32UL - ((high) - (low) + 1UL))) << (low))
344 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
346 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
348 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
350 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
352 #define IRDMA_MAX_STATS_16 0xffffULL
353 #define IRDMA_MAX_STATS_24 0xffffffULL
354 #define IRDMA_MAX_STATS_32 0xffffffffULL
355 #define IRDMA_MAX_STATS_48 0xffffffffffffULL
356 #define IRDMA_MAX_STATS_56 0xffffffffffffffULL
357 #define IRDMA_MAX_STATS_64 0xffffffffffffffffULL
359 #define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF
364 #define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0
365 #define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)
368 #define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0
369 #define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)
371 #define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)
372 #define IRDMA_CQPSQ_QHASH_ADDR1_S 0
373 #define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)
375 #define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)
376 #define IRDMA_CQPSQ_QHASH_ADDR3_S 0
377 #define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)
378 #define IRDMA_CQPSQ_QHASH_WQEVALID_S 63
379 #define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
390 #define IRDMA_CQPSQ_STATS_WQEVALID_S 63
391 #define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
400 #define IRDMA_CQPSQ_STATS_INST_INDEX_S 0
401 #define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)
402 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0
403 #define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0)
404 #define IRDMA_CQPSQ_WS_WQEVALID_S 63
405 #define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
425 #define IRDMA_CQPSQ_WS_NODEID_S 0
426 #define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)
432 #define IRDMA_CQPSQ_UP_WQEVALID_S 63
433 #define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
440 #define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0
441 #define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)
444 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63
445 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
446 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0
447 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)
454 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0
455 #define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)
468 #define IRDMA_CQPHC_DCQCN_T_S 0
469 #define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)
473 #define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)
474 #define IRDMA_CQPHC_DCQCN_B_S 0
475 #define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)
481 #define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)
482 #define IRDMA_CQPHC_HW_MINVER_S 0
483 #define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)
485 #define IRDMA_CQPHC_HW_MAJVER_GEN_1 0
499 #define IRDMA_CQPHC_HMC_PROFILE_S 0
500 #define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)
504 #define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)
506 #define IRDMA_CQPHC_QPCTX_S 0
507 #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)
508 #define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0
509 #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)
510 #define IRDMA_CQ_DBSA_CQEIDX_S 0
511 #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)
512 #define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0
513 #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)
525 #define IRDMA_CCQ_OPRETVAL_S 0
526 #define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)
528 #define IRDMA_CQ_MINERR_S 0
529 #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)
543 #define IRDMA_CQ_VALID_S 63
544 #define IRDMA_CQ_VALID BIT_ULL(63)
550 #define IRDMA_CQ_UDSMAC_S 0
551 #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)
553 #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)
555 #define IRDMA_CQ_IMMDATA_S 0
558 #define IRDMA_CQ_IMMDATALOW32_S 0
559 #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)
561 #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)
562 #define IRDMACQ_PAYLDLEN_S 0
563 #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)
565 #define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32)
566 #define IRDMACQ_INVSTAG_S 0
567 #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)
571 #define IRDMACQ_UDSRCQPN_S 0
572 #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)
584 #define IRDMA_CEQE_CQCTX_S 0
585 #define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)
586 #define IRDMA_CEQE_VALID_S 63
587 #define IRDMA_CEQE_VALID BIT_ULL(63)
592 #define IRDMA_AEQE_QPCQID_LOW_S 0
593 #define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)
610 #define IRDMA_AEQE_VALID_S 63
611 #define IRDMA_AEQE_VALID BIT_ULL(63)
621 #define IRDMA_UDA_QPSQ_AHIDX_S 0
622 #define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)
623 #define IRDMA_UDA_QPSQ_VALID_S 63
624 #define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
635 #define IRDMA_UDA_PAYLOADLEN_S 0
636 #define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)
641 #define IRDMA_UDA_L3PROTO_S 0
642 #define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)
647 #define IRDMA_CQPSQ_BUFSIZE_S 0
648 #define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)
651 #define IRDMA_CQPSQ_WQEVALID_S 63
652 #define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
653 #define IRDMA_CQPSQ_TPHVAL_S 0
654 #define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)
674 #define IRDMA_CQPSQ_QP_QPID_S 0
675 #define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)
713 #define IRDMA_CQPSQ_CQ_CQSIZE_S 0
714 #define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)
715 #define IRDMA_CQPSQ_CQ_CQCTX_S 0
716 #define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)
717 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0
718 #define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)
736 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0
737 #define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
742 #define IRDMA_CQPSQ_STAG_STAGLEN_S 0
743 #define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)
744 #define IRDMA_CQPSQ_STAG_KEY_S 0
745 #define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)
775 #define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0
776 #define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)
778 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0
779 #define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
783 #define IRDMA_CQPSQ_MLM_TABLEIDX_S 0
784 #define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)
789 #define IRDMA_CQPSQ_MLM_MAC0_S 0
790 #define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)
801 #define IRDMA_CQPSQ_MAT_REACHMAX_S 0
802 #define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)
803 #define IRDMA_CQPSQ_MAT_MACADDR_S 0
804 #define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)
805 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0
806 #define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)
813 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0
814 #define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)
822 #define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)
824 /* Manage Push Page - MPP */
825 #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff
826 #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff
828 #define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0
829 #define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)
830 #define IRDMA_CQPSQ_MPP_PPIDX_S 0
831 #define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)
838 /* Upload Context - UCTX */
841 #define IRDMA_CQPSQ_UCTX_QPID_S 0
842 #define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)
850 #define IRDMA_CQPSQ_MHMC_VFIDX_S 0
851 #define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)
855 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0
856 #define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)
859 #define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0
860 #define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)
861 #define IRDMA_CQPSQ_CEQ_CEQID_S 0
862 #define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)
871 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0
872 #define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
873 #define IRDMA_CQPSQ_AEQ_AEQECNT_S 0
874 #define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)
881 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0
882 #define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)
884 #define IRDMA_COMMIT_FPM_QPCNT_S 0
885 #define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)
888 #define IRDMA_CQPSQ_CFPM_HMCFNID_S 0
889 #define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)
891 #define IRDMA_CQPSQ_FWQE_AECODE_S 0
892 #define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)
895 #define IRDMA_CQPSQ_FWQE_RQMNERR_S 0
896 #define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)
902 #define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)
903 #define IRDMA_CQPSQ_FWQE_QPID_S 0
904 #define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)
913 #define IRDMA_CQPSQ_MAPT_PORT_S 0
914 #define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)
917 #define IRDMA_CQPSQ_UPESD_SDCMD_S 0
918 #define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)
919 #define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0
920 #define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)
922 #define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)
923 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63
924 #define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
926 #define IRDMA_CQPSQ_UPESD_BM_PF 0
932 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0
933 #define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)
938 #define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0
939 #define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)
940 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0
941 #define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)
947 #define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001
948 #define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005
950 #define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000
951 #define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000
952 #define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001
953 #define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF
954 #define IRDMAQPC_DDP_VER_S 0
955 #define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)
1000 #define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)
1002 #define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)
1009 #define IRDMAQPC_TTL_S 0
1010 #define IRDMAQPC_TTL GENMASK_ULL(7, 0)
1024 #define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)
1026 #define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)
1027 #define IRDMAQPC_DESTIPADDR1_S 0
1028 #define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)
1030 #define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)
1031 #define IRDMAQPC_DESTIPADDR3_S 0
1032 #define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)
1040 #define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)
1041 #define IRDMAQPC_FLOWLABEL_S 0
1042 #define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)
1058 #define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)
1066 #define IRDMAQPC_QKEY GENMASK_ULL(63, 32)
1067 #define IRDMAQPC_DESTQP_S 0
1068 #define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)
1073 #define IRDMAQPC_TIMESTAMP_RECENT_S 0
1074 #define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)
1076 #define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)
1077 #define IRDMAQPC_SNDNXT_S 0
1078 #define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)
1081 #define IRDMAQPC_PSNNXT_S 0
1082 #define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)
1086 #define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)
1087 #define IRDMAQPC_RCVNXT_S 0
1088 #define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)
1089 #define IRDMAQPC_EPSN_S 0
1090 #define IRDMAQPC_EPSN GENMASK_ULL(23, 0)
1092 #define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)
1093 #define IRDMAQPC_SNDMAX_S 0
1094 #define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)
1096 #define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)
1097 #define IRDMAQPC_PSNMAX_S 0
1098 #define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)
1101 #define IRDMAQPC_SRTT_S 0
1102 #define IRDMAQPC_SRTT GENMASK_ULL(31, 0)
1104 #define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)
1105 #define IRDMAQPC_SSTHRESH_S 0
1106 #define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)
1108 #define IRDMAQPC_CWND GENMASK_ULL(63, 32)
1111 #define IRDMAQPC_SNDWL1_S 0
1112 #define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)
1114 #define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)
1118 #define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)
1119 #define IRDMAQPC_MAXSNDWND_S 0
1120 #define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)
1125 #define IRDMAQPC_TXCQNUM_S 0
1126 #define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)
1129 #define IRDMAQPC_STAT_INDEX_S 0
1130 #define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)
1132 #define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)
1133 #define IRDMAQPC_LASTBYTESENT_S 0
1134 #define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)
1136 #define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)
1137 #define IRDMAQPC_ORDSIZE_S 0
1138 #define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)
1166 #define IRDMAQPC_THIGH GENMASK_ULL(63, 52)
1169 #define IRDMAQPC_REMENDPOINTIDX_S 0
1170 #define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)
1188 #define IRDMAQPC_SQTPHVAL_S 0
1189 #define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)
1196 #define IRDMAQPC_LOCAL_IPADDR3_S 0
1197 #define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)
1199 #define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)
1200 #define IRDMAQPC_LOCAL_IPADDR1_S 0
1201 #define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)
1203 #define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)
1204 #define IRDMA_FW_VER_MINOR_S 0
1205 #define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)
1208 #define IRDMA_FEATURE_INFO_S 0
1209 #define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)
1213 #define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)
1239 #define IRDMAQPSQ_VALID_S 63
1240 #define IRDMAQPSQ_VALID BIT_ULL(63)
1244 #define IRDMAQPSQ_FRAG_VALID_S 63
1245 #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
1248 #define IRDMAQPSQ_FRAG_STAG_S 0
1249 #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)
1250 #define IRDMAQPSQ_GEN1_FRAG_LEN_S 0
1251 #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)
1253 #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)
1254 #define IRDMAQPSQ_REMSTAGINV_S 0
1255 #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)
1256 #define IRDMAQPSQ_DESTQKEY_S 0
1257 #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)
1260 #define IRDMAQPSQ_AHID_S 0
1261 #define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)
1273 #define IRDMAQPSQ_IMMDATA_S 0
1274 #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)
1275 #define IRDMAQPSQ_REMSTAG_S 0
1276 #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)
1291 #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)
1292 #define IRDMAQPSQ_MWSTAG_S 0
1293 #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)
1298 #define IRDMAQPSQ_LOCSTAG_S 0
1299 #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)
1301 #define IRDMAQPSQ_STAGKEY_S 0
1302 #define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)
1311 #define IRDMAQPSQ_STAGLEN_S 0
1312 #define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)
1314 #define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)
1315 #define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0
1316 #define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)
1318 #define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)
1343 #define IRDMA_QUERY_FPM_MAX_QPS_S 0
1344 #define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)
1345 #define IRDMA_QUERY_FPM_MAX_CQS_S 0
1346 #define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)
1347 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0
1348 #define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)
1352 #define IRDMA_QUERY_FPM_MAX_CEQS_S 0
1353 #define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)
1355 #define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)
1357 #define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)
1363 #define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)
1365 #define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)
1367 #define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)
1368 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0
1369 #define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0)
1373 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \
1378 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \
1383 (_ceq)->ceqe_base[_pos].buf \
1399 offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \
1400 (_cqe) = (_cq)->cq_base[offset].buf; \
1404 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1409 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \
1414 (_ring).head = 0; \
1415 (_ring).tail = 0; \
1428 (_retcode) = 0; \
1430 (_retcode) = -ENOSPC; \
1439 (_retcode) = 0; \
1441 (_retcode) = -ENOSPC; \
1450 (_retcode) = 0; \
1452 (_retcode) = -ENOSPC; \
1459 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \
1461 (_retcode) = 0; \
1463 (_retcode) = -ENOSPC; \
1483 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \
1488 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \
1493 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \
1498 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \
1503 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \
1507 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \
1511 (IRDMA_RING_USED_QUANTA(_ring) != 0) \
1516 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \
1521 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \
1526 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \
1536 IRDMA_ANY_PROTOCOL = 0,
1550 IRDMA_WS_OP_TYPE_NODE = 0,
1555 IRDMA_WS_RATE_LIMIT_FLAGS_VALID = 0x1,
1556 IRDMA_WS_NO_RDMA_RATE_LIMIT = 0x2,
1557 IRDMA_WS_LEAF_NODE_IS_PART_GROUP = 0x4,
1558 IRDMA_WS_TREE_RATE_LIMITING = 0x8,
1559 IRDMA_WS_PACING_CONTROL = 0x10,
1563 IRDMA_ADD_NODE = 0,
1568 enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),
1569 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),
1570 IRDMA_Q2_ALIGNMENT_M = (256 - 1),
1571 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),
1572 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),
1573 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),
1574 IRDMA_SHADOWAREA_M = (128 - 1),
1575 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),
1576 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),
1580 IRDMA_CQP_ALIGNMENT = 0x200,
1581 IRDMA_AEQ_ALIGNMENT = 0x100,
1582 IRDMA_CEQ_ALIGNMENT = 0x100,
1583 IRDMA_CQ0_ALIGNMENT = 0x100,
1584 IRDMA_SD_BUF_ALIGNMENT = 0x80,
1585 IRDMA_FEATURE_BUF_ALIGNMENT = 0x10,
1589 * set_64bit_val - set 64 bit value to hw wqe
1600 * set_32bit_val - set 32 bit value to hw wqe
1611 * get_64bit_val - read 64 bit value from wqe
1622 * get_32bit_val - read 32 bit value from wqe