2 /*-
3  * SPDX-License-Identifier: BSD-2-Clause
5  * Copyright (c) 2004-2006
99 #define IPW_STATE_PS_ENTER		0x0040	/* entered power-save mode */
100 #define IPW_STATE_PS_EXIT		0x0080	/* exited power-save mode */
159 #define	IPW_RSSI_TO_DBM	(-98)		/* XXX fixed nf to convert dBm */
305 /* EEPROM = Electrically Erasable Programmable Read-Only Memory */
326 #define CSR_READ_1(sc, reg)						\  argument
327 	bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
329 #define CSR_READ_2(sc, reg)						\  argument
330 	bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
332 #define CSR_READ_4(sc, reg)						\  argument
333 	bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
335 #define CSR_WRITE_1(sc, reg, val)					\  argument
336 	bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
338 #define CSR_WRITE_2(sc, reg, val)					\  argument
339 	bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
341 #define CSR_WRITE_4(sc, reg, val)					\  argument
342 	bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
344 #define CSR_WRITE_MULTI_1(sc, reg, buf, len)				\  argument
345 	bus_space_write_multi_1((sc)->sc_st, (sc)->sc_sh, (reg), 	\
351 #define MEM_READ_1(sc, addr)						\  argument
352 	(CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)),		\
355 #define MEM_READ_4(sc, addr)						\  argument
356 	(CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr)),		\
359 #define MEM_WRITE_1(sc, addr, val) do {					\  argument
360 	CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr));		\
364 #define MEM_WRITE_2(sc, addr, val) do {					\  argument
365 	CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr));		\
369 #define MEM_WRITE_4(sc, addr, val) do {					\  argument
370 	CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr));		\
374 #define MEM_WRITE_MULTI_1(sc, addr, buf, len) do {			\  argument
375 	CSR_WRITE_4((sc), IPW_CSR_INDIRECT_ADDR, (addr));		\