Lines Matching +full:0 +full:x220000

84 #define DPRINTF(x)	do { if (ipw_debug > 0) printf x; } while (0)
85 #define DPRINTFN(n, x) do { if (ipw_debug >= (n)) printf x; } while (0)
86 int ipw_debug = 0;
87 SYSCTL_INT(_debug, OID_AUTO, ipw, CTLFLAG_RW, &ipw_debug, 0, "ipw debug level");
104 { 0x8086, 0x1043, "Intel(R) PRO/Wireless 2100 MiniPCI" },
106 { 0, 0, NULL }
157 #if 0
235 TASK_INIT(&sc->sc_init_task, 0, ipw_init_task, sc); in ipw_attach()
236 callout_init_mtx(&sc->sc_wdtimer, &sc->sc_mtx, 0); in ipw_attach()
238 pci_write_config(dev, 0x41, 0, 1); in ipw_attach()
243 i = PCIR_BAR(0); in ipw_attach()
253 i = 0; in ipw_attach()
261 if (ipw_reset(sc) != 0) { in ipw_attach()
266 if (ipw_dma_alloc(sc) != 0) { in ipw_attach()
287 val = ipw_read_prom_word(sc, IPW_EEPROM_MAC + 0); in ipw_attach()
288 ic->ic_macaddr[0] = val >> 8; in ipw_attach()
289 ic->ic_macaddr[1] = val & 0xff; in ipw_attach()
292 ic->ic_macaddr[3] = val & 0xff; in ipw_attach()
295 ic->ic_macaddr[5] = val & 0xff; in ipw_attach()
329 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, in ipw_attach()
331 "radio transmitter switch state (0=off, 1=on)"); in ipw_attach()
335 CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_NEEDGIANT, sc, 0, in ipw_attach()
343 if (error != 0) { in ipw_attach()
351 return 0; in ipw_attach()
394 return 0; in ipw_detach()
433 strcmp(sc->sc_firmware->name, imagename) != 0) { in ipw_vap_create()
497 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, in ipw_dma_alloc()
500 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->parent_dmat); in ipw_dma_alloc()
501 if (error != 0) { in ipw_dma_alloc()
509 error = bus_dma_tag_create(sc->parent_dmat, 4, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
510 BUS_SPACE_MAXADDR, NULL, NULL, IPW_TBD_SZ, 1, IPW_TBD_SZ, 0, NULL, in ipw_dma_alloc()
512 if (error != 0) { in ipw_dma_alloc()
519 if (error != 0) { in ipw_dma_alloc()
526 IPW_TBD_SZ, ipw_dma_map_addr, &sc->tbd_phys, 0); in ipw_dma_alloc()
527 if (error != 0) { in ipw_dma_alloc()
535 error = bus_dma_tag_create(sc->parent_dmat, 4, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
536 BUS_SPACE_MAXADDR, NULL, NULL, IPW_RBD_SZ, 1, IPW_RBD_SZ, 0, NULL, in ipw_dma_alloc()
538 if (error != 0) { in ipw_dma_alloc()
545 if (error != 0) { in ipw_dma_alloc()
552 IPW_RBD_SZ, ipw_dma_map_addr, &sc->rbd_phys, 0); in ipw_dma_alloc()
553 if (error != 0) { in ipw_dma_alloc()
561 error = bus_dma_tag_create(sc->parent_dmat, 4, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
562 BUS_SPACE_MAXADDR, NULL, NULL, IPW_STATUS_SZ, 1, IPW_STATUS_SZ, 0, in ipw_dma_alloc()
564 if (error != 0) { in ipw_dma_alloc()
572 if (error != 0) { in ipw_dma_alloc()
580 0); in ipw_dma_alloc()
581 if (error != 0) { in ipw_dma_alloc()
590 error = bus_dma_tag_create(sc->parent_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
592 sizeof (struct ipw_cmd), 0, NULL, NULL, &sc->cmd_dmat); in ipw_dma_alloc()
593 if (error != 0) { in ipw_dma_alloc()
598 error = bus_dmamap_create(sc->cmd_dmat, 0, &sc->cmd_map); in ipw_dma_alloc()
599 if (error != 0) { in ipw_dma_alloc()
608 error = bus_dma_tag_create(sc->parent_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
610 sizeof (struct ipw_hdr), 0, NULL, NULL, &sc->hdr_dmat); in ipw_dma_alloc()
611 if (error != 0) { in ipw_dma_alloc()
617 for (i = 0; i < IPW_NDATA; i++) { in ipw_dma_alloc()
619 error = bus_dmamap_create(sc->hdr_dmat, 0, &shdr->map); in ipw_dma_alloc()
620 if (error != 0) { in ipw_dma_alloc()
631 error = bus_dma_tag_create(sc->parent_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
632 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IPW_MAX_NSEG, MCLBYTES, 0, in ipw_dma_alloc()
634 if (error != 0) { in ipw_dma_alloc()
640 for (i = 0; i < IPW_NDATA; i++) { in ipw_dma_alloc()
642 error = bus_dmamap_create(sc->txbuf_dmat, 0, &sbuf->map); in ipw_dma_alloc()
643 if (error != 0) { in ipw_dma_alloc()
654 for (i = 0; i < IPW_NTBD; i++) { in ipw_dma_alloc()
663 error = bus_dma_tag_create(sc->parent_dmat, 1, 0, BUS_SPACE_MAXADDR_32BIT, in ipw_dma_alloc()
664 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, MCLBYTES, 0, NULL, in ipw_dma_alloc()
666 if (error != 0) { in ipw_dma_alloc()
671 for (i = 0; i < IPW_NRBD; i++) { in ipw_dma_alloc()
684 error = bus_dmamap_create(sc->rxbuf_dmat, 0, &sbuf->map); in ipw_dma_alloc()
685 if (error != 0) { in ipw_dma_alloc()
693 &physaddr, 0); in ipw_dma_alloc()
694 if (error != 0) { in ipw_dma_alloc()
708 return 0; in ipw_dma_alloc()
748 for (i = 0; i < IPW_NTBD; i++) in ipw_release()
757 for (i = 0; i < IPW_NDATA; i++) in ipw_release()
763 for (i = 0; i < IPW_NDATA; i++) { in ipw_release()
771 for (i = 0; i < IPW_NRBD; i++) { in ipw_release()
792 return 0; in ipw_shutdown()
802 return 0; in ipw_suspend()
811 pci_write_config(dev, 0x41, 0, 1); in ipw_resume()
814 return 0; in ipw_resume()
826 return 0; in ipw_cvtrate()
842 ipw_read_table1(sc, IPW_INFO_CURRENT_TX_RATE) & 0xf); in ipw_media_status()
854 DPRINTF(("%s: %s -> %s flags 0x%x\n", __func__, in ipw_newstate()
920 IPW_EEPROM_CTL(sc, 0); in ipw_read_prom_word()
936 for (n = 7; n >= 0; n--) { in ipw_read_prom_word()
946 val = 0; in ipw_read_prom_word()
947 for (n = 15; n >= 0; n--) { in ipw_read_prom_word()
954 IPW_EEPROM_CTL(sc, 0); in ipw_read_prom_word()
958 IPW_EEPROM_CTL(sc, 0); in ipw_read_prom_word()
970 if ((val = ipw_read_prom_word(sc, IPW_EEPROM_CHANNEL_LIST)) == 0) in ipw_read_chanmask()
971 val = 0x7ff; /* default to channels 1-11 */ in ipw_read_chanmask()
1009 DPRINTFN(2, ("Association succeeded (%s flags 0x%x)\n", in ipw_rx_newstate_intr()
1012 if ((sc->flags & IPW_FLAG_ASSOCIATING) == 0) { in ipw_rx_newstate_intr()
1013 DPRINTF(("Unexpected association (%s, flags 0x%x)\n", in ipw_rx_newstate_intr()
1022 DPRINTFN(3, ("Scanning (%s flags 0x%x)\n", in ipw_rx_newstate_intr()
1046 DPRINTFN(3, ("Scan complete (%s flags 0x%x)\n", in ipw_rx_newstate_intr()
1057 sc->sc_scan_timer = 0; in ipw_rx_newstate_intr()
1062 DPRINTFN(2, ("Association lost (%s flags 0x%x)\n", in ipw_rx_newstate_intr()
1076 DPRINTFN(2, ("Firmware disabled (%s flags 0x%x)\n", in ipw_rx_newstate_intr()
1082 ieee80211_notify_radio(ic, 0); in ipw_rx_newstate_intr()
1088 DPRINTFN(2, ("%s: unhandled state %u %s flags 0x%x\n", in ipw_rx_newstate_intr()
1125 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; in ipw_fix_channel()
1144 ieee80211_ieee2mhz(frm[2], 0), in ipw_fix_channel()
1147 c = &ic->ic_channels[0]; in ipw_fix_channel()
1189 MCLBYTES, ipw_dma_map_addr, &physaddr, 0); in ipw_rx_data_intr()
1190 if (error != 0) { in ipw_rx_data_intr()
1196 &physaddr, 0); in ipw_rx_data_intr()
1197 if (error != 0) { in ipw_rx_data_intr()
1220 tap->wr_flags = 0; in ipw_rx_data_intr()
1260 switch (le16toh(status->code) & 0xf) { in ipw_rx_intr()
1275 DPRINTFN(2, ("notification status, len %u flags 0x%x\n", in ipw_rx_intr()
1289 sbd->bd->flags = 0; in ipw_rx_intr()
1295 sc->rxcur = (r == 0) ? IPW_NRBD - 1 : r - 1; in ipw_rx_intr()
1326 ieee80211_tx_complete(sbuf->ni, sbuf->m, 0/*XXX*/); in ipw_release_sbd()
1328 sc->sc_tx_timer = 0; in ipw_release_sbd()
1353 sc->txold = (r == 0) ? IPW_NTBD - 1 : r - 1; in ipw_tx_intr()
1382 if (r == 0 || r == 0xffffffff) in ipw_intr()
1386 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_intr()
1414 if (error != 0) in ipw_dma_map_addr()
1419 *(bus_addr_t *)arg = segs[0].ds_addr; in ipw_dma_map_addr()
1461 for (i = 0; i < nitems(cmds); i++) in ipw_cmdname()
1490 sizeof (struct ipw_cmd), ipw_dma_map_addr, &physaddr, 0); in ipw_cmd()
1491 if (error != 0) { in ipw_cmd()
1498 sc->cmd.subtype = 0; in ipw_cmd()
1500 sc->cmd.seq = 0; in ipw_cmd()
1516 0, 0, len); in ipw_cmd()
1518 if (ipw_debug >= 9 && len > 0) { in ipw_cmd()
1519 printf(" data: 0x"); in ipw_cmd()
1533 error = msleep(sc, &sc->sc_mtx, 0, "ipwcmd", hz); in ipw_cmd()
1534 if (error != 0) { in ipw_cmd()
1540 return (0); in ipw_cmd()
1573 tap->wt_flags = 0; in ipw_tx_start()
1583 shdr->hdr.subtype = 0; in ipw_tx_start()
1584 shdr->hdr.encrypted = (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) ? 1 : 0; in ipw_tx_start()
1585 shdr->hdr.encrypt = 0; in ipw_tx_start()
1586 shdr->hdr.keyidx = 0; in ipw_tx_start()
1587 shdr->hdr.keysz = 0; in ipw_tx_start()
1588 shdr->hdr.fragmentsz = 0; in ipw_tx_start()
1599 &nsegs, 0); in ipw_tx_start()
1600 if (error != 0 && error != EFBIG) { in ipw_tx_start()
1606 if (error != 0) { in ipw_tx_start()
1617 segs, &nsegs, 0); in ipw_tx_start()
1618 if (error != 0) { in ipw_tx_start()
1627 sizeof (struct ipw_hdr), ipw_dma_map_addr, &physaddr, 0); in ipw_tx_start()
1628 if (error != 0) { in ipw_tx_start()
1658 for (i = 0; i < nsegs; i++) { in ipw_tx_start()
1663 sbd->bd->nfrag = 0; in ipw_tx_start()
1687 return 0; in ipw_tx_start()
1697 return 0; in ipw_raw_xmit()
1707 if ((sc->flags & IPW_FLAG_RUNNING) == 0) { in ipw_transmit()
1718 return (0); in ipw_transmit()
1732 if (ipw_tx_start(sc, m, ni) != 0) { in ipw_start()
1751 if (sc->sc_tx_timer > 0) { in ipw_watchdog()
1752 if (--sc->sc_tx_timer == 0) { in ipw_watchdog()
1758 if (sc->sc_scan_timer > 0) { in ipw_watchdog()
1759 if (--sc->sc_scan_timer == 0) { in ipw_watchdog()
1778 int startall = 0; in ipw_parent()
1781 if (ic->ic_nrunning > 0) { in ipw_parent()
1800 CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0); in ipw_stop_master()
1803 for (ntries = 0; ntries < 50; ntries++) { in ipw_stop_master()
1831 for (ntries = 0; ntries < 1000; ntries++) { in ipw_reset()
1847 return 0; in ipw_reset()
1856 for (i = 0; i < 100; i++) { in ipw_waitfordisable()
1858 return 0; in ipw_waitfordisable()
1860 if (error == 0 || error != EWOULDBLOCK) in ipw_waitfordisable()
1861 return 0; in ipw_waitfordisable()
1873 if ((sc->flags & IPW_FLAG_ENABLED) == 0) { in ipw_enable()
1875 error = ipw_cmd(sc, IPW_CMD_ENABLE, NULL, 0); in ipw_enable()
1876 if (error != 0) in ipw_enable()
1878 error = ipw_waitfordisable(sc, 0); in ipw_enable()
1879 if (error != 0) in ipw_enable()
1883 return 0; in ipw_enable()
1893 error = ipw_cmd(sc, IPW_CMD_DISABLE, NULL, 0); in ipw_disable()
1894 if (error != 0) in ipw_disable()
1897 if (error != 0) in ipw_disable()
1901 return 0; in ipw_disable()
1912 MEM_WRITE_4(sc, 0x3000e0, 0x80000000); in ipw_load_ucode()
1913 CSR_WRITE_4(sc, IPW_CSR_RST, 0); in ipw_load_ucode()
1915 MEM_WRITE_2(sc, 0x220000, 0x0703); in ipw_load_ucode()
1916 MEM_WRITE_2(sc, 0x220000, 0x0707); in ipw_load_ucode()
1918 MEM_WRITE_1(sc, 0x210014, 0x72); in ipw_load_ucode()
1919 MEM_WRITE_1(sc, 0x210014, 0x72); in ipw_load_ucode()
1921 MEM_WRITE_1(sc, 0x210000, 0x40); in ipw_load_ucode()
1922 MEM_WRITE_1(sc, 0x210000, 0x00); in ipw_load_ucode()
1923 MEM_WRITE_1(sc, 0x210000, 0x40); in ipw_load_ucode()
1925 MEM_WRITE_MULTI_1(sc, 0x210010, uc, size); in ipw_load_ucode()
1927 MEM_WRITE_1(sc, 0x210000, 0x00); in ipw_load_ucode()
1928 MEM_WRITE_1(sc, 0x210000, 0x00); in ipw_load_ucode()
1929 MEM_WRITE_1(sc, 0x210000, 0x80); in ipw_load_ucode()
1931 MEM_WRITE_2(sc, 0x220000, 0x0703); in ipw_load_ucode()
1932 MEM_WRITE_2(sc, 0x220000, 0x0707); in ipw_load_ucode()
1934 MEM_WRITE_1(sc, 0x210014, 0x72); in ipw_load_ucode()
1935 MEM_WRITE_1(sc, 0x210014, 0x72); in ipw_load_ucode()
1937 MEM_WRITE_1(sc, 0x210000, 0x00); in ipw_load_ucode()
1938 MEM_WRITE_1(sc, 0x210000, 0x80); in ipw_load_ucode()
1940 for (ntries = 0; ntries < 10; ntries++) { in ipw_load_ucode()
1941 if (MEM_READ_1(sc, 0x210000) & 1) in ipw_load_ucode()
1951 MEM_WRITE_4(sc, 0x3000e0, 0); in ipw_load_ucode()
1953 return 0; in ipw_load_ucode()
1957 #define GETLE32(p) ((p)[0] | (p)[1] << 8 | (p)[2] << 16 | (p)[3] << 24)
1958 #define GETLE16(p) ((p)[0] | (p)[1] << 8)
1984 CSR_WRITE_4(sc, IPW_CSR_RST, 0); in ipw_load_firmware()
1990 if ((error = msleep(sc, &sc->sc_mtx, 0, "ipwinit", hz)) != 0) { in ipw_load_firmware()
2000 return 0; in ipw_load_firmware()
2012 for (i = 0; i < IEEE80211_WEP_NKID; i++) { in ipw_setwepkeys()
2021 memset(wepkey.key, 0, sizeof wepkey.key); in ipw_setwepkeys()
2027 if (error != 0) in ipw_setwepkeys()
2030 return 0; in ipw_setwepkeys()
2038 memset(&wpaie, 0, sizeof(wpaie)); in ipw_setwpaie()
2051 if (bssid == NULL || bcmp(bssid, zerobssid, IEEE80211_ADDR_LEN) == 0) { in ipw_setbssid()
2053 return ipw_cmd(sc, IPW_CMD_SET_MANDATORY_BSSID, NULL, 0); in ipw_setbssid()
2064 if (ssidlen == 0) { in ipw_setssid()
2079 if (ipw_debug > 0) { in ipw_setssid()
2094 DPRINTF(("Scan options: mask 0x%x flags 0x%x\n", chanmask, flags)); in ipw_setscanopts()
2106 DPRINTF(("%s: flags 0x%x\n", __func__, sc->flags)); in ipw_scan()
2113 error = ipw_setscanopts(sc, 0x3fff, IPW_SCAN_DO_NOT_ASSOCIATE); in ipw_scan()
2114 if (error != 0) in ipw_scan()
2122 error = ipw_setssid(sc, NULL, 0); in ipw_scan()
2123 if (error != 0) in ipw_scan()
2133 params = 0; /* XXX? */ in ipw_scan()
2139 if (error != 0) { in ipw_scan()
2156 if (error == 0) in ipw_setchannel()
2172 if (error != 0) in ipw_assoc()
2175 memset(&security, 0, sizeof security); in ipw_assoc()
2182 if (error != 0) in ipw_assoc()
2188 if (error != 0) in ipw_assoc()
2194 if (error != 0) in ipw_assoc()
2199 if (error != 0) in ipw_assoc()
2208 if (error != 0) in ipw_assoc()
2213 data = htole32((vap->iv_flags & IEEE80211_F_PRIVACY) ? IPW_WEPON : 0); in ipw_assoc()
2214 DPRINTF(("Setting wep flags to 0x%x\n", le32toh(data))); in ipw_assoc()
2216 if (error != 0) in ipw_assoc()
2220 if (error != 0) in ipw_assoc()
2224 if (error != 0) in ipw_assoc()
2230 if (error != 0) in ipw_assoc()
2235 if (error != 0) in ipw_assoc()
2241 1<<(ieee80211_chan2ieee(ic, ni->ni_chan)-1), 0); in ipw_assoc()
2242 if (error != 0) in ipw_assoc()
2246 if (error == 0) in ipw_assoc()
2311 DPRINTF(("%s: state %s flags 0x%x\n", __func__, in ipw_init_locked()
2325 if (ipw_reset(sc) != 0) { in ipw_init_locked()
2340 if (ipw_load_ucode(sc, fw, le32toh(hdr->ucodesz)) != 0) { in ipw_init_locked()
2351 sc->txcur = 0; in ipw_init_locked()
2357 CSR_WRITE_4(sc, IPW_CSR_TX_READ, 0); in ipw_init_locked()
2362 CSR_WRITE_4(sc, IPW_CSR_RX_READ, 0); in ipw_init_locked()
2368 if (ipw_load_firmware(sc, fw, le32toh(hdr->mainsz)) != 0) { in ipw_init_locked()
2379 ipw_write_table1(sc, IPW_INFO_LOCK, 0); in ipw_init_locked()
2381 if (ipw_config(sc) != 0) { in ipw_init_locked()
2405 if (error != 0) in ipw_config()
2427 if (error != 0) in ipw_config()
2433 if (error != 0) in ipw_config()
2444 if (ic->ic_promisc > 0) in ipw_config()
2446 config.bss_chan = htole32(0x3fff); /* channels 1-14 */ in ipw_config()
2447 config.ibss_chan = htole32(0x7ff); /* channels 1-11 */ in ipw_config()
2448 DPRINTF(("Setting configuration to 0x%x\n", le32toh(config.flags))); in ipw_config()
2450 if (error != 0) in ipw_config()
2453 data = htole32(0xf); /* 1, 2, 5.5, 11 */ in ipw_config()
2454 DPRINTF(("Setting basic tx rates to 0x%x\n", le32toh(data))); in ipw_config()
2456 if (error != 0) in ipw_config()
2460 DPRINTF(("Setting msdu tx rates to 0x%x\n", le32toh(data))); in ipw_config()
2462 if (error != 0) in ipw_config()
2466 DPRINTF(("Setting tx rates to 0x%x\n", le32toh(data))); in ipw_config()
2468 if (error != 0) in ipw_config()
2474 if (error != 0) in ipw_config()
2482 if (error != 0) in ipw_config()
2486 return 0; in ipw_config()
2514 for (i = 0; i < IPW_NTBD; i++) in ipw_stop_locked()
2517 sc->sc_tx_timer = 0; in ipw_stop_locked()
2527 memset(buf, 0, sizeof buf); in ipw_sysctl_stats()
2565 #if 0
2578 size = info & 0xffff;
2589 return 0;
2596 for (; count > 0; offset++, datap++, count--) {
2607 for (; count > 0; offset++, datap++, count--) { in ipw_write_mem_1()
2631 memset(bands, 0, sizeof(bands)); in ipw_getradiocaps()
2637 i, 0, 0, 0, bands); in ipw_getradiocaps()