126 #define WR(sc, reg, val) bus_write_4((sc)->regs_res, reg, val)  macro
182 		WR(sc, GENI_M_IRQ_CLEAR, (1<<26));  in geniiic_intr()
188 		WR(sc, GENI_M_IRQ_EN_CLEAR, (1<<0));  in geniiic_intr()
189 		WR(sc, GENI_M_IRQ_EN_CLEAR, (1<<26));  in geniiic_intr()
190 		WR(sc, GENI_M_IRQ_CLEAR, (1<<0));  in geniiic_intr()
200 		WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_intr()
201 		WR(sc, GENI_M_IRQ_CLEAR, m_status);  in geniiic_intr()
214 		WR(sc, GENI_DMA_TX_IRQ_EN_CLR, RD(sc, GENI_DMA_TX_IRQ_STAT));  in geniiic_intr()
215 		WR(sc, GENI_DMA_TX_IRQ_CLR, RD(sc, GENI_DMA_TX_IRQ_STAT));  in geniiic_intr()
216 		WR(sc, GENI_DMA_RX_IRQ_EN_CLR, RD(sc, GENI_DMA_RX_IRQ_STAT));  in geniiic_intr()
217 		WR(sc, GENI_DMA_RX_IRQ_CLR, RD(sc, GENI_DMA_RX_IRQ_STAT));  in geniiic_intr()
246 	WR(sc, GENI_M_IRQ_CLEAR, istatus);  in geniiic_read()
252 	WR(sc, GENI_I2C_RX_TRANS_LEN, len);  in geniiic_read()
264 	WR(sc, GENI_RX_WATERMARK_REG, sc->rx_fifo_size - 4);  in geniiic_read()
267 	WR(sc, GENI_M_IRQ_EN, (1<<0) | (1<<26));  in geniiic_read()
270 	WR(sc, GENI_IRQ_EN, (1<<2));  in geniiic_read()
272 	WR(sc, GENI_M_CMD0, cmd);  in geniiic_read()
292 		WR(sc, GENI_M_CMD_CTRL_REG, (1<<2));  in geniiic_read()
294 		WR(sc, GENI_IRQ_EN, 0);  in geniiic_read()
342 	WR(sc, GENI_M_IRQ_CLEAR, status);  in geniiic_write()
344 	WR(sc, GENI_I2C_TX_TRANS_LEN, len);  in geniiic_write()
356 	WR(sc, GENI_M_CMD0, cmd);  in geniiic_write()
365 			WR(sc, GENI_TX_FIFOn, data);  in geniiic_write()
451 	WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_reset()
452 	WR(sc, GENI_M_IRQ_CLEAR, ~0);  in geniiic_reset()
453 	WR(sc, GENI_DMA_TX_IRQ_EN_CLR, ~0);  in geniiic_reset()
454 	WR(sc, GENI_DMA_TX_IRQ_CLR, ~0);  in geniiic_reset()
455 	WR(sc, GENI_DMA_RX_IRQ_EN_CLR, ~0);  in geniiic_reset()
456 	WR(sc, GENI_DMA_RX_IRQ_CLR, ~0);  in geniiic_reset()
459 	WR(sc, GENI_M_CMD_CTRL_REG, (1<<1));  in geniiic_reset()
461 	WR(sc, GENI_DMA_RX_FSM_RST, 1);  in geniiic_reset()
469 	WR(sc, GENI_DMA_TX_FSM_RST, 1);  in geniiic_reset()
559 	WR(sc, GENI_M_IRQ_EN, 0);  in geniiic_detach()