Lines Matching +full:rx +full:- +full:watermark
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
11 #define IGC_CTRL 0x00000 /* Device Control - RW */
12 #define IGC_STATUS 0x00008 /* Device Status - RO */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
18 #define IGC_MDIC 0x00020 /* MDI Control - RW */
19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */
20 #define IGC_FCAL 0x00028 /* Flow Control Address Low - RW */
21 #define IGC_FCAH 0x0002C /* Flow Control Address High -RW */
26 #define IGC_FCT 0x00030 /* Flow Control Type - RW */
27 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
28 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
29 #define IGC_ICR 0x01500 /* Intr Cause Read - RC/W1C */
30 #define IGC_ICS 0x01504 /* Intr Cause Set - WO */
31 #define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */
32 #define IGC_IMC 0x0150C /* Intr Mask Clear - WO */
33 #define IGC_IAM 0x01510 /* Intr Ack Auto Mask- RW */
34 #define IGC_RCTL 0x00100 /* Rx Control - RW */
35 #define IGC_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
36 #define IGC_TXCW 0x00178 /* Tx Configuration Word - RW */
37 #define IGC_RXCW 0x00180 /* Rx Configuration Word - RO */
38 #define IGC_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
40 #define IGC_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
41 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
42 #define IGC_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
43 #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
44 #define IGC_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
45 #define IGC_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
46 #define IGC_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
47 #define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
48 #define IGC_TCTL 0x00400 /* Tx Control - RW */
49 #define IGC_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
50 #define IGC_TIPG 0x00410 /* Tx Inter-packet gap -RW */
51 #define IGC_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
52 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */
57 #define IGC_PBA 0x01000 /* Packet Buffer Allocation - RW */
63 #define IGC_WDSTP 0x01040 /* Watchdog Setup - RW */
64 #define IGC_SWDSTS 0x01044 /* SW Device Status - RW */
65 #define IGC_FRTIMER 0x01048 /* Free Running Timer - RW */
66 #define IGC_TCPTIMER 0x0104C /* TCP Timer - RW */
67 #define IGC_ERT 0x02008 /* Early Rx Threshold - RW */
68 #define IGC_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
69 #define IGC_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
70 #define IGC_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
71 #define IGC_RDFH 0x02410 /* Rx Data FIFO Head - RW */
72 #define IGC_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
73 #define IGC_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
74 #define IGC_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
75 #define IGC_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
76 #define IGC_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
77 #define IGC_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
78 /* Split and Replication Rx Control - RW */
79 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
80 /* Shadow Ram Write Register - RW */
129 #define IGC_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
130 #define IGC_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
134 (0x054E0 + ((_i - 16) * 8)))
136 (0x054E4 + ((_i - 16) * 8)))
147 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
148 #define IGC_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
149 #define IGC_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
151 #define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
152 #define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
153 #define IGC_MPC 0x04010 /* Missed Packet Count - R/clr */
154 #define IGC_SCC 0x04014 /* Single Collision Count - R/clr */
155 #define IGC_ECOL 0x04018 /* Excessive Collision Count - R/clr */
156 #define IGC_MCC 0x0401C /* Multiple Collision Count - R/clr */
157 #define IGC_LATECOL 0x04020 /* Late Collision Count - R/clr */
158 #define IGC_COLC 0x04028 /* Collision Count - R/clr */
159 #define IGC_RERC 0x0402C /* Receive Error Count - R/clr */
160 #define IGC_DC 0x04030 /* Defer Count - R/clr */
161 #define IGC_TNCRS 0x04034 /* Tx-No CRS - R/clr */
162 #define IGC_HTDPMC 0x0403C /* Host Transmit Discarded by MAC - R/clr */
163 #define IGC_RLEC 0x04040 /* Receive Length Error Count - R/clr */
164 #define IGC_XONRXC 0x04048 /* XON Rx Count - R/clr */
165 #define IGC_XONTXC 0x0404C /* XON Tx Count - R/clr */
166 #define IGC_XOFFRXC 0x04050 /* XOFF Rx Count - R/clr */
167 #define IGC_XOFFTXC 0x04054 /* XOFF Tx Count - R/clr */
168 #define IGC_FCRUC 0x04058 /* Flow Control Rx Unsupported Count- R/clr */
169 #define IGC_PRC64 0x0405C /* Packets Rx (64 bytes) - R/clr */
170 #define IGC_PRC127 0x04060 /* Packets Rx (65-127 bytes) - R/clr */
171 #define IGC_PRC255 0x04064 /* Packets Rx (128-255 bytes) - R/clr */
172 #define IGC_PRC511 0x04068 /* Packets Rx (255-511 bytes) - R/clr */
173 #define IGC_PRC1023 0x0406C /* Packets Rx (512-1023 bytes) - R/clr */
174 #define IGC_PRC1522 0x04070 /* Packets Rx (1024-1522 bytes) - R/clr */
175 #define IGC_GPRC 0x04074 /* Good Packets Rx Count - R/clr */
176 #define IGC_BPRC 0x04078 /* Broadcast Packets Rx Count - R/clr */
177 #define IGC_MPRC 0x0407C /* Multicast Packets Rx Count - R/clr */
178 #define IGC_GPTC 0x04080 /* Good Packets Tx Count - R/clr */
179 #define IGC_GORCL 0x04088 /* Good Octets Rx Count Low - R/clr */
180 #define IGC_GORCH 0x0408C /* Good Octets Rx Count High - R/clr */
181 #define IGC_GOTCL 0x04090 /* Good Octets Tx Count Low - R/clr */
182 #define IGC_GOTCH 0x04094 /* Good Octets Tx Count High - R/clr */
183 #define IGC_RNBC 0x040A0 /* Rx No Buffers Count - R/clr */
184 #define IGC_RUC 0x040A4 /* Rx Undersize Count - R/clr */
185 #define IGC_RFC 0x040A8 /* Rx Fragment Count - R/clr */
186 #define IGC_ROC 0x040AC /* Rx Oversize Count - R/clr */
187 #define IGC_RJC 0x040B0 /* Rx Jabber Count - R/clr */
188 #define IGC_MGTPRC 0x040B4 /* Management Packets Rx Count - R/clr */
189 #define IGC_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
190 #define IGC_MGTPTC 0x040BC /* Management Packets Tx Count - R/clr */
191 #define IGC_TORL 0x040C0 /* Total Octets Rx Low - R/clr */
192 #define IGC_TORH 0x040C4 /* Total Octets Rx High - R/clr */
193 #define IGC_TOTL 0x040C8 /* Total Octets Tx Low - R/clr */
194 #define IGC_TOTH 0x040CC /* Total Octets Tx High - R/clr */
195 #define IGC_TPR 0x040D0 /* Total Packets Rx - R/clr */
196 #define IGC_TPT 0x040D4 /* Total Packets Tx - R/clr */
197 #define IGC_PTC64 0x040D8 /* Packets Tx (64 bytes) - R/clr */
198 #define IGC_PTC127 0x040DC /* Packets Tx (65-127 bytes) - R/clr */
199 #define IGC_PTC255 0x040E0 /* Packets Tx (128-255 bytes) - R/clr */
200 #define IGC_PTC511 0x040E4 /* Packets Tx (256-511 bytes) - R/clr */
201 #define IGC_PTC1023 0x040E8 /* Packets Tx (512-1023 bytes) - R/clr */
202 #define IGC_PTC1522 0x040EC /* Packets Tx (1024-1522 Bytes) - R/clr */
203 #define IGC_MPTC 0x040F0 /* Multicast Packets Tx Count - R/clr */
204 #define IGC_BPTC 0x040F4 /* Broadcast Packets Tx Count - R/clr */
205 #define IGC_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */
207 #define IGC_RXDMTC 0x04120 /* Rx Descriptor Minimum Threshold Count */
223 #define IGC_PCS_ANADV 0x04218 /* AN advertisement - RW */
224 #define IGC_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
225 #define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */
226 #define IGC_RLPML 0x05004 /* Rx Long Packet Max Length */
228 #define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */
229 #define IGC_RA 0x05400 /* Receive Address - RW Array */
230 #define IGC_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
231 #define IGC_WUC 0x05800 /* Wakeup Control - RW */
232 #define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */
233 #define IGC_WUS 0x05810 /* Wakeup Status - RO */
235 #define IGC_MANC 0x05820 /* Management Control - RW */
236 #define IGC_IPAV 0x05838 /* IP Address Valid - RW */
237 #define IGC_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
238 #define IGC_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
239 #define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */
240 #define IGC_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
241 #define IGC_WUPM_EXT 0x0B800 /* Wakeup Packet Memory Extended - RO Array */
242 #define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Extended - RW */
243 #define IGC_WUS_EXT 0x05814 /* Wakeup Status Extended - RW1C */
244 #define IGC_FHFTSL 0x05804 /* Flex Filter Indirect Table Select - RW */
245 #define IGC_PROXYFCEX 0x05590 /* Proxy Filter Control Extended - RW1C */
246 #define IGC_PROXYEXS 0x05594 /* Proxy Extended Status - RO */
247 #define IGC_WFUTPF 0x05500 /* Wake Flex UDP TCP Port Filter - RW Array */
248 #define IGC_RFUTPF 0x05580 /* Range Flex UDP TCP Port Filter - RW */
249 #define IGC_RWPFC 0x05584 /* Range Wake Port Filter Control - RW */
250 #define IGC_WFUTPS 0x05588 /* Wake Filter UDP TCP Status - RW1C */
251 #define IGC_WCS 0x0558C /* Wake Control Status - RW1C */
252 /* MSI-X Table Register Descriptions */
253 #define IGC_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */
254 #define IGC_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
262 #define IGC_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
263 #define IGC_MANC2H 0x05860 /* Management Control To Host - RW */
267 #define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
272 /* Driver-only SW semaphore (not used by BOOT agents) */
279 #define IGC_MRQC 0x05818 /* Multiple Receive Control - RW */
282 #define IGC_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
283 #define IGC_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
284 /* Redirection Table - RW Array */
286 /* RSS Random Key - RW Array */
290 #define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
291 #define IGC_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
292 #define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
293 #define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
294 #define IGC_RXSTMPL 0x0B624 /* Rx timestamp Low - RO */
295 #define IGC_RXSTMPH 0x0B628 /* Rx timestamp High - RO */
296 #define IGC_RXSATRL 0x0B62C /* Rx timestamp attribute low - RO */
297 #define IGC_RXSATRH 0x0B630 /* Rx timestamp attribute high - RO */
298 #define IGC_TXSTMPL 0x0B618 /* Tx timestamp value Low - RO */
299 #define IGC_TXSTMPH 0x0B61C /* Tx timestamp value High - RO */
300 #define IGC_SYSTIML 0x0B600 /* System time register Low - RO */
301 #define IGC_SYSTIMH 0x0B604 /* System time register High - RO */
302 #define IGC_TIMINCA 0x0B608 /* Increment attributes register - RW */
303 #define IGC_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
304 #define IGC_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
314 #define IGC_FTQF(_n) (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
315 #define IGC_TTQF(_n) (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
329 #define IGC_RTRPCS 0x2474 /* Rx packet plane control and status */
330 #define IGC_RTRUP2TC 0x05AC4 /* Rx User Priority to Traffic Class */
332 /* Tx Desc plane TC Rate-scheduler config */
334 /* Tx Packet plane TC Rate-Scheduler Config */
336 /* Rx Packet plane TC Rate-Scheduler Config */
338 /* Tx Desc Plane TC Rate-Scheduler Status */
340 /* Tx Desc Plane TC Rate-Scheduler MMW */
342 /* Tx Packet plane TC Rate-Scheduler Status */
344 /* Tx Packet plane TC Rate-scheduler MMW */
346 /* Rx Packet plane TC Rate-Scheduler Status */
348 /* Rx Packet plane TC Rate-Scheduler MMW */
350 /* Tx Desc plane VM Rate-Scheduler MMW*/
352 /* Tx BCN Rate-Scheduler MMW */
355 #define IGC_RTTDVMRC 0x3608 /* Tx Desc Plane VM Rate-Scheduler Config */
356 #define IGC_RTTDVMRS 0x360C /* Tx Desc Plane VM Rate-Scheduler Status */
357 #define IGC_RTTBCNRC 0x36B0 /* Tx BCN Rate-Scheduler Config */
358 #define IGC_RTTBCNRS 0x36B4 /* Tx BCN Rate-Scheduler Status */
362 #define IGC_RTRBCNCR 0xB20C /* Rx BCN Control Register */
374 #define IGC_DMCCNT 0x05DD4 /* Current Rx Count */
375 #define IGC_FCRTC 0x02170 /* Flow Control Rx high watermark */
396 #define IGC_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */
397 #define IGC_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */
410 #define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
411 #define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
412 #define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
413 #define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
414 #define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
415 #define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
416 #define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */