Lines Matching full:rw
11 #define IGC_CTRL 0x00000 /* Device Control - RW */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
18 #define IGC_MDIC 0x00020 /* MDI Control - RW */
19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */
20 #define IGC_FCAL 0x00028 /* Flow Control Address Low - RW */
21 #define IGC_FCAH 0x0002C /* Flow Control Address High -RW */
26 #define IGC_FCT 0x00030 /* Flow Control Type - RW */
27 #define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
28 #define IGC_VET 0x00038 /* VLAN Ether Type - RW */
31 #define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */
33 #define IGC_IAM 0x01510 /* Intr Ack Auto Mask- RW */
34 #define IGC_RCTL 0x00100 /* Rx Control - RW */
35 #define IGC_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
36 #define IGC_TXCW 0x00178 /* Tx Configuration Word - RW */
41 #define IGC_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
43 #define IGC_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
44 #define IGC_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
45 #define IGC_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */
46 #define IGC_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
47 #define IGC_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
48 #define IGC_TCTL 0x00400 /* Tx Control - RW */
49 #define IGC_TCTL_EXT 0x00404 /* Extended Tx Control - RW */
50 #define IGC_TIPG 0x00410 /* Tx Inter-packet gap -RW */
51 #define IGC_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
52 #define IGC_LEDCTL 0x00E00 /* LED Control - RW */
57 #define IGC_PBA 0x01000 /* Packet Buffer Allocation - RW */
63 #define IGC_WDSTP 0x01040 /* Watchdog Setup - RW */
64 #define IGC_SWDSTS 0x01044 /* SW Device Status - RW */
65 #define IGC_FRTIMER 0x01048 /* Free Running Timer - RW */
66 #define IGC_TCPTIMER 0x0104C /* TCP Timer - RW */
67 #define IGC_ERT 0x02008 /* Early Rx Threshold - RW */
68 #define IGC_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
69 #define IGC_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
70 #define IGC_PSRCTL 0x02170 /* Packet Split Receive Control - RW */
71 #define IGC_RDFH 0x02410 /* Rx Data FIFO Head - RW */
72 #define IGC_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
73 #define IGC_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
74 #define IGC_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
75 #define IGC_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
76 #define IGC_PBRTH 0x02458 /* PB Rx Arbitration Threshold - RW */
77 #define IGC_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
78 /* Split and Replication Rx Control - RW */
79 #define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
80 /* Shadow Ram Write Register - RW */
129 #define IGC_RSRPD 0x02C00 /* Rx Small Packet Detect - RW */
130 #define IGC_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */
147 #define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
148 #define IGC_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
149 #define IGC_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
223 #define IGC_PCS_ANADV 0x04218 /* AN advertisement - RW */
224 #define IGC_PCS_LPAB 0x0421C /* Link Partner Ability - RW */
225 #define IGC_RXCSUM 0x05000 /* Rx Checksum Control - RW */
228 #define IGC_MTA 0x05200 /* Multicast Table Array - RW Array */
229 #define IGC_RA 0x05400 /* Receive Address - RW Array */
230 #define IGC_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
231 #define IGC_WUC 0x05800 /* Wakeup Control - RW */
232 #define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */
235 #define IGC_MANC 0x05820 /* Management Control - RW */
236 #define IGC_IPAV 0x05838 /* IP Address Valid - RW */
237 #define IGC_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
238 #define IGC_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
239 #define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */
242 #define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Extended - RW */
244 #define IGC_FHFTSL 0x05804 /* Flex Filter Indirect Table Select - RW */
247 #define IGC_WFUTPF 0x05500 /* Wake Flex UDP TCP Port Filter - RW Array */
248 #define IGC_RFUTPF 0x05580 /* Range Flex UDP TCP Port Filter - RW */
249 #define IGC_RWPFC 0x05584 /* Range Wake Port Filter Control - RW */
254 #define IGC_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
262 #define IGC_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
263 #define IGC_MANC2H 0x05860 /* Management Control To Host - RW */
267 #define IGC_SW_FW_SYNC 0x05B5C /* SW-FW Synchronization - RW */
279 #define IGC_MRQC 0x05818 /* Multiple Receive Control - RW */
282 #define IGC_IMIRVP 0x05AC0 /* Immediate INT Rx VLAN Priority -RW */
283 #define IGC_MSIXBM(_i) (0x01600 + ((_i) * 4)) /* MSI-X Alloc Reg -RW */
284 /* Redirection Table - RW Array */
286 /* RSS Random Key - RW Array */
290 #define IGC_UTA 0x0A000 /* Unicast Table Array - RW */
291 #define IGC_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
292 #define IGC_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
293 #define IGC_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
302 #define IGC_TIMINCA 0x0B608 /* Increment attributes register - RW */
303 #define IGC_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
304 #define IGC_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
410 #define IGC_TRGTTIML0 0x0B644 /* Target Time Register 0 Low - RW */
411 #define IGC_TRGTTIMH0 0x0B648 /* Target Time Register 0 High - RW */
412 #define IGC_TRGTTIML1 0x0B64C /* Target Time Register 1 Low - RW */
413 #define IGC_TRGTTIMH1 0x0B650 /* Target Time Register 1 High - RW */
414 #define IGC_FREQOUT0 0x0B654 /* Frequency Out 0 Control Register - RW */
415 #define IGC_FREQOUT1 0x0B658 /* Frequency Out 1 Control Register - RW */
416 #define IGC_TSSDP 0x0003C /* Time Sync SDP Configuration Register - RW */