24 	phy->ops.init_params = igc_null_ops_generic;  in igc_init_phy_ops_generic()
25 	phy->ops.acquire = igc_null_ops_generic;  in igc_init_phy_ops_generic()
26 	phy->ops.check_reset_block = igc_null_ops_generic;  in igc_init_phy_ops_generic()
27 	phy->ops.force_speed_duplex = igc_null_ops_generic;  in igc_init_phy_ops_generic()
28 	phy->ops.get_info = igc_null_ops_generic;  in igc_init_phy_ops_generic()
29 	phy->ops.set_page = igc_null_set_page;  in igc_init_phy_ops_generic()
30 	phy->ops.read_reg = igc_null_read_reg;  in igc_init_phy_ops_generic()
31 	phy->ops.read_reg_locked = igc_null_read_reg;  in igc_init_phy_ops_generic()
32 	phy->ops.read_reg_page = igc_null_read_reg;  in igc_init_phy_ops_generic()
33 	phy->ops.release = igc_null_phy_generic;  in igc_init_phy_ops_generic()
34 	phy->ops.reset = igc_null_ops_generic;  in igc_init_phy_ops_generic()
35 	phy->ops.set_d0_lplu_state = igc_null_lplu_state;  in igc_init_phy_ops_generic()
36 	phy->ops.set_d3_lplu_state = igc_null_lplu_state;  in igc_init_phy_ops_generic()
37 	phy->ops.write_reg = igc_null_write_reg;  in igc_init_phy_ops_generic()
38 	phy->ops.write_reg_locked = igc_null_write_reg;  in igc_init_phy_ops_generic()
39 	phy->ops.write_reg_page = igc_null_write_reg;  in igc_init_phy_ops_generic()
40 	phy->ops.power_up = igc_null_phy_generic;  in igc_init_phy_ops_generic()
41 	phy->ops.power_down = igc_null_phy_generic;  in igc_init_phy_ops_generic()
139 	if (!phy->ops.read_reg)  in igc_get_phy_id()
142 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);  in igc_get_phy_id()
148 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);  in igc_get_phy_id()
299 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);  in igc_phy_setup_autoneg()
305 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,  in igc_phy_setup_autoneg()
313 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<  in igc_phy_setup_autoneg()
441 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);  in igc_phy_setup_autoneg()
448 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,  in igc_phy_setup_autoneg()
452 		ret_val = phy->ops.write_reg(hw,  in igc_phy_setup_autoneg()
500 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);  in igc_copper_link_autoneg()
505 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);  in igc_copper_link_autoneg()
553 		ret_val = hw->phy.ops.force_speed_duplex(hw);  in igc_setup_copper_link_generic()
570 		hw->mac.ops.config_collision_dist(hw);  in igc_setup_copper_link_generic()
635 	hw->mac.ops.config_collision_dist(hw);  in igc_phy_force_speed_duplex_setup()
662 	if (!hw->phy.ops.read_reg)  in igc_set_d3_lplu_state_generic()
665 	ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);  in igc_set_d3_lplu_state_generic()
671 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,  in igc_set_d3_lplu_state_generic()
681 			ret_val = phy->ops.read_reg(hw,  in igc_set_d3_lplu_state_generic()
688 			ret_val = phy->ops.write_reg(hw,  in igc_set_d3_lplu_state_generic()
694 			ret_val = phy->ops.read_reg(hw,  in igc_set_d3_lplu_state_generic()
701 			ret_val = phy->ops.write_reg(hw,  in igc_set_d3_lplu_state_generic()
711 		ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,  in igc_set_d3_lplu_state_generic()
717 		ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,  in igc_set_d3_lplu_state_generic()
723 		ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,  in igc_set_d3_lplu_state_generic()
770 	if (!hw->phy.ops.read_reg)  in igc_wait_autoneg()
775 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_wait_autoneg()
778 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_wait_autoneg()
809 	if (!hw->phy.ops.read_reg)  in igc_phy_has_link_generic()
817 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_phy_has_link_generic()
828 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);  in igc_phy_has_link_generic()
861 	if (phy->ops.check_reset_block) {  in igc_phy_hw_reset_generic()
862 		ret_val = phy->ops.check_reset_block(hw);  in igc_phy_hw_reset_generic()
867 	ret_val = phy->ops.acquire(hw);  in igc_phy_hw_reset_generic()
893 	phy->ops.release(hw);  in igc_phy_hw_reset_generic()
911 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);  in igc_power_up_phy_copper()
913 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);  in igc_power_up_phy_copper()
930 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);  in igc_power_down_phy_copper()
932 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);  in igc_power_down_phy_copper()
954 		ret_val = hw->phy.ops.acquire(hw);  in igc_write_phy_reg_gpy()
960 		hw->phy.ops.release(hw);  in igc_write_phy_reg_gpy()
988 		ret_val = hw->phy.ops.acquire(hw);  in igc_read_phy_reg_gpy()
994 		hw->phy.ops.release(hw);  in igc_read_phy_reg_gpy()
1018 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);  in __igc_access_xmdio_reg()
1022 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);  in __igc_access_xmdio_reg()
1026 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |  in __igc_access_xmdio_reg()
1032 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);  in __igc_access_xmdio_reg()
1034 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);  in __igc_access_xmdio_reg()
1039 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);  in __igc_access_xmdio_reg()