Lines Matching full:phy
13 * igc_init_phy_ops_generic - Initialize PHY function pointers
20 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_ops_generic() local
24 phy->ops.init_params = igc_null_ops_generic; in igc_init_phy_ops_generic()
25 phy->ops.acquire = igc_null_ops_generic; in igc_init_phy_ops_generic()
26 phy->ops.check_reset_block = igc_null_ops_generic; in igc_init_phy_ops_generic()
27 phy->ops.force_speed_duplex = igc_null_ops_generic; in igc_init_phy_ops_generic()
28 phy->ops.get_info = igc_null_ops_generic; in igc_init_phy_ops_generic()
29 phy->ops.set_page = igc_null_set_page; in igc_init_phy_ops_generic()
30 phy->ops.read_reg = igc_null_read_reg; in igc_init_phy_ops_generic()
31 phy->ops.read_reg_locked = igc_null_read_reg; in igc_init_phy_ops_generic()
32 phy->ops.read_reg_page = igc_null_read_reg; in igc_init_phy_ops_generic()
33 phy->ops.release = igc_null_phy_generic; in igc_init_phy_ops_generic()
34 phy->ops.reset = igc_null_ops_generic; in igc_init_phy_ops_generic()
35 phy->ops.set_d0_lplu_state = igc_null_lplu_state; in igc_init_phy_ops_generic()
36 phy->ops.set_d3_lplu_state = igc_null_lplu_state; in igc_init_phy_ops_generic()
37 phy->ops.write_reg = igc_null_write_reg; in igc_init_phy_ops_generic()
38 phy->ops.write_reg_locked = igc_null_write_reg; in igc_init_phy_ops_generic()
39 phy->ops.write_reg_page = igc_null_write_reg; in igc_init_phy_ops_generic()
40 phy->ops.power_up = igc_null_phy_generic; in igc_init_phy_ops_generic()
41 phy->ops.power_down = igc_null_phy_generic; in igc_init_phy_ops_generic()
105 * igc_check_reset_block_generic - Check if PHY reset is blocked
108 * Read the PHY management control register and check whether a PHY reset
125 * igc_get_phy_id - Retrieve the PHY ID and revision
128 * Reads the PHY registers and stores the PHY ID and possibly the PHY
133 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id() local
139 if (!phy->ops.read_reg) in igc_get_phy_id()
142 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
146 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
148 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); in igc_get_phy_id()
152 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in igc_get_phy_id()
153 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); in igc_get_phy_id()
164 * Reads the MDI control register in the PHY at offset and stores the
169 struct igc_phy_info *phy = &hw->phy; in igc_read_phy_reg_mdic() local
175 DEBUGOUT1("PHY Address %d is out of range\n", offset); in igc_read_phy_reg_mdic()
179 /* Set up Op-code, Phy Address, and register offset in the MDI in igc_read_phy_reg_mdic()
181 * PHY to retrieve the desired data. in igc_read_phy_reg_mdic()
184 (phy->addr << IGC_MDIC_PHY_SHIFT) | in igc_read_phy_reg_mdic()
224 * Writes data to MDI control register in the PHY at offset.
228 struct igc_phy_info *phy = &hw->phy; in igc_write_phy_reg_mdic() local
234 DEBUGOUT1("PHY Address %d is out of range\n", offset); in igc_write_phy_reg_mdic()
238 /* Set up Op-code, Phy Address, and register offset in the MDI in igc_write_phy_reg_mdic()
240 * PHY to retrieve the desired data. in igc_write_phy_reg_mdic()
244 (phy->addr << IGC_MDIC_PHY_SHIFT) | in igc_write_phy_reg_mdic()
278 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
282 * register and if the PHY is already setup for auto-negotiation, then
288 struct igc_phy_info *phy = &hw->phy; in igc_phy_setup_autoneg() local
296 phy->autoneg_advertised &= phy->autoneg_mask; in igc_phy_setup_autoneg()
299 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
303 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { in igc_phy_setup_autoneg()
305 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
311 if (phy->autoneg_mask & ADVERTISE_2500_FULL) { in igc_phy_setup_autoneg()
313 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << in igc_phy_setup_autoneg()
323 * the appropriate PHY registers. First we will parse for in igc_phy_setup_autoneg()
339 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); in igc_phy_setup_autoneg()
342 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { in igc_phy_setup_autoneg()
348 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { in igc_phy_setup_autoneg()
354 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { in igc_phy_setup_autoneg()
360 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { in igc_phy_setup_autoneg()
365 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ in igc_phy_setup_autoneg()
366 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) in igc_phy_setup_autoneg()
370 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { in igc_phy_setup_autoneg()
375 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */ in igc_phy_setup_autoneg()
376 if (phy->autoneg_advertised & ADVERTISE_2500_HALF) in igc_phy_setup_autoneg()
380 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) { in igc_phy_setup_autoneg()
388 * setup the PHY advertisement registers accordingly. If in igc_phy_setup_autoneg()
441 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); in igc_phy_setup_autoneg()
447 if (phy->autoneg_mask & ADVERTISE_1000_FULL) in igc_phy_setup_autoneg()
448 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, in igc_phy_setup_autoneg()
451 if (phy->autoneg_mask & ADVERTISE_2500_FULL) in igc_phy_setup_autoneg()
452 ret_val = phy->ops.write_reg(hw, in igc_phy_setup_autoneg()
466 * configure to advertise the full capability. Setup the PHY to autoneg
472 struct igc_phy_info *phy = &hw->phy; in igc_copper_link_autoneg() local
481 phy->autoneg_advertised &= phy->autoneg_mask; in igc_copper_link_autoneg()
486 if (!phy->autoneg_advertised) in igc_copper_link_autoneg()
487 phy->autoneg_advertised = phy->autoneg_mask; in igc_copper_link_autoneg()
498 * the Auto Neg Restart bit in the PHY control register. in igc_copper_link_autoneg()
500 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); in igc_copper_link_autoneg()
505 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); in igc_copper_link_autoneg()
512 if (phy->autoneg_wait_to_complete) { in igc_copper_link_autoneg()
549 /* PHY will be set to 10H, 10F, 100H or 100F in igc_setup_copper_link_generic()
553 ret_val = hw->phy.ops.force_speed_duplex(hw); in igc_setup_copper_link_generic()
580 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
584 * Forces speed and duplex on the PHY by doing the following: disable flow
609 /* Disable autoneg on the phy */ in igc_phy_force_speed_duplex_setup()
656 struct igc_phy_info *phy = &hw->phy; in igc_set_d3_lplu_state_generic() local
662 if (!hw->phy.ops.read_reg) in igc_set_d3_lplu_state_generic()
665 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data); in igc_set_d3_lplu_state_generic()
671 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
680 if (phy->smart_speed == igc_smart_speed_on) { in igc_set_d3_lplu_state_generic()
681 ret_val = phy->ops.read_reg(hw, in igc_set_d3_lplu_state_generic()
688 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
693 } else if (phy->smart_speed == igc_smart_speed_off) { in igc_set_d3_lplu_state_generic()
694 ret_val = phy->ops.read_reg(hw, in igc_set_d3_lplu_state_generic()
701 ret_val = phy->ops.write_reg(hw, in igc_set_d3_lplu_state_generic()
707 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) || in igc_set_d3_lplu_state_generic()
708 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) || in igc_set_d3_lplu_state_generic()
709 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) { in igc_set_d3_lplu_state_generic()
711 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT, in igc_set_d3_lplu_state_generic()
717 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG, in igc_set_d3_lplu_state_generic()
723 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG, in igc_set_d3_lplu_state_generic()
736 * A downshift is detected by querying the PHY link health.
740 struct igc_phy_info *phy = &hw->phy; in igc_check_downshift_generic() local
745 switch (phy->type) { in igc_check_downshift_generic()
749 phy->speed_downgraded = false; in igc_check_downshift_generic()
770 if (!hw->phy.ops.read_reg) in igc_wait_autoneg()
775 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
778 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_wait_autoneg()
793 * igc_phy_has_link_generic - Polls PHY for link
799 * Polls the PHY status register for link, 'iterations' number of times.
809 if (!hw->phy.ops.read_reg) in igc_phy_has_link_generic()
817 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link_generic()
828 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); in igc_phy_has_link_generic()
845 * igc_phy_hw_reset_generic - PHY hardware reset
850 * bit in the PHY. Wait the appropriate delay time for the device to
855 struct igc_phy_info *phy = &hw->phy; in igc_phy_hw_reset_generic() local
861 if (phy->ops.check_reset_block) { in igc_phy_hw_reset_generic()
862 ret_val = phy->ops.check_reset_block(hw); in igc_phy_hw_reset_generic()
867 ret_val = phy->ops.acquire(hw); in igc_phy_hw_reset_generic()
877 usec_delay(phy->reset_delay_us); in igc_phy_hw_reset_generic()
891 DEBUGOUT("Timeout expired after a phy reset\n"); in igc_phy_hw_reset_generic()
893 phy->ops.release(hw); in igc_phy_hw_reset_generic()
899 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
902 * In the case of a PHY power down to save power, or to turn off link during a
910 /* The PHY will retain its settings across a power down/up cycle */ in igc_power_up_phy_copper()
911 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_up_phy_copper()
913 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igc_power_up_phy_copper()
918 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
921 * In the case of a PHY power down to save power, or to turn off link during a
929 /* The PHY will retain its settings across a power down/up cycle */ in igc_power_down_phy_copper()
930 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); in igc_power_down_phy_copper()
932 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); in igc_power_down_phy_copper()
936 * igc_write_phy_reg_gpy - Write GPY PHY register
941 * Acquires semaphore, if necessary, then writes the data to PHY register
954 ret_val = hw->phy.ops.acquire(hw); in igc_write_phy_reg_gpy()
960 hw->phy.ops.release(hw); in igc_write_phy_reg_gpy()
969 * igc_read_phy_reg_gpy - Read GPY PHY register
975 * Acquires semaphore, if necessary, then reads the data in the PHY register
988 ret_val = hw->phy.ops.acquire(hw); in igc_read_phy_reg_gpy()
994 hw->phy.ops.release(hw); in igc_read_phy_reg_gpy()
1018 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr); in __igc_access_xmdio_reg()
1022 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address); in __igc_access_xmdio_reg()
1026 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA | in __igc_access_xmdio_reg()
1032 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data); in __igc_access_xmdio_reg()
1034 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data); in __igc_access_xmdio_reg()
1039 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0); in __igc_access_xmdio_reg()