10 static void igc_config_collision_dist_generic(struct igc_hw *hw);
18 void igc_init_mac_ops_generic(struct igc_hw *hw)  in igc_init_mac_ops_generic()  argument
20 	struct igc_mac_info *mac = &hw->mac;  in igc_init_mac_ops_generic()
33 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)  in igc_null_ops_generic()  argument
43 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw)  in igc_null_mac_generic()  argument
55 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw,  in igc_null_link_info()  argument
66 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw)  in igc_null_mng_mode()  argument
78 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw,  in igc_null_update_mc()  argument
91 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw,  in igc_null_write_vfta()  argument
104 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw,  in igc_null_rar_set()  argument
117 void igc_set_lan_id_single_port(struct igc_hw *hw)  in igc_set_lan_id_single_port()  argument
119 	struct igc_bus_info *bus = &hw->bus;  in igc_set_lan_id_single_port()
131 void igc_clear_vfta_generic(struct igc_hw *hw)  in igc_clear_vfta_generic()  argument
138 		IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);  in igc_clear_vfta_generic()
139 		IGC_WRITE_FLUSH(hw);  in igc_clear_vfta_generic()
152 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)  in igc_write_vfta_generic()  argument
156 	IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);  in igc_write_vfta_generic()
157 	IGC_WRITE_FLUSH(hw);  in igc_write_vfta_generic()
169 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)  in igc_init_rx_addrs_generic()  argument
179 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);  in igc_init_rx_addrs_generic()
184 		hw->mac.ops.rar_set(hw, mac_addr, i);  in igc_init_rx_addrs_generic()
199 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)  in igc_check_alt_mac_addr_generic()  argument
208 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);  in igc_check_alt_mac_addr_generic()
213 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,  in igc_check_alt_mac_addr_generic()
225 	if (hw->bus.func == IGC_FUNC_1)  in igc_check_alt_mac_addr_generic()
229 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);  in igc_check_alt_mac_addr_generic()
249 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);  in igc_check_alt_mac_addr_generic()
263 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)  in igc_rar_set_generic()  argument
285 	IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);  in igc_rar_set_generic()
286 	IGC_WRITE_FLUSH(hw);  in igc_rar_set_generic()
287 	IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);  in igc_rar_set_generic()
288 	IGC_WRITE_FLUSH(hw);  in igc_rar_set_generic()
301 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)  in igc_hash_mc_addr_generic()  argument
309 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;  in igc_hash_mc_addr_generic()
342 	switch (hw->mac.mc_filter_type) {  in igc_hash_mc_addr_generic()
372 void igc_update_mc_addr_list_generic(struct igc_hw *hw,  in igc_update_mc_addr_list_generic()  argument
381 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));  in igc_update_mc_addr_list_generic()
385 		hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);  in igc_update_mc_addr_list_generic()
387 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);  in igc_update_mc_addr_list_generic()
390 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);  in igc_update_mc_addr_list_generic()
395 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)  in igc_update_mc_addr_list_generic()
396 		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);  in igc_update_mc_addr_list_generic()
397 	IGC_WRITE_FLUSH(hw);  in igc_update_mc_addr_list_generic()
406 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)  in igc_clear_hw_cntrs_base_generic()  argument
410 	IGC_READ_REG(hw, IGC_CRCERRS);  in igc_clear_hw_cntrs_base_generic()
411 	IGC_READ_REG(hw, IGC_MPC);  in igc_clear_hw_cntrs_base_generic()
412 	IGC_READ_REG(hw, IGC_SCC);  in igc_clear_hw_cntrs_base_generic()
413 	IGC_READ_REG(hw, IGC_ECOL);  in igc_clear_hw_cntrs_base_generic()
414 	IGC_READ_REG(hw, IGC_MCC);  in igc_clear_hw_cntrs_base_generic()
415 	IGC_READ_REG(hw, IGC_LATECOL);  in igc_clear_hw_cntrs_base_generic()
416 	IGC_READ_REG(hw, IGC_COLC);  in igc_clear_hw_cntrs_base_generic()
417 	IGC_READ_REG(hw, IGC_RERC);  in igc_clear_hw_cntrs_base_generic()
418 	IGC_READ_REG(hw, IGC_DC);  in igc_clear_hw_cntrs_base_generic()
419 	IGC_READ_REG(hw, IGC_RLEC);  in igc_clear_hw_cntrs_base_generic()
420 	IGC_READ_REG(hw, IGC_XONRXC);  in igc_clear_hw_cntrs_base_generic()
421 	IGC_READ_REG(hw, IGC_XONTXC);  in igc_clear_hw_cntrs_base_generic()
422 	IGC_READ_REG(hw, IGC_XOFFRXC);  in igc_clear_hw_cntrs_base_generic()
423 	IGC_READ_REG(hw, IGC_XOFFTXC);  in igc_clear_hw_cntrs_base_generic()
424 	IGC_READ_REG(hw, IGC_FCRUC);  in igc_clear_hw_cntrs_base_generic()
425 	IGC_READ_REG(hw, IGC_GPRC);  in igc_clear_hw_cntrs_base_generic()
426 	IGC_READ_REG(hw, IGC_BPRC);  in igc_clear_hw_cntrs_base_generic()
427 	IGC_READ_REG(hw, IGC_MPRC);  in igc_clear_hw_cntrs_base_generic()
428 	IGC_READ_REG(hw, IGC_GPTC);  in igc_clear_hw_cntrs_base_generic()
429 	IGC_READ_REG(hw, IGC_GORCL);  in igc_clear_hw_cntrs_base_generic()
430 	IGC_READ_REG(hw, IGC_GORCH);  in igc_clear_hw_cntrs_base_generic()
431 	IGC_READ_REG(hw, IGC_GOTCL);  in igc_clear_hw_cntrs_base_generic()
432 	IGC_READ_REG(hw, IGC_GOTCH);  in igc_clear_hw_cntrs_base_generic()
433 	IGC_READ_REG(hw, IGC_RNBC);  in igc_clear_hw_cntrs_base_generic()
434 	IGC_READ_REG(hw, IGC_RUC);  in igc_clear_hw_cntrs_base_generic()
435 	IGC_READ_REG(hw, IGC_RFC);  in igc_clear_hw_cntrs_base_generic()
436 	IGC_READ_REG(hw, IGC_ROC);  in igc_clear_hw_cntrs_base_generic()
437 	IGC_READ_REG(hw, IGC_RJC);  in igc_clear_hw_cntrs_base_generic()
438 	IGC_READ_REG(hw, IGC_TORL);  in igc_clear_hw_cntrs_base_generic()
439 	IGC_READ_REG(hw, IGC_TORH);  in igc_clear_hw_cntrs_base_generic()
440 	IGC_READ_REG(hw, IGC_TOTL);  in igc_clear_hw_cntrs_base_generic()
441 	IGC_READ_REG(hw, IGC_TOTH);  in igc_clear_hw_cntrs_base_generic()
442 	IGC_READ_REG(hw, IGC_TPR);  in igc_clear_hw_cntrs_base_generic()
443 	IGC_READ_REG(hw, IGC_TPT);  in igc_clear_hw_cntrs_base_generic()
444 	IGC_READ_REG(hw, IGC_MPTC);  in igc_clear_hw_cntrs_base_generic()
445 	IGC_READ_REG(hw, IGC_BPTC);  in igc_clear_hw_cntrs_base_generic()
446 	IGC_READ_REG(hw, IGC_TLPIC);  in igc_clear_hw_cntrs_base_generic()
447 	IGC_READ_REG(hw, IGC_RLPIC);  in igc_clear_hw_cntrs_base_generic()
448 	IGC_READ_REG(hw, IGC_RXDMTC);  in igc_clear_hw_cntrs_base_generic()
459 s32 igc_check_for_copper_link_generic(struct igc_hw *hw)  in igc_check_for_copper_link_generic()  argument
461 	struct igc_mac_info *mac = &hw->mac;  in igc_check_for_copper_link_generic()
479 	ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);  in igc_check_for_copper_link_generic()
491 	igc_check_downshift_generic(hw);  in igc_check_for_copper_link_generic()
503 	mac->ops.config_collision_dist(hw);  in igc_check_for_copper_link_generic()
510 	ret_val = igc_config_fc_after_link_up_generic(hw);  in igc_check_for_copper_link_generic()
527 s32 igc_setup_link_generic(struct igc_hw *hw)  in igc_setup_link_generic()  argument
536 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))  in igc_setup_link_generic()
542 	if (hw->fc.requested_mode == igc_fc_default) {  in igc_setup_link_generic()
543 		hw->fc.requested_mode = igc_fc_full;  in igc_setup_link_generic()
549 	hw->fc.current_mode = hw->fc.requested_mode;  in igc_setup_link_generic()
552 		hw->fc.current_mode);  in igc_setup_link_generic()
555 	ret_val = hw->mac.ops.setup_physical_interface(hw);  in igc_setup_link_generic()
565 	IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);  in igc_setup_link_generic()
566 	IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);  in igc_setup_link_generic()
567 	IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);  in igc_setup_link_generic()
569 	IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);  in igc_setup_link_generic()
571 	return igc_set_fc_watermarks_generic(hw);  in igc_setup_link_generic()
581 static void igc_config_collision_dist_generic(struct igc_hw *hw)  in igc_config_collision_dist_generic()  argument
587 	tctl = IGC_READ_REG(hw, IGC_TCTL);  in igc_config_collision_dist_generic()
592 	IGC_WRITE_REG(hw, IGC_TCTL, tctl);  in igc_config_collision_dist_generic()
593 	IGC_WRITE_FLUSH(hw);  in igc_config_collision_dist_generic()
604 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)  in igc_set_fc_watermarks_generic()  argument
616 	if (hw->fc.current_mode & igc_fc_tx_pause) {  in igc_set_fc_watermarks_generic()
621 		fcrtl = hw->fc.low_water;  in igc_set_fc_watermarks_generic()
622 		if (hw->fc.send_xon)  in igc_set_fc_watermarks_generic()
625 		fcrth = hw->fc.high_water;  in igc_set_fc_watermarks_generic()
627 	IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);  in igc_set_fc_watermarks_generic()
628 	IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);  in igc_set_fc_watermarks_generic()
643 s32 igc_force_mac_fc_generic(struct igc_hw *hw)  in igc_force_mac_fc_generic()  argument
649 	ctrl = IGC_READ_REG(hw, IGC_CTRL);  in igc_force_mac_fc_generic()
668 	DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);  in igc_force_mac_fc_generic()
670 	switch (hw->fc.current_mode) {  in igc_force_mac_fc_generic()
690 	IGC_WRITE_REG(hw, IGC_CTRL, ctrl);  in igc_force_mac_fc_generic()
705 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)  in igc_config_fc_after_link_up_generic()  argument
707 	struct igc_mac_info *mac = &hw->mac;  in igc_config_fc_after_link_up_generic()
729 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);  in igc_config_fc_after_link_up_generic()
732 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);  in igc_config_fc_after_link_up_generic()
747 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,  in igc_config_fc_after_link_up_generic()
751 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,  in igc_config_fc_after_link_up_generic()
797 			if (hw->fc.requested_mode == igc_fc_full) {  in igc_config_fc_after_link_up_generic()
798 				hw->fc.current_mode = igc_fc_full;  in igc_config_fc_after_link_up_generic()
801 				hw->fc.current_mode = igc_fc_rx_pause;  in igc_config_fc_after_link_up_generic()
816 			hw->fc.current_mode = igc_fc_tx_pause;  in igc_config_fc_after_link_up_generic()
830 			hw->fc.current_mode = igc_fc_rx_pause;  in igc_config_fc_after_link_up_generic()
836 			hw->fc.current_mode = igc_fc_none;  in igc_config_fc_after_link_up_generic()
844 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);  in igc_config_fc_after_link_up_generic()
851 			hw->fc.current_mode = igc_fc_none;  in igc_config_fc_after_link_up_generic()
856 		ret_val = igc_force_mac_fc_generic(hw);  in igc_config_fc_after_link_up_generic()
875 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,  in igc_get_speed_and_duplex_copper_generic()  argument
882 	status = IGC_READ_REG(hw, IGC_STATUS);  in igc_get_speed_and_duplex_copper_generic()
888 		if ((hw->mac.type == igc_i225) &&  in igc_get_speed_and_duplex_copper_generic()
921 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)  in igc_get_hw_semaphore_generic()  argument
924 	s32 timeout = hw->nvm.word_size + 1;  in igc_get_hw_semaphore_generic()
931 		swsm = IGC_READ_REG(hw, IGC_SWSM);  in igc_get_hw_semaphore_generic()
946 		swsm = IGC_READ_REG(hw, IGC_SWSM);  in igc_get_hw_semaphore_generic()
947 		IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);  in igc_get_hw_semaphore_generic()
950 		if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)  in igc_get_hw_semaphore_generic()
958 		igc_put_hw_semaphore_generic(hw);  in igc_get_hw_semaphore_generic()
972 void igc_put_hw_semaphore_generic(struct igc_hw *hw)  in igc_put_hw_semaphore_generic()  argument
978 	swsm = IGC_READ_REG(hw, IGC_SWSM);  in igc_put_hw_semaphore_generic()
982 	IGC_WRITE_REG(hw, IGC_SWSM, swsm);  in igc_put_hw_semaphore_generic()
991 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)  in igc_get_auto_rd_done_generic()  argument
998 		if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)  in igc_get_auto_rd_done_generic()
1023 s32 igc_disable_pcie_master_generic(struct igc_hw *hw)  in igc_disable_pcie_master_generic()  argument
1030 	ctrl = IGC_READ_REG(hw, IGC_CTRL);  in igc_disable_pcie_master_generic()
1032 	IGC_WRITE_REG(hw, IGC_CTRL, ctrl);  in igc_disable_pcie_master_generic()
1035 		if (!(IGC_READ_REG(hw, IGC_STATUS) &  in igc_disable_pcie_master_generic()