Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 static void igc_config_collision_dist_generic(struct igc_hw *hw);
13 * igc_init_mac_ops_generic - Initialize MAC function pointers
14 * @hw: pointer to the HW structure
16 * Setups up the function pointers to no-op functions
18 void igc_init_mac_ops_generic(struct igc_hw *hw) in igc_init_mac_ops_generic() argument
20 struct igc_mac_info *mac = &hw->mac; in igc_init_mac_ops_generic()
24 mac->ops.init_params = igc_null_ops_generic; in igc_init_mac_ops_generic()
25 mac->ops.config_collision_dist = igc_config_collision_dist_generic; in igc_init_mac_ops_generic()
26 mac->ops.rar_set = igc_rar_set_generic; in igc_init_mac_ops_generic()
30 * igc_null_ops_generic - No-op function, returns 0
31 * @hw: pointer to the HW structure
33 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw) in igc_null_ops_generic() argument
40 * igc_null_mac_generic - No-op function, return void
41 * @hw: pointer to the HW structure
43 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG *hw) in igc_null_mac_generic() argument
50 * igc_null_link_info - No-op function, return 0
51 * @hw: pointer to the HW structure
55 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_link_info() argument
63 * igc_null_mng_mode - No-op function, return false
64 * @hw: pointer to the HW structure
66 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG *hw) in igc_null_mng_mode() argument
73 * igc_null_update_mc - No-op function, return void
74 * @hw: pointer to the HW structure
78 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_update_mc() argument
86 * igc_null_write_vfta - No-op function, return void
87 * @hw: pointer to the HW structure
91 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_write_vfta() argument
99 * igc_null_rar_set - No-op function, return 0
100 * @hw: pointer to the HW structure
104 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG *hw, in igc_null_rar_set() argument
112 * igc_set_lan_id_single_port - Set LAN id for a single port device
113 * @hw: pointer to the HW structure
117 void igc_set_lan_id_single_port(struct igc_hw *hw) in igc_set_lan_id_single_port() argument
119 struct igc_bus_info *bus = &hw->bus; in igc_set_lan_id_single_port()
121 bus->func = 0; in igc_set_lan_id_single_port()
125 * igc_clear_vfta_generic - Clear VLAN filter table
126 * @hw: pointer to the HW structure
131 void igc_clear_vfta_generic(struct igc_hw *hw) in igc_clear_vfta_generic() argument
138 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0); in igc_clear_vfta_generic()
139 IGC_WRITE_FLUSH(hw); in igc_clear_vfta_generic()
144 * igc_write_vfta_generic - Write value to VLAN filter table
145 * @hw: pointer to the HW structure
152 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value) in igc_write_vfta_generic() argument
156 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value); in igc_write_vfta_generic()
157 IGC_WRITE_FLUSH(hw); in igc_write_vfta_generic()
161 * igc_init_rx_addrs_generic - Initialize receive address's
162 * @hw: pointer to the HW structure
169 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count) in igc_init_rx_addrs_generic() argument
179 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); in igc_init_rx_addrs_generic()
181 /* Zero out the other (rar_entry_count - 1) receive addresses */ in igc_init_rx_addrs_generic()
182 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); in igc_init_rx_addrs_generic()
184 hw->mac.ops.rar_set(hw, mac_addr, i); in igc_init_rx_addrs_generic()
188 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
189 * @hw: pointer to the HW structure
192 * can be setup by pre-boot software and must be treated like a permanent
199 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw) in igc_check_alt_mac_addr_generic() argument
208 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data); in igc_check_alt_mac_addr_generic()
213 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, in igc_check_alt_mac_addr_generic()
225 if (hw->bus.func == IGC_FUNC_1) in igc_check_alt_mac_addr_generic()
229 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); in igc_check_alt_mac_addr_generic()
246 * same as the normal permanent MAC address stored by the HW into the in igc_check_alt_mac_addr_generic()
249 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); in igc_check_alt_mac_addr_generic()
255 * igc_rar_set_generic - Set receive address register
256 * @hw: pointer to the HW structure
263 int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index) in igc_rar_set_generic() argument
269 /* HW expects these in little endian so we reverse the byte order in igc_rar_set_generic()
281 /* Some bridges will combine consecutive 32-bit writes into in igc_rar_set_generic()
285 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low); in igc_rar_set_generic()
286 IGC_WRITE_FLUSH(hw); in igc_rar_set_generic()
287 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high); in igc_rar_set_generic()
288 IGC_WRITE_FLUSH(hw); in igc_rar_set_generic()
294 * igc_hash_mc_addr_generic - Generate a multicast hash value
295 * @hw: pointer to the HW structure
301 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr) in igc_hash_mc_addr_generic() argument
309 hash_mask = (hw->mac.mta_reg_count * 32) - 1; in igc_hash_mc_addr_generic()
311 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts in igc_hash_mc_addr_generic()
321 * left-shifts where the MSB of mc_addr[5] would still fall within in igc_hash_mc_addr_generic()
324 * remaining number of bits. Thus 8 - bit_shift. The rest of the in igc_hash_mc_addr_generic()
327 * 8-bit shifting total. in igc_hash_mc_addr_generic()
330 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), in igc_hash_mc_addr_generic()
342 switch (hw->mac.mc_filter_type) { in igc_hash_mc_addr_generic()
357 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | in igc_hash_mc_addr_generic()
364 * igc_update_mc_addr_list_generic - Update Multicast addresses
365 * @hw: pointer to the HW structure
372 void igc_update_mc_addr_list_generic(struct igc_hw *hw, in igc_update_mc_addr_list_generic() argument
381 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); in igc_update_mc_addr_list_generic()
385 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list); in igc_update_mc_addr_list_generic()
387 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); in igc_update_mc_addr_list_generic()
390 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); in igc_update_mc_addr_list_generic()
395 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) in igc_update_mc_addr_list_generic()
396 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]); in igc_update_mc_addr_list_generic()
397 IGC_WRITE_FLUSH(hw); in igc_update_mc_addr_list_generic()
401 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
402 * @hw: pointer to the HW structure
406 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw) in igc_clear_hw_cntrs_base_generic() argument
410 IGC_READ_REG(hw, IGC_CRCERRS); in igc_clear_hw_cntrs_base_generic()
411 IGC_READ_REG(hw, IGC_MPC); in igc_clear_hw_cntrs_base_generic()
412 IGC_READ_REG(hw, IGC_SCC); in igc_clear_hw_cntrs_base_generic()
413 IGC_READ_REG(hw, IGC_ECOL); in igc_clear_hw_cntrs_base_generic()
414 IGC_READ_REG(hw, IGC_MCC); in igc_clear_hw_cntrs_base_generic()
415 IGC_READ_REG(hw, IGC_LATECOL); in igc_clear_hw_cntrs_base_generic()
416 IGC_READ_REG(hw, IGC_COLC); in igc_clear_hw_cntrs_base_generic()
417 IGC_READ_REG(hw, IGC_RERC); in igc_clear_hw_cntrs_base_generic()
418 IGC_READ_REG(hw, IGC_DC); in igc_clear_hw_cntrs_base_generic()
419 IGC_READ_REG(hw, IGC_RLEC); in igc_clear_hw_cntrs_base_generic()
420 IGC_READ_REG(hw, IGC_XONRXC); in igc_clear_hw_cntrs_base_generic()
421 IGC_READ_REG(hw, IGC_XONTXC); in igc_clear_hw_cntrs_base_generic()
422 IGC_READ_REG(hw, IGC_XOFFRXC); in igc_clear_hw_cntrs_base_generic()
423 IGC_READ_REG(hw, IGC_XOFFTXC); in igc_clear_hw_cntrs_base_generic()
424 IGC_READ_REG(hw, IGC_FCRUC); in igc_clear_hw_cntrs_base_generic()
425 IGC_READ_REG(hw, IGC_GPRC); in igc_clear_hw_cntrs_base_generic()
426 IGC_READ_REG(hw, IGC_BPRC); in igc_clear_hw_cntrs_base_generic()
427 IGC_READ_REG(hw, IGC_MPRC); in igc_clear_hw_cntrs_base_generic()
428 IGC_READ_REG(hw, IGC_GPTC); in igc_clear_hw_cntrs_base_generic()
429 IGC_READ_REG(hw, IGC_GORCL); in igc_clear_hw_cntrs_base_generic()
430 IGC_READ_REG(hw, IGC_GORCH); in igc_clear_hw_cntrs_base_generic()
431 IGC_READ_REG(hw, IGC_GOTCL); in igc_clear_hw_cntrs_base_generic()
432 IGC_READ_REG(hw, IGC_GOTCH); in igc_clear_hw_cntrs_base_generic()
433 IGC_READ_REG(hw, IGC_RNBC); in igc_clear_hw_cntrs_base_generic()
434 IGC_READ_REG(hw, IGC_RUC); in igc_clear_hw_cntrs_base_generic()
435 IGC_READ_REG(hw, IGC_RFC); in igc_clear_hw_cntrs_base_generic()
436 IGC_READ_REG(hw, IGC_ROC); in igc_clear_hw_cntrs_base_generic()
437 IGC_READ_REG(hw, IGC_RJC); in igc_clear_hw_cntrs_base_generic()
438 IGC_READ_REG(hw, IGC_TORL); in igc_clear_hw_cntrs_base_generic()
439 IGC_READ_REG(hw, IGC_TORH); in igc_clear_hw_cntrs_base_generic()
440 IGC_READ_REG(hw, IGC_TOTL); in igc_clear_hw_cntrs_base_generic()
441 IGC_READ_REG(hw, IGC_TOTH); in igc_clear_hw_cntrs_base_generic()
442 IGC_READ_REG(hw, IGC_TPR); in igc_clear_hw_cntrs_base_generic()
443 IGC_READ_REG(hw, IGC_TPT); in igc_clear_hw_cntrs_base_generic()
444 IGC_READ_REG(hw, IGC_MPTC); in igc_clear_hw_cntrs_base_generic()
445 IGC_READ_REG(hw, IGC_BPTC); in igc_clear_hw_cntrs_base_generic()
446 IGC_READ_REG(hw, IGC_TLPIC); in igc_clear_hw_cntrs_base_generic()
447 IGC_READ_REG(hw, IGC_RLPIC); in igc_clear_hw_cntrs_base_generic()
448 IGC_READ_REG(hw, IGC_RXDMTC); in igc_clear_hw_cntrs_base_generic()
452 * igc_check_for_copper_link_generic - Check for link (Copper)
453 * @hw: pointer to the HW structure
459 s32 igc_check_for_copper_link_generic(struct igc_hw *hw) in igc_check_for_copper_link_generic() argument
461 struct igc_mac_info *mac = &hw->mac; in igc_check_for_copper_link_generic()
467 /* We only want to go out to the PHY registers to see if Auto-Neg in igc_check_for_copper_link_generic()
472 if (!mac->get_link_status) in igc_check_for_copper_link_generic()
479 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); in igc_check_for_copper_link_generic()
486 mac->get_link_status = false; in igc_check_for_copper_link_generic()
489 * immediately after link-up in igc_check_for_copper_link_generic()
491 igc_check_downshift_generic(hw); in igc_check_for_copper_link_generic()
496 if (!mac->autoneg) in igc_check_for_copper_link_generic()
497 return -IGC_ERR_CONFIG; in igc_check_for_copper_link_generic()
499 /* Auto-Neg is enabled. Auto Speed Detection takes care in igc_check_for_copper_link_generic()
503 mac->ops.config_collision_dist(hw); in igc_check_for_copper_link_generic()
505 /* Configure Flow Control now that Auto-Neg has completed. in igc_check_for_copper_link_generic()
506 * First, we need to restore the desired flow control in igc_check_for_copper_link_generic()
507 * settings because we may have had to re-autoneg with a in igc_check_for_copper_link_generic()
510 ret_val = igc_config_fc_after_link_up_generic(hw); in igc_check_for_copper_link_generic()
512 DEBUGOUT("Error configuring flow control\n"); in igc_check_for_copper_link_generic()
518 * igc_setup_link_generic - Setup flow control and link settings
519 * @hw: pointer to the HW structure
521 * Determines which flow control settings to use, then configures flow
522 * control. Calls the appropriate media-specific link configuration
527 s32 igc_setup_link_generic(struct igc_hw *hw) in igc_setup_link_generic() argument
536 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) in igc_setup_link_generic()
539 /* If requested flow control is set to default, set flow control in igc_setup_link_generic()
542 if (hw->fc.requested_mode == igc_fc_default) { in igc_setup_link_generic()
543 hw->fc.requested_mode = igc_fc_full; in igc_setup_link_generic()
546 /* Save off the requested flow control mode for use later. Depending in igc_setup_link_generic()
549 hw->fc.current_mode = hw->fc.requested_mode; in igc_setup_link_generic()
551 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", in igc_setup_link_generic()
552 hw->fc.current_mode); in igc_setup_link_generic()
555 ret_val = hw->mac.ops.setup_physical_interface(hw); in igc_setup_link_generic()
559 /* Initialize the flow control address, type, and PAUSE timer in igc_setup_link_generic()
560 * registers to their default values. This is done even if flow in igc_setup_link_generic()
564 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); in igc_setup_link_generic()
565 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE); in igc_setup_link_generic()
566 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH); in igc_setup_link_generic()
567 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW); in igc_setup_link_generic()
569 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time); in igc_setup_link_generic()
571 return igc_set_fc_watermarks_generic(hw); in igc_setup_link_generic()
575 * igc_config_collision_dist_generic - Configure collision distance
576 * @hw: pointer to the HW structure
581 static void igc_config_collision_dist_generic(struct igc_hw *hw) in igc_config_collision_dist_generic() argument
587 tctl = IGC_READ_REG(hw, IGC_TCTL); in igc_config_collision_dist_generic()
592 IGC_WRITE_REG(hw, IGC_TCTL, tctl); in igc_config_collision_dist_generic()
593 IGC_WRITE_FLUSH(hw); in igc_config_collision_dist_generic()
597 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
598 * @hw: pointer to the HW structure
600 * Sets the flow control high/low threshold (watermark) registers. If
601 * flow control XON frame transmission is enabled, then set XON frame
604 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw) in igc_set_fc_watermarks_generic() argument
610 /* Set the flow control receive threshold registers. Normally, in igc_set_fc_watermarks_generic()
616 if (hw->fc.current_mode & igc_fc_tx_pause) { in igc_set_fc_watermarks_generic()
621 fcrtl = hw->fc.low_water; in igc_set_fc_watermarks_generic()
622 if (hw->fc.send_xon) in igc_set_fc_watermarks_generic()
625 fcrth = hw->fc.high_water; in igc_set_fc_watermarks_generic()
627 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl); in igc_set_fc_watermarks_generic()
628 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth); in igc_set_fc_watermarks_generic()
634 * igc_force_mac_fc_generic - Force the MAC's flow control settings
635 * @hw: pointer to the HW structure
637 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
643 s32 igc_force_mac_fc_generic(struct igc_hw *hw) in igc_force_mac_fc_generic() argument
645 u32 ctrl; in igc_force_mac_fc_generic() local
649 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_force_mac_fc_generic()
651 /* Because we didn't get link via the internal auto-negotiation in igc_force_mac_fc_generic()
653 * auto-neg), we have to manually enable/disable transmit an in igc_force_mac_fc_generic()
654 * receive flow control. in igc_force_mac_fc_generic()
656 * The "Case" statement below enables/disable flow control in igc_force_mac_fc_generic()
657 * according to the "hw->fc.current_mode" parameter. in igc_force_mac_fc_generic()
660 * 0: Flow control is completely disabled in igc_force_mac_fc_generic()
661 * 1: Rx flow control is enabled (we can receive pause in igc_force_mac_fc_generic()
663 * 2: Tx flow control is enabled (we can send pause frames in igc_force_mac_fc_generic()
665 * 3: Both Rx and Tx flow control (symmetric) is enabled. in igc_force_mac_fc_generic()
668 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); in igc_force_mac_fc_generic()
670 switch (hw->fc.current_mode) { in igc_force_mac_fc_generic()
672 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE)); in igc_force_mac_fc_generic()
675 ctrl &= (~IGC_CTRL_TFCE); in igc_force_mac_fc_generic()
676 ctrl |= IGC_CTRL_RFCE; in igc_force_mac_fc_generic()
679 ctrl &= (~IGC_CTRL_RFCE); in igc_force_mac_fc_generic()
680 ctrl |= IGC_CTRL_TFCE; in igc_force_mac_fc_generic()
683 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE); in igc_force_mac_fc_generic()
686 DEBUGOUT("Flow control param set incorrectly\n"); in igc_force_mac_fc_generic()
687 return -IGC_ERR_CONFIG; in igc_force_mac_fc_generic()
690 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_force_mac_fc_generic()
696 * igc_config_fc_after_link_up_generic - Configures flow control after link
697 * @hw: pointer to the HW structure
699 * Checks the status of auto-negotiation after link up to ensure that the
701 * flow control needs to be forced also. If auto-negotiation is enabled
702 * and did not fail, then we configure flow control based on our link
705 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw) in igc_config_fc_after_link_up_generic() argument
707 struct igc_mac_info *mac = &hw->mac; in igc_config_fc_after_link_up_generic()
715 DEBUGOUT("Error forcing flow control settings\n"); in igc_config_fc_after_link_up_generic()
719 /* Check for the case where we have copper media and auto-neg is in igc_config_fc_after_link_up_generic()
720 * enabled. In this case, we need to check and see if Auto-Neg in igc_config_fc_after_link_up_generic()
722 * flow control configured. in igc_config_fc_after_link_up_generic()
724 if (mac->autoneg) { in igc_config_fc_after_link_up_generic()
729 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in igc_config_fc_after_link_up_generic()
732 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); in igc_config_fc_after_link_up_generic()
745 * flow control was negotiated. in igc_config_fc_after_link_up_generic()
747 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, in igc_config_fc_after_link_up_generic()
751 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, in igc_config_fc_after_link_up_generic()
758 * Page Ability Register (Address 5) determine flow control in igc_config_fc_after_link_up_generic()
761 * 1999, describes these PAUSE resolution bits and how flow in igc_config_fc_after_link_up_generic()
767 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up_generic()
778 * Symmetric Flow Control is enabled at both ends. The in igc_config_fc_after_link_up_generic()
781 * For Symmetric Flow Control: in igc_config_fc_after_link_up_generic()
785 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up_generic()
793 * FULL flow control because we could not advertise Rx in igc_config_fc_after_link_up_generic()
797 if (hw->fc.requested_mode == igc_fc_full) { in igc_config_fc_after_link_up_generic()
798 hw->fc.current_mode = igc_fc_full; in igc_config_fc_after_link_up_generic()
799 DEBUGOUT("Flow Control = FULL.\n"); in igc_config_fc_after_link_up_generic()
801 hw->fc.current_mode = igc_fc_rx_pause; in igc_config_fc_after_link_up_generic()
802 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); in igc_config_fc_after_link_up_generic()
809 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up_generic()
816 hw->fc.current_mode = igc_fc_tx_pause; in igc_config_fc_after_link_up_generic()
817 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n"); in igc_config_fc_after_link_up_generic()
823 *-------|---------|-------|---------|-------------------- in igc_config_fc_after_link_up_generic()
830 hw->fc.current_mode = igc_fc_rx_pause; in igc_config_fc_after_link_up_generic()
831 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n"); in igc_config_fc_after_link_up_generic()
833 /* Per the IEEE spec, at this point flow control in igc_config_fc_after_link_up_generic()
836 hw->fc.current_mode = igc_fc_none; in igc_config_fc_after_link_up_generic()
837 DEBUGOUT("Flow Control = NONE.\n"); in igc_config_fc_after_link_up_generic()
840 /* Now we need to do one last check... If we auto- in igc_config_fc_after_link_up_generic()
841 * negotiated to HALF DUPLEX, flow control should not be in igc_config_fc_after_link_up_generic()
844 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); in igc_config_fc_after_link_up_generic()
851 hw->fc.current_mode = igc_fc_none; in igc_config_fc_after_link_up_generic()
854 * controller to use the correct flow control settings. in igc_config_fc_after_link_up_generic()
856 ret_val = igc_force_mac_fc_generic(hw); in igc_config_fc_after_link_up_generic()
858 DEBUGOUT("Error forcing flow control settings\n"); in igc_config_fc_after_link_up_generic()
867 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
868 * @hw: pointer to the HW structure
875 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed, in igc_get_speed_and_duplex_copper_generic() argument
882 status = IGC_READ_REG(hw, IGC_STATUS); in igc_get_speed_and_duplex_copper_generic()
888 if ((hw->mac.type == igc_i225) && in igc_get_speed_and_duplex_copper_generic()
916 * igc_get_hw_semaphore_generic - Acquire hardware semaphore
917 * @hw: pointer to the HW structure
919 * Acquire the HW semaphore to access the PHY or NVM
921 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw) in igc_get_hw_semaphore_generic() argument
924 s32 timeout = hw->nvm.word_size + 1; in igc_get_hw_semaphore_generic()
931 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_generic()
940 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); in igc_get_hw_semaphore_generic()
941 return -IGC_ERR_NVM; in igc_get_hw_semaphore_generic()
946 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_generic()
947 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_generic()
950 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_generic()
958 igc_put_hw_semaphore_generic(hw); in igc_get_hw_semaphore_generic()
960 return -IGC_ERR_NVM; in igc_get_hw_semaphore_generic()
967 * igc_put_hw_semaphore_generic - Release hardware semaphore
968 * @hw: pointer to the HW structure
972 void igc_put_hw_semaphore_generic(struct igc_hw *hw) in igc_put_hw_semaphore_generic() argument
978 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_put_hw_semaphore_generic()
982 IGC_WRITE_REG(hw, IGC_SWSM, swsm); in igc_put_hw_semaphore_generic()
986 * igc_get_auto_rd_done_generic - Check for auto read completion
987 * @hw: pointer to the HW structure
991 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw) in igc_get_auto_rd_done_generic() argument
998 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD) in igc_get_auto_rd_done_generic()
1005 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); in igc_get_auto_rd_done_generic()
1006 return -IGC_ERR_RESET; in igc_get_auto_rd_done_generic()
1013 * igc_disable_pcie_master_generic - Disables PCI-express master access
1014 * @hw: pointer to the HW structure
1016 * Returns IGC_SUCCESS if successful, else returns -10
1017 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1020 * Disables PCI-Express master access and verifies there are no pending
1023 s32 igc_disable_pcie_master_generic(struct igc_hw *hw) in igc_disable_pcie_master_generic() argument
1025 u32 ctrl; in igc_disable_pcie_master_generic() local
1030 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_disable_pcie_master_generic()
1031 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master_generic()
1032 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_disable_pcie_master_generic()
1035 if (!(IGC_READ_REG(hw, IGC_STATUS) & in igc_disable_pcie_master_generic()
1039 timeout--; in igc_disable_pcie_master_generic()
1044 return -IGC_ERR_MASTER_REQUESTS_PENDING; in igc_disable_pcie_master_generic()