Lines Matching +full:hw +full:- +full:flow +full:- +full:ctrl
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 static s32 igc_init_nvm_params_i225(struct igc_hw *hw);
11 static s32 igc_init_mac_params_i225(struct igc_hw *hw);
12 static s32 igc_init_phy_params_i225(struct igc_hw *hw);
13 static s32 igc_reset_hw_i225(struct igc_hw *hw);
14 static s32 igc_acquire_nvm_i225(struct igc_hw *hw);
15 static void igc_release_nvm_i225(struct igc_hw *hw);
16 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw);
17 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
19 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw);
22 * igc_init_nvm_params_i225 - Init NVM func ptrs.
23 * @hw: pointer to the HW structure
25 static s32 igc_init_nvm_params_i225(struct igc_hw *hw) in igc_init_nvm_params_i225() argument
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
28 u32 eecd = IGC_READ_REG(hw, IGC_EECD); in igc_init_nvm_params_i225()
36 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
47 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
48 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
49 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
50 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
53 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
54 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? in igc_init_nvm_params_i225()
57 if (nvm->word_size == (1 << 15)) in igc_init_nvm_params_i225()
58 nvm->page_size = 128; in igc_init_nvm_params_i225()
60 nvm->ops.acquire = igc_acquire_nvm_i225; in igc_init_nvm_params_i225()
61 nvm->ops.release = igc_release_nvm_i225; in igc_init_nvm_params_i225()
62 if (igc_get_flash_presence_i225(hw)) { in igc_init_nvm_params_i225()
63 hw->nvm.type = igc_nvm_flash_hw; in igc_init_nvm_params_i225()
64 nvm->ops.read = igc_read_nvm_srrd_i225; in igc_init_nvm_params_i225()
65 nvm->ops.write = igc_write_nvm_srwr_i225; in igc_init_nvm_params_i225()
66 nvm->ops.validate = igc_validate_nvm_checksum_i225; in igc_init_nvm_params_i225()
67 nvm->ops.update = igc_update_nvm_checksum_i225; in igc_init_nvm_params_i225()
69 hw->nvm.type = igc_nvm_invm; in igc_init_nvm_params_i225()
70 nvm->ops.write = igc_null_write_nvm; in igc_init_nvm_params_i225()
71 nvm->ops.validate = igc_null_ops_generic; in igc_init_nvm_params_i225()
72 nvm->ops.update = igc_null_ops_generic; in igc_init_nvm_params_i225()
79 * igc_init_mac_params_i225 - Init MAC func ptrs.
80 * @hw: pointer to the HW structure
82 static s32 igc_init_mac_params_i225(struct igc_hw *hw) in igc_init_mac_params_i225() argument
84 struct igc_mac_info *mac = &hw->mac; in igc_init_mac_params_i225()
85 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; in igc_init_mac_params_i225()
90 igc_init_mac_ops_generic(hw); in igc_init_mac_params_i225()
93 hw->phy.media_type = igc_media_type_copper; in igc_init_mac_params_i225()
95 mac->mta_reg_count = 128; in igc_init_mac_params_i225()
97 mac->rar_entry_count = IGC_RAR_ENTRIES_BASE; in igc_init_mac_params_i225()
100 mac->ops.reset_hw = igc_reset_hw_i225; in igc_init_mac_params_i225()
101 /* hw initialization */ in igc_init_mac_params_i225()
102 mac->ops.init_hw = igc_init_hw_i225; in igc_init_mac_params_i225()
104 mac->ops.setup_link = igc_setup_link_generic; in igc_init_mac_params_i225()
106 mac->ops.check_for_link = igc_check_for_link_i225; in igc_init_mac_params_i225()
108 mac->ops.get_link_up_info = igc_get_speed_and_duplex_copper_generic; in igc_init_mac_params_i225()
110 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225; in igc_init_mac_params_i225()
112 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225; in igc_init_mac_params_i225()
115 dev_spec->clear_semaphore_once = true; in igc_init_mac_params_i225()
116 mac->ops.setup_physical_interface = igc_setup_copper_link_i225; in igc_init_mac_params_i225()
119 mac->asf_firmware_present = true; in igc_init_mac_params_i225()
122 mac->ops.update_mc_addr_list = igc_update_mc_addr_list_generic; in igc_init_mac_params_i225()
124 mac->ops.write_vfta = igc_write_vfta_generic; in igc_init_mac_params_i225()
130 * igc_init_phy_params_i225 - Init PHY func ptrs.
131 * @hw: pointer to the HW structure
133 static s32 igc_init_phy_params_i225(struct igc_hw *hw) in igc_init_phy_params_i225() argument
135 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_params_i225()
141 if (hw->phy.media_type != igc_media_type_copper) { in igc_init_phy_params_i225()
142 phy->type = igc_phy_none; in igc_init_phy_params_i225()
146 phy->ops.power_up = igc_power_up_phy_copper; in igc_init_phy_params_i225()
147 phy->ops.power_down = igc_power_down_phy_copper_base; in igc_init_phy_params_i225()
149 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500; in igc_init_phy_params_i225()
151 phy->reset_delay_us = 100; in igc_init_phy_params_i225()
153 phy->ops.acquire = igc_acquire_phy_base; in igc_init_phy_params_i225()
154 phy->ops.check_reset_block = igc_check_reset_block_generic; in igc_init_phy_params_i225()
155 phy->ops.release = igc_release_phy_base; in igc_init_phy_params_i225()
156 phy->ops.reset = igc_phy_hw_reset_generic; in igc_init_phy_params_i225()
157 phy->ops.read_reg = igc_read_phy_reg_gpy; in igc_init_phy_params_i225()
158 phy->ops.write_reg = igc_write_phy_reg_gpy; in igc_init_phy_params_i225()
165 ret_val = hw->phy.ops.reset(hw); in igc_init_phy_params_i225()
169 ret_val = igc_get_phy_id(hw); in igc_init_phy_params_i225()
170 phy->type = igc_phy_i225; in igc_init_phy_params_i225()
177 * igc_reset_hw_i225 - Reset hardware
178 * @hw: pointer to the HW structure
182 static s32 igc_reset_hw_i225(struct igc_hw *hw) in igc_reset_hw_i225() argument
184 u32 ctrl; in igc_reset_hw_i225() local
190 * Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_i225()
193 ret_val = igc_disable_pcie_master_generic(hw); in igc_reset_hw_i225()
195 DEBUGOUT("PCI-E Master disable polling has failed.\n"); in igc_reset_hw_i225()
198 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); in igc_reset_hw_i225()
200 IGC_WRITE_REG(hw, IGC_RCTL, 0); in igc_reset_hw_i225()
201 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); in igc_reset_hw_i225()
202 IGC_WRITE_FLUSH(hw); in igc_reset_hw_i225()
206 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_reset_hw_i225()
209 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); in igc_reset_hw_i225()
211 ret_val = igc_get_auto_rd_done_generic(hw); in igc_reset_hw_i225()
222 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); in igc_reset_hw_i225()
223 IGC_READ_REG(hw, IGC_ICR); in igc_reset_hw_i225()
226 ret_val = igc_check_alt_mac_addr_generic(hw); in igc_reset_hw_i225()
231 /* igc_acquire_nvm_i225 - Request for access to EEPROM
232 * @hw: pointer to the HW structure
237 * EEPROM access and return -IGC_ERR_NVM (-1).
239 static s32 igc_acquire_nvm_i225(struct igc_hw *hw) in igc_acquire_nvm_i225() argument
245 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); in igc_acquire_nvm_i225()
250 /* igc_release_nvm_i225 - Release exclusive access to EEPROM
251 * @hw: pointer to the HW structure
256 static void igc_release_nvm_i225(struct igc_hw *hw) in igc_release_nvm_i225() argument
260 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); in igc_release_nvm_i225()
263 /* igc_acquire_swfw_sync_i225 - Acquire SW/FW semaphore
264 * @hw: pointer to the HW structure
270 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) in igc_acquire_swfw_sync_i225() argument
281 if (igc_get_hw_semaphore_i225(hw)) { in igc_acquire_swfw_sync_i225()
282 ret_val = -IGC_ERR_SWFW_SYNC; in igc_acquire_swfw_sync_i225()
286 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); in igc_acquire_swfw_sync_i225()
293 igc_put_hw_semaphore_generic(hw); in igc_acquire_swfw_sync_i225()
300 ret_val = -IGC_ERR_SWFW_SYNC; in igc_acquire_swfw_sync_i225()
305 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); in igc_acquire_swfw_sync_i225()
307 igc_put_hw_semaphore_generic(hw); in igc_acquire_swfw_sync_i225()
313 /* igc_release_swfw_sync_i225 - Release SW/FW semaphore
314 * @hw: pointer to the HW structure
320 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) in igc_release_swfw_sync_i225() argument
326 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) in igc_release_swfw_sync_i225()
329 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); in igc_release_swfw_sync_i225()
331 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); in igc_release_swfw_sync_i225()
333 igc_put_hw_semaphore_generic(hw); in igc_release_swfw_sync_i225()
337 * igc_setup_copper_link_i225 - Configure copper link settings
338 * @hw: pointer to the HW structure
340 * Configures the link for auto-neg or forced speed and duplex. Then we check
342 * and flow control are called.
344 s32 igc_setup_copper_link_i225(struct igc_hw *hw) in igc_setup_copper_link_i225() argument
348 u32 ctrl; in igc_setup_copper_link_i225() local
352 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_setup_copper_link_i225()
353 ctrl |= IGC_CTRL_SLU; in igc_setup_copper_link_i225()
354 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX); in igc_setup_copper_link_i225()
355 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_setup_copper_link_i225()
357 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_setup_copper_link_i225()
359 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); in igc_setup_copper_link_i225()
361 ret_val = igc_setup_copper_link_generic(hw); in igc_setup_copper_link_i225()
366 /* igc_get_hw_semaphore_i225 - Acquire hardware semaphore
367 * @hw: pointer to the HW structure
369 * Acquire the HW semaphore to access the PHY or NVM
371 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) in igc_get_hw_semaphore_i225() argument
374 s32 timeout = hw->nvm.word_size + 1; in igc_get_hw_semaphore_i225()
381 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
393 if (hw->dev_spec._i225.clear_semaphore_once) { in igc_get_hw_semaphore_i225()
394 hw->dev_spec._i225.clear_semaphore_once = false; in igc_get_hw_semaphore_i225()
395 igc_put_hw_semaphore_generic(hw); in igc_get_hw_semaphore_i225()
397 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
407 DEBUGOUT("Driver can't access device -\n"); in igc_get_hw_semaphore_i225()
409 return -IGC_ERR_NVM; in igc_get_hw_semaphore_i225()
415 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
416 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_i225()
419 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_i225()
427 igc_put_hw_semaphore_generic(hw); in igc_get_hw_semaphore_i225()
429 return -IGC_ERR_NVM; in igc_get_hw_semaphore_i225()
435 /* igc_read_nvm_srrd_i225 - Reads Shadow Ram using EERD register
436 * @hw: pointer to the HW structure
444 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, in igc_read_nvm_srrd_i225() argument
457 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? in igc_read_nvm_srrd_i225()
458 IGC_EERD_EEWR_MAX_COUNT : (words - i); in igc_read_nvm_srrd_i225()
459 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_read_nvm_srrd_i225()
460 status = igc_read_nvm_eerd(hw, offset, count, in igc_read_nvm_srrd_i225()
462 hw->nvm.ops.release(hw); in igc_read_nvm_srrd_i225()
474 /* igc_write_nvm_srwr_i225 - Write to Shadow RAM using EEWR
475 * @hw: pointer to the HW structure
486 * If error code is returned, data and Shadow RAM may be inconsistent - buffer
489 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, in igc_write_nvm_srwr_i225() argument
502 count = (words - i) / IGC_EERD_EEWR_MAX_COUNT > 0 ? in igc_write_nvm_srwr_i225()
503 IGC_EERD_EEWR_MAX_COUNT : (words - i); in igc_write_nvm_srwr_i225()
504 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_write_nvm_srwr_i225()
505 status = __igc_write_nvm_srwr(hw, offset, count, in igc_write_nvm_srwr_i225()
507 hw->nvm.ops.release(hw); in igc_write_nvm_srwr_i225()
519 /* __igc_write_nvm_srwr - Write to Shadow Ram using EEWR
520 * @hw: pointer to the HW structure
530 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, in __igc_write_nvm_srwr() argument
533 struct igc_nvm_info *nvm = &hw->nvm; in __igc_write_nvm_srwr()
543 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || in __igc_write_nvm_srwr()
546 ret_val = -IGC_ERR_NVM; in __igc_write_nvm_srwr()
555 IGC_WRITE_REG(hw, IGC_SRWR, eewr); in __igc_write_nvm_srwr()
559 IGC_READ_REG(hw, IGC_SRWR)) { in __igc_write_nvm_srwr()
576 /* igc_validate_nvm_checksum_i225 - Validate EEPROM checksum
577 * @hw: pointer to the HW structure
582 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) in igc_validate_nvm_checksum_i225() argument
589 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_validate_nvm_checksum_i225()
594 read_op_ptr = hw->nvm.ops.read; in igc_validate_nvm_checksum_i225()
595 hw->nvm.ops.read = igc_read_nvm_eerd; in igc_validate_nvm_checksum_i225()
597 status = igc_validate_nvm_checksum_generic(hw); in igc_validate_nvm_checksum_i225()
600 hw->nvm.ops.read = read_op_ptr; in igc_validate_nvm_checksum_i225()
602 hw->nvm.ops.release(hw); in igc_validate_nvm_checksum_i225()
610 /* igc_update_nvm_checksum_i225 - Update EEPROM checksum
611 * @hw: pointer to the HW structure
617 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) in igc_update_nvm_checksum_i225() argument
629 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); in igc_update_nvm_checksum_i225()
635 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_update_nvm_checksum_i225()
636 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read in igc_update_nvm_checksum_i225()
642 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); in igc_update_nvm_checksum_i225()
644 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
651 checksum = (u16)NVM_SUM - checksum; in igc_update_nvm_checksum_i225()
652 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, in igc_update_nvm_checksum_i225()
655 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
660 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
662 ret_val = igc_update_flash_i225(hw); in igc_update_nvm_checksum_i225()
670 /* igc_get_flash_presence_i225 - Check if flash device is detected.
671 * @hw: pointer to the HW structure
673 bool igc_get_flash_presence_i225(struct igc_hw *hw) in igc_get_flash_presence_i225() argument
680 eec = IGC_READ_REG(hw, IGC_EECD); in igc_get_flash_presence_i225()
688 /* igc_set_flsw_flash_burst_counter_i225 - sets FLSW NVM Burst
691 * @hw: pointer to the HW structure
694 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, in igc_set_flsw_flash_burst_counter_i225() argument
703 /* Write FLSWCNT - burst counter */ in igc_set_flsw_flash_burst_counter_i225()
704 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); in igc_set_flsw_flash_burst_counter_i225()
712 /* igc_write_erase_flash_command_i225 - write/erase to a sector
715 * @hw: pointer to the HW structure
719 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode, in igc_write_erase_flash_command_i225() argument
728 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
734 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
735 timeout--; in igc_write_erase_flash_command_i225()
740 return -IGC_ERR_NVM; in igc_write_erase_flash_command_i225()
745 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); in igc_write_erase_flash_command_i225()
748 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
757 /* igc_update_flash_i225 - Commit EEPROM to the flash
763 * @hw: pointer to the HW structure
765 s32 igc_update_flash_i225(struct igc_hw *hw) in igc_update_flash_i225() argument
777 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & in igc_update_flash_i225()
779 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & in igc_update_flash_i225()
782 ret_val = igc_pool_flash_update_done_i225(hw); in igc_update_flash_i225()
783 if (ret_val == -IGC_ERR_NVM) { in igc_update_flash_i225()
788 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; in igc_update_flash_i225()
789 IGC_WRITE_REG(hw, IGC_EECD, flup); in igc_update_flash_i225()
791 ret_val = igc_pool_flash_update_done_i225(hw); in igc_update_flash_i225()
803 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) in igc_update_flash_i225()
807 ret_val = igc_write_erase_flash_command_i225(hw, in igc_update_flash_i225()
820 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, in igc_update_flash_i225()
826 ret_val = igc_write_erase_flash_command_i225(hw, in igc_update_flash_i225()
832 ret_val = igc_read_nvm_eerd(hw, current_offset, in igc_update_flash_i225()
840 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, in igc_update_flash_i225()
845 ret_val = igc_poll_eerd_eewr_done(hw, in igc_update_flash_i225()
857 /* igc_pool_flash_update_done_i225 - Pool FLUDONE status.
858 * @hw: pointer to the HW structure
860 s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) in igc_pool_flash_update_done_i225() argument
862 s32 ret_val = -IGC_ERR_NVM; in igc_pool_flash_update_done_i225()
868 reg = IGC_READ_REG(hw, IGC_EECD); in igc_pool_flash_update_done_i225()
879 /* igc_set_ltr_i225 - Set Latency Tolerance Reporting thresholds.
880 * @hw: pointer to the HW structure
886 static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) in igc_set_ltr_i225() argument
896 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in igc_set_ltr_i225()
901 if ((hw->phy.media_type == igc_media_type_copper) && in igc_set_ltr_i225()
902 !(hw->dev_spec._i225.eee_disable) && in igc_set_ltr_i225()
905 ltrc = IGC_READ_REG(hw, IGC_LTRC) | in igc_set_ltr_i225()
907 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); in igc_set_ltr_i225()
911 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & in igc_set_ltr_i225()
915 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & in igc_set_ltr_i225()
923 size = IGC_READ_REG(hw, IGC_RXPBS) & in igc_set_ltr_i225()
927 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { in igc_set_ltr_i225()
928 size -= (IGC_READ_REG(hw, IGC_DMACR) & in igc_set_ltr_i225()
938 size -= hw->dev_spec._i225.mtu; in igc_set_ltr_i225()
945 return -IGC_ERR_CONFIG; in igc_set_ltr_i225()
963 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); in igc_set_ltr_i225()
967 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); in igc_set_ltr_i225()
970 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); in igc_set_ltr_i225()
974 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); in igc_set_ltr_i225()
981 /* igc_check_for_link_i225 - Check for link
982 * @hw: pointer to the HW structure
988 s32 igc_check_for_link_i225(struct igc_hw *hw) in igc_check_for_link_i225() argument
990 struct igc_mac_info *mac = &hw->mac; in igc_check_for_link_i225()
997 * Auto-Neg has completed and/or if our link status has in igc_check_for_link_i225()
1001 if (!mac->get_link_status) { in igc_check_for_link_i225()
1010 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); in igc_check_for_link_i225()
1021 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); in igc_check_for_link_i225()
1028 mac->get_link_status = false; in igc_check_for_link_i225()
1031 * immediately after link-up in igc_check_for_link_i225()
1033 igc_check_downshift_generic(hw); in igc_check_for_link_i225()
1038 if (!mac->autoneg) in igc_check_for_link_i225()
1041 /* Auto-Neg is enabled. Auto Speed Detection takes care in igc_check_for_link_i225()
1045 mac->ops.config_collision_dist(hw); in igc_check_for_link_i225()
1047 /* Configure Flow Control now that Auto-Neg has completed. in igc_check_for_link_i225()
1048 * First, we need to restore the desired flow control in igc_check_for_link_i225()
1049 * settings because we may have had to re-autoneg with a in igc_check_for_link_i225()
1052 ret_val = igc_config_fc_after_link_up_generic(hw); in igc_check_for_link_i225()
1054 DEBUGOUT("Error configuring flow control\n"); in igc_check_for_link_i225()
1059 ret_val = igc_set_ltr_i225(hw, link); in igc_check_for_link_i225()
1064 /* igc_init_function_pointers_i225 - Init func ptrs.
1065 * @hw: pointer to the HW structure
1069 void igc_init_function_pointers_i225(struct igc_hw *hw) in igc_init_function_pointers_i225() argument
1071 igc_init_mac_ops_generic(hw); in igc_init_function_pointers_i225()
1072 igc_init_phy_ops_generic(hw); in igc_init_function_pointers_i225()
1073 igc_init_nvm_ops_generic(hw); in igc_init_function_pointers_i225()
1074 hw->mac.ops.init_params = igc_init_mac_params_i225; in igc_init_function_pointers_i225()
1075 hw->nvm.ops.init_params = igc_init_nvm_params_i225; in igc_init_function_pointers_i225()
1076 hw->phy.ops.init_params = igc_init_phy_params_i225; in igc_init_function_pointers_i225()
1079 /* igc_init_hw_i225 - Init hw for I225
1080 * @hw: pointer to the HW structure
1082 * Called to initialize hw for i225 hw family.
1084 s32 igc_init_hw_i225(struct igc_hw *hw) in igc_init_hw_i225() argument
1090 ret_val = igc_init_hw_base(hw); in igc_init_hw_i225()
1095 * igc_set_d0_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D0 state
1096 * @hw: pointer to the HW structure
1102 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active) in igc_set_d0_lplu_state_i225() argument
1108 data = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_set_d0_lplu_state_i225()
1118 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); in igc_set_d0_lplu_state_i225()
1123 * igc_set_d3_lplu_state_i225 - Set Low-Power-Link-Up (LPLU) D3 state
1124 * @hw: pointer to the HW structure
1130 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active) in igc_set_d3_lplu_state_i225() argument
1136 data = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_set_d3_lplu_state_i225()
1148 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); in igc_set_d3_lplu_state_i225()
1153 * igc_set_eee_i225 - Enable/disable EEE support
1154 * @hw: pointer to the HW structure
1162 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, in igc_set_eee_i225() argument
1169 if (hw->mac.type != igc_i225 || in igc_set_eee_i225()
1170 hw->phy.media_type != igc_media_type_copper) in igc_set_eee_i225()
1172 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); in igc_set_eee_i225()
1173 eeer = IGC_READ_REG(hw, IGC_EEER); in igc_set_eee_i225()
1176 if (!(hw->dev_spec._i225.eee_disable)) { in igc_set_eee_i225()
1177 u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU); in igc_set_eee_i225()
1206 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); in igc_set_eee_i225()
1207 IGC_WRITE_REG(hw, IGC_EEER, eeer); in igc_set_eee_i225()
1208 IGC_READ_REG(hw, IGC_IPCNFG); in igc_set_eee_i225()
1209 IGC_READ_REG(hw, IGC_EEER); in igc_set_eee_i225()