Lines Matching full:hw

10 static s32 igc_init_nvm_params_i225(struct igc_hw *hw);
11 static s32 igc_init_mac_params_i225(struct igc_hw *hw);
12 static s32 igc_init_phy_params_i225(struct igc_hw *hw);
13 static s32 igc_reset_hw_i225(struct igc_hw *hw);
14 static s32 igc_acquire_nvm_i225(struct igc_hw *hw);
15 static void igc_release_nvm_i225(struct igc_hw *hw);
16 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw);
17 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words,
19 static s32 igc_pool_flash_update_done_i225(struct igc_hw *hw);
23 * @hw: pointer to the HW structure
25 static s32 igc_init_nvm_params_i225(struct igc_hw *hw) in igc_init_nvm_params_i225() argument
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
28 u32 eecd = IGC_READ_REG(hw, IGC_EECD); in igc_init_nvm_params_i225()
62 if (igc_get_flash_presence_i225(hw)) { in igc_init_nvm_params_i225()
63 hw->nvm.type = igc_nvm_flash_hw; in igc_init_nvm_params_i225()
69 hw->nvm.type = igc_nvm_invm; in igc_init_nvm_params_i225()
80 * @hw: pointer to the HW structure
82 static s32 igc_init_mac_params_i225(struct igc_hw *hw) in igc_init_mac_params_i225() argument
84 struct igc_mac_info *mac = &hw->mac; in igc_init_mac_params_i225()
85 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225; in igc_init_mac_params_i225()
90 igc_init_mac_ops_generic(hw); in igc_init_mac_params_i225()
93 hw->phy.media_type = igc_media_type_copper; in igc_init_mac_params_i225()
101 /* hw initialization */ in igc_init_mac_params_i225()
131 * @hw: pointer to the HW structure
133 static s32 igc_init_phy_params_i225(struct igc_hw *hw) in igc_init_phy_params_i225() argument
135 struct igc_phy_info *phy = &hw->phy; in igc_init_phy_params_i225()
141 if (hw->phy.media_type != igc_media_type_copper) { in igc_init_phy_params_i225()
165 ret_val = hw->phy.ops.reset(hw); in igc_init_phy_params_i225()
169 ret_val = igc_get_phy_id(hw); in igc_init_phy_params_i225()
178 * @hw: pointer to the HW structure
182 static s32 igc_reset_hw_i225(struct igc_hw *hw) in igc_reset_hw_i225() argument
193 ret_val = igc_disable_pcie_master_generic(hw); in igc_reset_hw_i225()
198 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); in igc_reset_hw_i225()
200 IGC_WRITE_REG(hw, IGC_RCTL, 0); in igc_reset_hw_i225()
201 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP); in igc_reset_hw_i225()
202 IGC_WRITE_FLUSH(hw); in igc_reset_hw_i225()
206 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_reset_hw_i225()
209 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST); in igc_reset_hw_i225()
211 ret_val = igc_get_auto_rd_done_generic(hw); in igc_reset_hw_i225()
222 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff); in igc_reset_hw_i225()
223 IGC_READ_REG(hw, IGC_ICR); in igc_reset_hw_i225()
226 ret_val = igc_check_alt_mac_addr_generic(hw); in igc_reset_hw_i225()
232 * @hw: pointer to the HW structure
239 static s32 igc_acquire_nvm_i225(struct igc_hw *hw) in igc_acquire_nvm_i225() argument
245 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); in igc_acquire_nvm_i225()
251 * @hw: pointer to the HW structure
256 static void igc_release_nvm_i225(struct igc_hw *hw) in igc_release_nvm_i225() argument
260 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM); in igc_release_nvm_i225()
264 * @hw: pointer to the HW structure
270 s32 igc_acquire_swfw_sync_i225(struct igc_hw *hw, u16 mask) in igc_acquire_swfw_sync_i225() argument
281 if (igc_get_hw_semaphore_i225(hw)) { in igc_acquire_swfw_sync_i225()
286 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); in igc_acquire_swfw_sync_i225()
293 igc_put_hw_semaphore_generic(hw); in igc_acquire_swfw_sync_i225()
305 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); in igc_acquire_swfw_sync_i225()
307 igc_put_hw_semaphore_generic(hw); in igc_acquire_swfw_sync_i225()
314 * @hw: pointer to the HW structure
320 void igc_release_swfw_sync_i225(struct igc_hw *hw, u16 mask) in igc_release_swfw_sync_i225() argument
326 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS) in igc_release_swfw_sync_i225()
329 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC); in igc_release_swfw_sync_i225()
331 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync); in igc_release_swfw_sync_i225()
333 igc_put_hw_semaphore_generic(hw); in igc_release_swfw_sync_i225()
338 * @hw: pointer to the HW structure
344 s32 igc_setup_copper_link_i225(struct igc_hw *hw) in igc_setup_copper_link_i225() argument
352 ctrl = IGC_READ_REG(hw, IGC_CTRL); in igc_setup_copper_link_i225()
355 IGC_WRITE_REG(hw, IGC_CTRL, ctrl); in igc_setup_copper_link_i225()
357 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_setup_copper_link_i225()
359 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg); in igc_setup_copper_link_i225()
361 ret_val = igc_setup_copper_link_generic(hw); in igc_setup_copper_link_i225()
367 * @hw: pointer to the HW structure
369 * Acquire the HW semaphore to access the PHY or NVM
371 static s32 igc_get_hw_semaphore_i225(struct igc_hw *hw) in igc_get_hw_semaphore_i225() argument
374 s32 timeout = hw->nvm.word_size + 1; in igc_get_hw_semaphore_i225()
381 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
393 if (hw->dev_spec._i225.clear_semaphore_once) { in igc_get_hw_semaphore_i225()
394 hw->dev_spec._i225.clear_semaphore_once = false; in igc_get_hw_semaphore_i225()
395 igc_put_hw_semaphore_generic(hw); in igc_get_hw_semaphore_i225()
397 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
415 swsm = IGC_READ_REG(hw, IGC_SWSM); in igc_get_hw_semaphore_i225()
416 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI); in igc_get_hw_semaphore_i225()
419 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI) in igc_get_hw_semaphore_i225()
427 igc_put_hw_semaphore_generic(hw); in igc_get_hw_semaphore_i225()
436 * @hw: pointer to the HW structure
444 s32 igc_read_nvm_srrd_i225(struct igc_hw *hw, u16 offset, u16 words, in igc_read_nvm_srrd_i225() argument
459 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_read_nvm_srrd_i225()
460 status = igc_read_nvm_eerd(hw, offset, count, in igc_read_nvm_srrd_i225()
462 hw->nvm.ops.release(hw); in igc_read_nvm_srrd_i225()
475 * @hw: pointer to the HW structure
489 s32 igc_write_nvm_srwr_i225(struct igc_hw *hw, u16 offset, u16 words, in igc_write_nvm_srwr_i225() argument
504 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_write_nvm_srwr_i225()
505 status = __igc_write_nvm_srwr(hw, offset, count, in igc_write_nvm_srwr_i225()
507 hw->nvm.ops.release(hw); in igc_write_nvm_srwr_i225()
520 * @hw: pointer to the HW structure
530 static s32 __igc_write_nvm_srwr(struct igc_hw *hw, u16 offset, u16 words, in __igc_write_nvm_srwr() argument
533 struct igc_nvm_info *nvm = &hw->nvm; in __igc_write_nvm_srwr()
555 IGC_WRITE_REG(hw, IGC_SRWR, eewr); in __igc_write_nvm_srwr()
559 IGC_READ_REG(hw, IGC_SRWR)) { in __igc_write_nvm_srwr()
577 * @hw: pointer to the HW structure
582 s32 igc_validate_nvm_checksum_i225(struct igc_hw *hw) in igc_validate_nvm_checksum_i225() argument
589 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_validate_nvm_checksum_i225()
594 read_op_ptr = hw->nvm.ops.read; in igc_validate_nvm_checksum_i225()
595 hw->nvm.ops.read = igc_read_nvm_eerd; in igc_validate_nvm_checksum_i225()
597 status = igc_validate_nvm_checksum_generic(hw); in igc_validate_nvm_checksum_i225()
600 hw->nvm.ops.read = read_op_ptr; in igc_validate_nvm_checksum_i225()
602 hw->nvm.ops.release(hw); in igc_validate_nvm_checksum_i225()
611 * @hw: pointer to the HW structure
617 s32 igc_update_nvm_checksum_i225(struct igc_hw *hw) in igc_update_nvm_checksum_i225() argument
629 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data); in igc_update_nvm_checksum_i225()
635 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) { in igc_update_nvm_checksum_i225()
636 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read in igc_update_nvm_checksum_i225()
642 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data); in igc_update_nvm_checksum_i225()
644 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
652 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1, in igc_update_nvm_checksum_i225()
655 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
660 hw->nvm.ops.release(hw); in igc_update_nvm_checksum_i225()
662 ret_val = igc_update_flash_i225(hw); in igc_update_nvm_checksum_i225()
671 * @hw: pointer to the HW structure
673 bool igc_get_flash_presence_i225(struct igc_hw *hw) in igc_get_flash_presence_i225() argument
680 eec = IGC_READ_REG(hw, IGC_EECD); in igc_get_flash_presence_i225()
691 * @hw: pointer to the HW structure
694 s32 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, in igc_set_flsw_flash_burst_counter_i225() argument
704 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter); in igc_set_flsw_flash_burst_counter_i225()
715 * @hw: pointer to the HW structure
719 s32 igc_write_erase_flash_command_i225(struct igc_hw *hw, u32 opcode, in igc_write_erase_flash_command_i225() argument
728 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
734 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
745 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl); in igc_write_erase_flash_command_i225()
748 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL); in igc_write_erase_flash_command_i225()
763 * @hw: pointer to the HW structure
765 s32 igc_update_flash_i225(struct igc_hw *hw) in igc_update_flash_i225() argument
777 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) & in igc_update_flash_i225()
779 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & in igc_update_flash_i225()
782 ret_val = igc_pool_flash_update_done_i225(hw); in igc_update_flash_i225()
788 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225; in igc_update_flash_i225()
789 IGC_WRITE_REG(hw, IGC_EECD, flup); in igc_update_flash_i225()
791 ret_val = igc_pool_flash_update_done_i225(hw); in igc_update_flash_i225()
803 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225) in igc_update_flash_i225()
807 ret_val = igc_write_erase_flash_command_i225(hw, in igc_update_flash_i225()
820 ret_val = igc_set_flsw_flash_burst_counter_i225(hw, in igc_update_flash_i225()
826 ret_val = igc_write_erase_flash_command_i225(hw, in igc_update_flash_i225()
832 ret_val = igc_read_nvm_eerd(hw, current_offset, in igc_update_flash_i225()
840 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA, in igc_update_flash_i225()
845 ret_val = igc_poll_eerd_eewr_done(hw, in igc_update_flash_i225()
858 * @hw: pointer to the HW structure
860 s32 igc_pool_flash_update_done_i225(struct igc_hw *hw) in igc_pool_flash_update_done_i225() argument
868 reg = IGC_READ_REG(hw, IGC_EECD); in igc_pool_flash_update_done_i225()
880 * @hw: pointer to the HW structure
886 static s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) in igc_set_ltr_i225() argument
896 hw->mac.ops.get_link_up_info(hw, &speed, &duplex); in igc_set_ltr_i225()
901 if ((hw->phy.media_type == igc_media_type_copper) && in igc_set_ltr_i225()
902 !(hw->dev_spec._i225.eee_disable) && in igc_set_ltr_i225()
905 ltrc = IGC_READ_REG(hw, IGC_LTRC) | in igc_set_ltr_i225()
907 IGC_WRITE_REG(hw, IGC_LTRC, ltrc); in igc_set_ltr_i225()
911 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) & in igc_set_ltr_i225()
915 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) & in igc_set_ltr_i225()
923 size = IGC_READ_REG(hw, IGC_RXPBS) & in igc_set_ltr_i225()
927 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) { in igc_set_ltr_i225()
928 size -= (IGC_READ_REG(hw, IGC_DMACR) & in igc_set_ltr_i225()
938 size -= hw->dev_spec._i225.mtu; in igc_set_ltr_i225()
963 ltrv = IGC_READ_REG(hw, IGC_LTRMINV); in igc_set_ltr_i225()
967 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv); in igc_set_ltr_i225()
970 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV); in igc_set_ltr_i225()
974 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv); in igc_set_ltr_i225()
982 * @hw: pointer to the HW structure
988 s32 igc_check_for_link_i225(struct igc_hw *hw) in igc_check_for_link_i225() argument
990 struct igc_mac_info *mac = &hw->mac; in igc_check_for_link_i225()
1010 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); in igc_check_for_link_i225()
1021 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link); in igc_check_for_link_i225()
1033 igc_check_downshift_generic(hw); in igc_check_for_link_i225()
1045 mac->ops.config_collision_dist(hw); in igc_check_for_link_i225()
1052 ret_val = igc_config_fc_after_link_up_generic(hw); in igc_check_for_link_i225()
1059 ret_val = igc_set_ltr_i225(hw, link); in igc_check_for_link_i225()
1065 * @hw: pointer to the HW structure
1069 void igc_init_function_pointers_i225(struct igc_hw *hw) in igc_init_function_pointers_i225() argument
1071 igc_init_mac_ops_generic(hw); in igc_init_function_pointers_i225()
1072 igc_init_phy_ops_generic(hw); in igc_init_function_pointers_i225()
1073 igc_init_nvm_ops_generic(hw); in igc_init_function_pointers_i225()
1074 hw->mac.ops.init_params = igc_init_mac_params_i225; in igc_init_function_pointers_i225()
1075 hw->nvm.ops.init_params = igc_init_nvm_params_i225; in igc_init_function_pointers_i225()
1076 hw->phy.ops.init_params = igc_init_phy_params_i225; in igc_init_function_pointers_i225()
1079 /* igc_init_hw_i225 - Init hw for I225
1080 * @hw: pointer to the HW structure
1082 * Called to initialize hw for i225 hw family.
1084 s32 igc_init_hw_i225(struct igc_hw *hw) in igc_init_hw_i225() argument
1090 ret_val = igc_init_hw_base(hw); in igc_init_hw_i225()
1096 * @hw: pointer to the HW structure
1102 s32 igc_set_d0_lplu_state_i225(struct igc_hw *hw, bool active) in igc_set_d0_lplu_state_i225() argument
1108 data = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_set_d0_lplu_state_i225()
1118 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); in igc_set_d0_lplu_state_i225()
1124 * @hw: pointer to the HW structure
1130 s32 igc_set_d3_lplu_state_i225(struct igc_hw *hw, bool active) in igc_set_d3_lplu_state_i225() argument
1136 data = IGC_READ_REG(hw, IGC_I225_PHPM); in igc_set_d3_lplu_state_i225()
1148 IGC_WRITE_REG(hw, IGC_I225_PHPM, data); in igc_set_d3_lplu_state_i225()
1154 * @hw: pointer to the HW structure
1162 s32 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G, in igc_set_eee_i225() argument
1169 if (hw->mac.type != igc_i225 || in igc_set_eee_i225()
1170 hw->phy.media_type != igc_media_type_copper) in igc_set_eee_i225()
1172 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG); in igc_set_eee_i225()
1173 eeer = IGC_READ_REG(hw, IGC_EEER); in igc_set_eee_i225()
1176 if (!(hw->dev_spec._i225.eee_disable)) { in igc_set_eee_i225()
1177 u32 eee_su = IGC_READ_REG(hw, IGC_EEE_SU); in igc_set_eee_i225()
1206 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg); in igc_set_eee_i225()
1207 IGC_WRITE_REG(hw, IGC_EEER, eeer); in igc_set_eee_i225()
1208 IGC_READ_REG(hw, IGC_IPCNFG); in igc_set_eee_i225()
1209 IGC_READ_REG(hw, IGC_EEER); in igc_set_eee_i225()