Lines Matching +full:wakeup +full:- +full:threshold
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
14 /* Definitions for power management and wakeup registers */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
29 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 /* 1000/H is not supported, nor spec-compliant. */
326 #define IGC_TCTL_CT 0x00000ff0 /* collision threshold */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
450 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
490 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
505 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
534 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
554 #define IGC_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
555 #define IGC_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
556 #define IGC_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
776 #define IGC_THSTAT_LOW_EVENT 0x20000000 /* Low thermal threshold */
777 #define IGC_THSTAT_MID_EVENT 0x00200000 /* Mid thermal threshold */
778 #define IGC_THSTAT_HIGH_EVENT 0x00002000 /* High thermal threshold */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1223 /* DMA Coalescing Rx Threshold */
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1233 /* DMA Coalescing Transmit Threshold */
1238 /* Rx Traffic Rate Threshold */
1246 /* Flow ctrl Rx Threshold High val */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out