Lines Matching +full:valid +full:- +full:wakeup +full:- +full:mask
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
14 /* Definitions for power management and wakeup registers */
19 #define IGC_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
20 #define IGC_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
29 #define IGC_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
90 #define IGC_RXD_STAT_IPIDV 0x200 /* IP identification valid */
91 #define IGC_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
106 /* Same mask, but for extended and packet split descriptors */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
159 /* these buffer sizes are valid if IGC_RCTL_BSEX is 0 */
164 /* these buffer sizes are valid if IGC_RCTL_BSEX is 1 */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
217 #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
245 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
486 /* This defines the bits that are set in the Interrupt Mask
501 /* Interrupt Mask Set */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
507 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
519 /* Extended Interrupt Mask Set */
580 #define IGC_RAH_AV 0x80000000 /* Receive descriptor valid */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
617 #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
618 #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
625 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
629 #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */
634 #define IGC_TSYNCTXCTL_TXTT_0 0x00000001 /* Tx timestamp reg 0 valid */
637 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
638 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
670 /* Time Sync Interrupt Cause/Mask Register Bits */
742 #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
744 #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
753 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
754 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
755 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
758 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
948 #define IGC_EECD_SEC1VAL 0x00400000 /* Sector One Valid */
956 #define IGC_EECD_SEC1VAL_I225 0x02000000 /* Sector One Valid */
958 #define IGC_FWSM_FW_VALID_I225 0x8000 /* FW valid bit */
1007 /* Mask bits for fields in Word 0x0f of the NVM */
1012 /* Mask bits for fields in Word 0x1a of the NVM */
1015 /* Mask bits for fields in Word 0x03 of the EEPROM */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1098 /* Bit definitions for valid PHY IDs.
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1355 #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */