Lines Matching +full:sync +full:- +full:update +full:- +full:mask
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
107 /* Same mask, but for extended and packet split descriptors */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
218 #define IGC_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
246 #define IGC_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
279 /* 1000/H is not supported, nor spec-compliant. */
329 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
346 /* GPY211 - I225 defines */
461 #define IGC_ICR_TS 0x00080000 /* Time Sync Interrupt */
465 #define IGC_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
487 /* This defines the bits that are set in the Interrupt Mask
502 /* Interrupt Mask Set */
507 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
508 #define IGC_ITR_VAL_MASK 0x04 /* ITR value mask */
513 #define IGC_IMS_TS IGC_ICR_TS /* Time Sync Interrupt */
515 #define IGC_IMS_DOUTSYNC IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
520 /* Extended Interrupt Mask Set */
605 /* Loop limit on how long we wait for auto-negotiation to complete */
618 #define IGC_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
619 #define IGC_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
626 #define IGC_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
627 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
630 #define IGC_RXCW_CW 0x0000ffff /* RxConfigWord mask */
639 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
671 /* Time Sync Interrupt Cause/Mask Register Bits */
743 #define IGC_TTQF_DISABLE_MASK 0xF0008000 /* TTQF Disable Mask */
745 #define IGC_TTQF_PROTOCOL_MASK 0xFF /* TTQF Protocol Mask */
754 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
755 #define IGC_TTQF_MASK_ENABLE 0x10000000 /* TTQF Mask Enable Bit */
756 #define IGC_IMIR_CLEAR_MASK 0xF001FFFF /* IMIR Reg Clear Mask */
759 #define IGC_IMIREXT_CLEAR_MASK 0x7FFFF /* IMIREXT Reg Clear Mask */
881 /* 1000BASE-T Control Register */
897 /* 1000BASE-T Status Register */
920 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
921 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
947 #define IGC_EECD_FLUPD 0x00080000 /* Update FLASH */
948 #define IGC_EECD_AUPDEN 0x00100000 /* Ena Auto FLASH update */
952 #define IGC_EECD_FLUPD_I225 0x00800000 /* Update FLASH */
953 #define IGC_EECD_FLUDONE_I225 0x04000000 /* Update FLASH done */
1008 /* Mask bits for fields in Word 0x0f of the NVM */
1013 /* Mask bits for fields in Word 0x1a of the NVM */
1016 /* Mask bits for fields in Word 0x03 of the EEPROM */
1031 /* NVM Commands - Microwire */
1038 /* NVM Commands - SPI */
1042 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1070 /* PCI/PCI-X/PCI-EX Config space */
1096 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1129 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1140 * 1 = 50-80M
1141 * 2 = 80-110M
1142 * 3 = 110-140M
1171 * 15-5: page
1172 * 4-0: register offset
1190 /* Page 193 - Port Control Registers */
1195 /* Page 194 - KMRN Registers */
1209 #define IGC_N0_QUEUE -1
1231 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1260 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1264 /* Minimum time for 100BASE-T where no data will be transmit following move out
1356 #define IGC_STATUS_LAN_ID_MASK 0x00000000C /* Mask for Lan ID field */