Lines Matching +full:rx +full:- +full:queue +full:- +full:2
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
153 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
160 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
161 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
162 #define IGC_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
163 #define IGC_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
165 #define IGC_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
166 #define IGC_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
167 #define IGC_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
198 #define IGC_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */
211 #define IGC_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
225 #define IGC_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
246 #define IGC_STATUS_FUNC_SHIFT 2
266 #define FULL_DUPLEX 2
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
332 #define IGC_TARC0_ENABLE 0x00000400 /* Enable Tx Queue 0 */
345 /* GPY211 - I225 defines */
447 #define IGC_ICR_TXQE 0x00000002 /* Transmit Queue empty */
449 #define IGC_ICR_RXSEQ 0x00000008 /* Rx sequence error */
450 #define IGC_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
451 #define IGC_ICR_RXO 0x00000040 /* Rx overrun */
452 #define IGC_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
453 #define IGC_ICR_RXCFG 0x00000400 /* Rx /c/ ordered set */
456 #define IGC_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
470 #define IGC_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */
471 #define IGC_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */
472 #define IGC_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */
473 #define IGC_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */
474 #define IGC_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
475 #define IGC_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
476 #define IGC_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
477 #define IGC_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
504 #define IGC_IMS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
505 #define IGC_IMS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
508 #define IGC_IMS_RXO IGC_ICR_RXO /* Rx overrun */
509 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
520 #define IGC_EIMS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
521 #define IGC_EIMS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
522 #define IGC_EIMS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
523 #define IGC_EIMS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
524 #define IGC_EIMS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
525 #define IGC_EIMS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
526 #define IGC_EIMS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
527 #define IGC_EIMS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
533 #define IGC_ICS_RXSEQ IGC_ICR_RXSEQ /* Rx sequence error */
534 #define IGC_ICS_RXDMT0 IGC_ICR_RXDMT0 /* Rx desc min. threshold */
537 #define IGC_EICS_RX_QUEUE0 IGC_EICR_RX_QUEUE0 /* Rx Queue 0 Interrupt */
538 #define IGC_EICS_RX_QUEUE1 IGC_EICR_RX_QUEUE1 /* Rx Queue 1 Interrupt */
539 #define IGC_EICS_RX_QUEUE2 IGC_EICR_RX_QUEUE2 /* Rx Queue 2 Interrupt */
540 #define IGC_EICS_RX_QUEUE3 IGC_EICR_RX_QUEUE3 /* Rx Queue 3 Interrupt */
541 #define IGC_EICS_TX_QUEUE0 IGC_EICR_TX_QUEUE0 /* Tx Queue 0 Interrupt */
542 #define IGC_EICS_TX_QUEUE1 IGC_EICR_TX_QUEUE1 /* Tx Queue 1 Interrupt */
543 #define IGC_EICS_TX_QUEUE2 IGC_EICR_TX_QUEUE2 /* Tx Queue 2 Interrupt */
544 #define IGC_EICS_TX_QUEUE3 IGC_EICR_TX_QUEUE3 /* Tx Queue 3 Interrupt */
582 #define IGC_RAH_MAC_ADDR_LEN 2
587 #define IGC_ERR_PHY 2
604 /* Loop limit on how long we wait for auto-negotiation to complete */
611 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
637 #define IGC_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
638 #define IGC_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
644 #define IGC_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
683 #define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */
693 #define AUX0_SEL_SDP2 (2u << 0) /* Assign SDP2 to auxiliary time stamp 0. */
695 #define AUX0_TS_SDP_EN (1u << 2) /* Enable auxiliary time stamp trigger 0. */
698 #define AUX1_SEL_SDP2 (2u << 3) /* Assign SDP2 to auxiliary time stamp 1. */
709 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
711 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
715 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
719 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
734 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
743 #define IGC_TTQF_QUEUE_ENABLE 0x100 /* TTQF Queue Enable Bit */
752 #define IGC_TTQF_QUEUE_SHIFT 16 /* TTQF Queue Shfit */
753 #define IGC_TTQF_RX_QUEUE_MASK 0x70000 /* TTQF Queue Mask */
766 #define IGC_MEDIA_PORT_OTHER 2
787 #define IGC_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */
791 #define IGC_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */
801 #define IGC_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */
870 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
913 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
961 #define IGC_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */
963 #define IGC_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1165 /* M88EC018 Rev 2 specific DownShift settings */
1170 * 15-5: page
1171 * 4-0: register offset
1185 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21)
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1223 /* DMA Coalescing Rx Threshold */
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1238 /* Rx Traffic Rate Threshold */
1240 /* Rx packet rate in current window */
1243 /* DMA Coal Rx Traffic Current Count */
1246 /* Flow ctrl Rx Threshold High val */
1252 #define IGC_RXPBS_CFG_TS_EN 0x80000000 /* Timestamp in Rx buffer */
1253 #define IGC_RXPBS_SIZE_I210_MASK 0x0000003F /* Rx packet buffer size */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1273 #define IGC_LTRMINV_SCALE_1024 2
1280 #define IGC_LTRMAXV_SCALE_1024 2
1287 #define IGC_RXPBS_SIZE_I225_MASK 0x0000003F /* Rx packet buffer size */
1357 #define IGC_STATUS_LAN_ID_OFFSET 2