Lines Matching +full:rate +full:- +full:lp +full:- +full:ms
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
793 #define IGC_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */
811 #define IGC_EEE_LP_ADV_DEV_I225 7 /* EEE LP Adv Device */
812 #define IGC_EEE_LP_ADV_ADDR_I225 61 /* EEE LP Adv Register */
861 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
862 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP 10T Half Dplx Capable */
863 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP 10T Full Dplx Capable */
864 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP 100TX Half Dplx Capable */
865 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */
866 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
867 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
868 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asym Pause Direction bit */
869 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP detected Remote Fault */
870 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP rx'd link code word */
874 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
875 #define NWAY_ER_PAGE_RXD 0x0002 /* LP 10T Half Dplx Capable */
876 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP 10T Full Dplx Capable */
877 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP 100TX Half Dplx Capable */
878 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP 100TX Full Dplx Capable */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
898 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asym pause direction bit */
899 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
900 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1038 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1238 /* Rx Traffic Rate Threshold */
1240 /* Rx packet rate in current window */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out