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1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
59 #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
157 #define IGC_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
359 #define IGC_CT_SHIFT 4
380 #define ETHERNET_FCS_SIZE 4
403 #define IGC_PBA_8K 0x0008 /* 8KB */
404 #define IGC_PBA_10K 0x000A /* 10KB */
405 #define IGC_PBA_12K 0x000C /* 12KB */
406 #define IGC_PBA_14K 0x000E /* 14KB */
407 #define IGC_PBA_16K 0x0010 /* 16KB */
419 #define IGC_PBA_48K 0x0030 /* 48KB */
420 #define IGC_PBA_64K 0x0040 /* 64KB */
434 #define IFS_RATIO 4
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
569 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */
581 #define IGC_RAL_MAC_ADDR_LEN 4
589 #define IGC_ERR_PARAM 4
604 /* Loop limit on how long we wait for auto-negotiation to complete */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
674 #define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */
684 #define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */
794 #define IGC_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */
858 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
860 /* Link Partner Ability Register (Base Page) */
871 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
915 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
917 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page Tx */
918 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
986 #define NVM_MINOR_SHIFT 4
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1053 (ID_LED_DEF1_DEF2 << 4) | \
1069 /* PCI/PCI-X/PCI-EX Config space */
1085 #define PCIE_LINK_WIDTH_SHIFT 4
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1142 * 4 = >140M
1170 * 15-5: page
1171 * 4-0: register offset
1174 #define GG82563_REG(page, reg) \ argument
1175 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS))
1180 #define GG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) /* Page Select */
1182 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alt Page Select */
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1213 #define IGC_VLANPQF_QUEUE_SEL(_n, q_idx) ((q_idx) << ((_n) * 4))
1214 #define IGC_VLANPQF_P_VALID(_n) (0x1 << (3 + (_n) * 4))
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1248 #define IGC_FCRTC_RTH_COAL_SHIFT 4
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1300 #define IGC_INVM_RECORD_SIZE_IN_BYTES 4
1307 #define IGC_INVM_MAJOR_SHIFT 4